JPH09284114A - Analog input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the space factor of a noise interrupt MOS transistor (TR) by providing two or more P-channel MOS TRs connected in series between input and output terminals and a control means making them conductive or nonconductive so as to interrupt a noise signal in an input signal. SOLUTION: Two PMOS TRs P11, P12 connected in series between terminals IN1 and out in an input channel CN1 form a transfer switching circuit. A PMOS TR P13 and an NMOS TR N13 connected to a base terminal of the TR P11 have a function of interrupting a noise signal inputted by the input terminal IN1 when the CH1 is not selected by controlling the voltage of the base terminal of the TR P11. Since the noise signal is not transmitted to a noise interruption TR P14, it is not required to widen the channel width for the purpose of decreasing the on-resistance of the TR P14. Thus, the area is reduced to nearly 1/150.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an integrated circuit,
The present invention relates to an analog input circuit that is applied to an A / D converter or the like and switches an analog signal.

[0002]

2. Description of the Related Art Conventionally, this type of circuit is disclosed in Japanese Patent Laid-Open No. 64-73.
817, the circuit of which is shown in FIG. In each of a large number of input channels (CH1, CH2 ...), the input terminals (IN1, IN2 ...), the first control signal terminals (PHI1, PHI2 ...), and the control signal terminals are complementary. A second control signal terminal (/ PHI1, / PHI2 ...) To which a specific signal is input, and an output terminal OUT common to all input channels are provided, and each input channel includes six transistors. It is configured.

In the input channel CH1, two PMOS transistors P1 and P2 connected in series and two NMOS transistors N1 and N2 connected in series are connected in parallel between the input terminal IN1 and the output terminal OUT. There is. These transistors P1, P2,
N1 and N2 form a transfer type switching circuit, and the NMOS transistor N3 connected to the midpoint PA of the PMOS transistors P1 and P2 and the PMOS transistor P3 connected to the midpoint NA of the NMOS transistors N1 and N2 are the midpoints. By controlling the potentials of PA and NA, it has a function of blocking a noise signal input to the transfer type switching circuit when CH1 is in the non-selected state.

Next, the operation of the analog input circuit shown in FIG. 10 will be described. When the first control signal terminal PHI1 is set to a low level voltage (hereinafter referred to as L level), the second control signal terminal / PHI1 is set to a high level voltage (hereinafter referred to as H level), so that the MOS transistors N1 and N1 are connected.
2, P1 and P2 are in the ON state, noise blocking transistors N3 and P3 are in the OFF state, and CH1 is in the selected state. In this state, the transistors N1, N2, P
Since 1 and P2 are all in the ON state, the analog signal input to the input terminal IN1 is transmitted to the output terminal OUT.

Next, when the first control signal terminal PHI1 is set to the H level, the transistors N1, N2, P1,
All P2 are in the OFF state, and noise blocking transistor N
3, P3 are turned on, and CH1 is deselected. In this state, the transistors N1, N2, P1, P2
Since all are in the OFF state, the analog signal input to the input terminal IN1 is not transmitted to the output terminal OUT.

FIG. 11 shows the above-mentioned NMOSs connected in series.
A cross-sectional view of the transistors N1 and N2 on the integrated circuit is shown. Now, when the voltage -V lower than the low level power supply voltage (hereinafter referred to as Vss) is input to the input terminal IN1 due to noise or the like when CH1 is in the non-selected state, the NMO
The parasitic bipolar transistor 141 built in the S transistor N1 is turned on, and the potential at the intermediate point NA is V
However, since the noise cutoff transistor P3 is in the ON state, the potential of the intermediate point NA is raised to the high level power supply voltage (hereinafter, referred to as Vcc). Midpoint NA
Is set to Vcc, the parasitic bipolar transistor 1 built in the NMOS transistor N2 in the subsequent stage.
42 and the NMOS transistor N2 are not turned on.

Therefore, when CH1 is in the non-selected state, and when a low voltage of Vss or lower is input to the input terminal IN1 due to noise or the like, the potential of the intermediate point NA is controlled by the noise blocking transistor P3, and the NMOS transistor in the subsequent stage is controlled. N2
Parasitic bipolar transistors 142 and N built in
By holding the MOS transistor N2 in the OFF state, the input noise signal is prevented from affecting the output terminal OUT.

Next, the current flow in the state of FIG. 11 is shown in (1) and (2) of FIG. An equivalent circuit along this current flow is shown in (3) of FIG. FIG.
As shown in (3) of 2, since the noise blocking PMOS transistor P3 and the parasitic bipolar transistor are in the ON state, the respective transistors can be replaced by the ON resistances R1 and R2. Therefore, the potential V at point A
A is given by the following formula.

VA = R2 × (Vcc + V) / (R1 + R2) (Equation 1) As shown in (Equation 1), the on resistance R1 of the noise blocking PMOS transistor P3 is greater than the on resistance R2 of the parasitic bipolar transistor 141. When the resistance value is too large to be ignored, the potential at the intermediate point NA falls below Vcc, and the parasitic bipolar transistor (not shown) built in the second NMOS transistor N2.
Is turned on, the noise signal is transmitted to the output terminal OUT. Therefore, it is necessary to increase the channel width of the noise blocking PMOS transistor P3 and reduce the on-resistance value.

On the other hand, when a signal having a voltage higher than the power supply voltage Vcc is input to the input terminal due to noise or the like, similarly to the above, the noise cut-off transistor N3 of the noise cutoff transistor N3 is prevented so that the noise signal does not affect the output terminal. The on-resistance value also had to be reduced.

[0011]

As described above, in order to stably operate the conventional analog input circuit, the channel width is increased in order to reduce the on-resistance of the two noise blocking MOS transistors. There was a need. Therefore, the occupied area of the noise blocking MOS transistor is inevitably large (about 150 times the area of a normal MOS transistor).

It is an object of the present invention to cut off a noise signal input to an input terminal and reduce an occupied area of a noise cutting MOS transistor in one channel of an analog input circuit in a non-selected state. .

[0013]

In order to achieve the above object, the present invention provides two or more P-channel MOS transistors connected between an input terminal and an output terminal, and all the P-channel MOS transistors. Control means connected to the gate terminal of the transistor for electrically connecting or disconnecting these P-channel MOS transistors (hereinafter referred to as ON / OFF), and two or more Ps connected in series.
The substrate terminals of at least one P-channel MOS transistor other than the P-channel MOS transistor connected to the output terminal of the channel MOS transistor are connected, and the substrate terminals of the P-channel MOS transistor are connected to all of the above. When the P-channel MOS transistor is ON, all the P
Noise blocking means for blocking a noise signal by biasing to a low level voltage when the channel MOS transistor is OFF, and all P channels in which the noise blocking means is not connected to the substrate terminal in the P channel MOS transistor. Power supply means for biasing the substrate terminal of the MOS transistor to a high level voltage.

When two or more MOS transistors connected in series between the input terminal and the output terminal are N-channel MOS transistors instead of the above-mentioned P-channel MOS transistors, all of them are connected in series. N
It is connected to the gate terminal of the channel MOS transistor, and these N channel MOS transistors are turned on / off.
Control means for turning off and connection to at least one N-channel MOS transistor substrate terminal except N-channel MOS transistor connected to output terminal of two or more N-channel MOS transistors connected in series The noise signal is cut off by setting the substrate terminal of the N-channel MOS transistors to a low level voltage when all the N-channel MOS transistors are ON and to a high level voltage when all the N-channel MOS transistors are ON. And a power supply means for biasing the substrate terminals of all N-channel MOS transistors whose substrate terminals in the N-channel MOS transistors are not connected to the noise-blocking means to a low level voltage. Characterize things.

According to the present invention, the power supply voltage V is applied to one channel in a non-selected state of the analog input channel.
When a noise signal larger than cc or a noise signal smaller than Vss is input to the input terminal, the MOS connected to the output terminal of the two or more one conductivity type channel MOS transistors connected in series. By controlling the substrate voltage of the MOS transistor excluding the transistor by using the noise blocking means, this one conductivity type channel MO
The parasitic bipolar transistor built in the one-conductivity-type channel MOS transistor after the S transistor is
By holding in the FF state, it is possible to prevent the input noise signal from affecting the output terminal.

Further, unlike the conventional circuit, since the noise signal is not transmitted through the noise cutoff transistor, it is not necessary to increase the channel width in order to reduce the ON resistance of the noise cutoff transistor.

[0017]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a first embodiment of the present invention. As shown in (1) of FIG. 1, in each of a large number of input channels (CH1, CH2, CH3 ...), input terminals (IN1, IN2, IN3 ...)
And an output terminal OUT common to all the input channels is provided, and the circuit (A100,
A101, A102 ...) is composed of four transistors.

In the input channel CH1, the two PMOS transistors P11 and P12 connected in series between the input terminal IN1 and the output terminal OUT form a transfer type switching circuit and are connected to the substrate terminal of the PMOS transistor P11. The PMOS transistor P13 and the NMOS transistor N13 are PMOS
By controlling the voltage of the substrate terminal of the transistor P11, it has the function of blocking the noise signal input to the input terminal IN1 when CH1 is in the non-selected state.

Next, the circuit operation of FIG. 1A will be described.
When the control signal terminal INA is at L level (CH1 is in the selected state), the PMOS transistors P11, P12, P13 are O
In the N state (CH1 is open), the NMOS transistor N13 is turned off. At this time, since P13 is in the ON state, the substrate potential of P11 is biased to Vcc, and the analog input signal input to the input terminal IN1 is P11,
P12 is transmitted and output as it is to the output terminal OUT.

On the other hand, the control signal terminal INA has an H level (C
When H1 is in non-selected state), PMOS transistor P1
Since 1, P12, and P13 are in the OFF state (CH1 is closed), the analog input signal input to the input terminal IN1 is not output to the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
An equivalent circuit for NA = H is shown in (2) of FIG.
When a noise signal smaller than Vss is input to the input terminal IN1, the parasitic bipolar transistor RP11 built in the PMOS transistors P11 and P11 is turned off.
Since it is in the state, the noise signal does not affect the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
(NA = H), when a noise signal larger than Vss is input to the input terminal IN1, the parasitic bipolar transistor R built in the PMOS transistor P11.
Since P11 is in the ON state and the potential of the input terminal IN1 is pulled to the base voltage Vss of the parasitic bipolar transistor RP11 and becomes Vss + Vthp11 (Vthp11 is the threshold voltage of the parasitic bipolar transistor RP11), the potential at the A10 point serving as the collector is Vss + Vt.
It becomes hp11. In addition, the potential at point A10 (Vss + Vt
Since hp1) is less than or equal to Vcc which is the base voltage of the parasitic bipolar transistor RP12 incorporated in the PMOS transistor P12, the parasitic bipolar transistor RP12 is held in the OFF state. That is, the latter stage does not operate as a parasitic bipolar transistor, but operates as a diode between the base of the transistor RP12 (the substrate of the PMOS transistor P12) and the emitter (point A10).

Therefore, when a noise signal larger than Vss is input to the input terminal IN1 when CH1 is in the non-selected state,
The substrate voltage of the PMOS transistor P11 is biased to Vss by turning on the noise blocking transistor N13, and the potential at the point A10 is made lower than the base voltage (Vcc) of the parasitic bipolar transistor PR12 in the subsequent stage. This noise signal can be blocked by keeping the OFF state. Also, unlike the conventional circuit as described above, since the noise signal does not propagate through the noise cutoff transistor N13, it is not necessary to increase the channel width in order to reduce the on-resistance of the noise cutoff transistor. Therefore, the area of these circuits on the integrated circuit can be reduced to about 4: 600, that is, about 1/150.

Next, a second embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 2, each input channel circuit (B200, B201, B202 ...) Is composed of four transistors.

In one input channel CH1 (circuit B200) among a plurality of input channels, two NMOS transistors N11 and N12 connected in series between the input terminal IN1 and the output terminal OUT are transfer type switching circuits. And the PMOS transistor P14 and the NMOS transistor N14 connected to the substrate terminal of the NMOS transistor N11 are
By controlling the voltage of the substrate terminal of the transistor P11, it has the function of blocking the noise signal input to the input terminal IN1 when CH1 is in the non-selected state.

Next, the circuit operation of FIG. 2A will be described.
When the control signal terminal INA is at the H level (CH1 is in the selected state), the NMOS transistors N11, N12, N14 are O
In the N state, the PMOS transistor P14 is turned off. At this time, since N14 is in the ON state, the substrate potential of N11 is biased to Vss, and the analog input signal input to the input terminal IN1 is transmitted to N11 and N12 and output terminal O.
It is output to the UT as it is.

When the control signal terminal INA is at L level (CH1 is in a non-selected state), NMOS transistors N11 and N1
Since 2 and N14 are turned off, the analog input signal input to the input terminal IN1 is not output to the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
An equivalent circuit for NA = L is shown in (2) of FIG.
When a noise signal larger than Vcc is input to the input terminal IN1, the parasitic bipolar transistor RN11 built in the NMOS transistors N11 and N11 is turned off.
Since it is in the state, the noise signal does not affect the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
(NA = L), when a noise signal smaller than Vcc is input to the input terminal IN1, the parasitic bipolar transistor R built in the NMOS transistor N11.
N11 is in the ON state, the potential of the input terminal IN1 is pulled to the base voltage Vcc of the parasitic bipolar transistor RP20, and becomes Vcc-Vthn11 (Vthn11 is the threshold voltage of the parasitic bipolar transistor RN11). Is Vcc-Vt
It becomes hn11. Further, the potential at the A20 point (Vcc-Vt
hn11) is equal to or higher than the base voltage Vss of the parasitic bipolar transistor RN12 incorporated in the NMOS transistor N2, the parasitic bipolar transistor RN12 is held in the OFF state. That is, therefore, when CH1 is in the non-selected state, Vcc is applied to the input terminal IN1.
When a smaller noise signal is input, the substrate voltage of the NMOS transistor N11 is changed to the noise cutoff transistor P1.
4 is turned on to bias to Vcc, the potential at the point A20 is made higher than the base voltage (Vss) of the parasitic bipolar transistor RN12 in the subsequent stage, and this parasitic bipolar transistor RN12 is held in the OFF state to generate this noise signal. Can be shut off.

Further, unlike the conventional circuit as described above, since the noise signal does not propagate through the noise cutoff transistor P14, it is not necessary to increase the channel width in order to reduce the ON resistance of the noise cutoff transistor P14. . Therefore, in the first embodiment, the area of these circuits on the integrated circuit can be reduced to about 4: 600, that is, about 1/150.

Next, a third embodiment will be described with reference to the drawings. As shown in FIG. 3, the circuit A100 (see FIG. 1) and the circuit B200 (see FIG. 2) are connected in parallel to form one analog input channel CH1. Further, the control signal INA and the control signal / INA have a complementary relationship with each other.

Next, the circuit operation of FIG. 3 will be described. When the control signal INA is at the L level (selected state), the circuit A100 and the circuit B200 are in the selected state as described in the first and second embodiments, and the analog input signal input to the input terminal IN1 is input. Is output to the output terminal OUT.

When the control signal INA is at the H level, as described in the first and second embodiments, the circuit A10 is used.
0 and the circuit B200 are in the non-selected state, and the input terminal IN
The analog input signal input to 1 is not output to the output terminal OUT.

Further, when the control signal INA is at H level (non-selected state), as described in the first and second embodiments, what kind of noise signal is input to the circuit of FIG. Even if input to IN1, this noise signal can be blocked, and the area of these circuits on the integrated circuit can be reduced. In addition, a transfer gate can be formed by connecting the circuits of FIGS. 1 and 2 in parallel, and the equivalent resistance value between the input terminal IN and the output terminal OUT can be made substantially constant.

Next, a fourth embodiment will be described with reference to the drawings. As shown in FIG. 4, in the input channel CH1 which is one of a large number of input channels, 3 connected in series between the input terminal IN1 and the output terminal OUT.
Two PMOS transistors P41 and P42 and P43
Is a transfer type switching circuit, and PMO
PMOS connected to the substrate terminal of the S transistor P42
Transistor P44 and NMOS transistor N44
Controls the voltage of the substrate terminal of the PMOS transistor P42 so that when the CH1 is in the non-selected state, the input terminal I
It has a function of blocking a noise signal input to N1.

Next, the circuit operation of FIG. 4A will be described.
When the control signal terminal INA is at L level (CH1 is in the selected state), the PMOS transistors P41, P42, P43, P
44 is in the ON state (CH1 is open), and the NMOS transistor N44 is in the OFF state. At this time, P44
Is ON, the substrate potential of P42 is biased to Vcc, and the analog input signal input to the input terminal IN1 is transmitted through P41, P42 and P43 and is output to the output terminal OUT as it is.

On the other hand, the control signal terminal INA has an H level (C
When H1 is in non-selected state), PMOS transistor P4
Since 1, P42, P43, and P44 are in the OFF state (CH1 is closed), the analog input signal input to the input terminal IN1 is not output to the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
An equivalent circuit for NA = H is shown in (2) of FIG.
When a noise signal smaller than Vcc is input to the input terminal IN1, the PMOS transistor P41 and the parasitic bipolar transistor RP41 built in P41 are turned off.
Since it is in the state, the noise signal does not affect the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
(NA = H), when a noise signal larger than Vcc is input to the input terminal IN1, the parasitic bipolar transistor R built in the PMOS transistor P41
Since P41 is in the ON state and the potential of the input terminal IN1 is pulled to the base voltage Vcc of the parasitic bipolar transistor RP41 and becomes Vcc + Vthp41 (Vthp41 is the threshold voltage of the parasitic bipolar transistor RP41), the potential at the point A40 serving as the collector is Vcc + Vt.
It becomes hp41.

Therefore, the diode of the base (Vss) and the emitter (point A40) of the parasitic bipolar transistor RP42 built in the PMOS transistor P42 is turned on.
State. Therefore, the potential of A41 does not exceed Vcc, so that the parasitic bipolar transistor RP43 is held in the OFF state.

Therefore, when a noise signal larger than Vcc is input to the input terminal IN1 when CH1 is in the non-selected state,
The substrate voltage of the PMOS transistor P42 is biased to Vss by turning on the noise blocking transistor N44, and the potential at the point A41 is made lower than the base voltage (Vcc) of the parasitic bipolar transistor PR43 in the subsequent stage. This noise signal can be blocked by keeping the OFF state. Also, similar to the above, the area of these circuits on the integrated circuit can be reduced to about 4: 600, or about 1/150.

Further, in (1) of FIG. 1, the input terminal I
There is a case where another circuit, for example, a logic gate 190 is connected to N1, and it is desired to input an H level signal to the logic gate 190 by setting the analog input channel CH1 to the non-selected state and setting the input terminal IN1 to the H level. is there. In this case, the parasitic bipolar transistor RP11 built in the PMOS transistor P11 is turned on (see (2) in FIG. 1), the input voltage IN1 is pulled by the base voltage Vss of the parasitic bipolar transistor RP11, and the input voltage IN1 becomes higher than the H level. Is also a low potential Vss + Vt
It becomes hp11. Therefore, the desired H level potential is not input to the logic gate 190. Like this
There is a problem that the circuit A100 affects other circuits.

On the other hand, in (1) of FIG. 4, the input terminal I
When another circuit such as a logic gate 490 is connected to N1, the H level potential is input to the input terminal IN1 in order to input the H level potential to the logic gate 490.
At this time, the parasitic bipolar transistor RP41 built in the PMOS transistor P41 is not turned on, so that the input H-level signal is not affected by the analog input circuit A400 and is transmitted to the logic gate 490 as it is. Therefore, the circuit of the present embodiment can minimize the area occupied by these circuits and does not affect other circuits even when used in combination with other circuits.

Next, a fifth embodiment will be described with reference to the drawings. As shown in FIG. 5, in the input channel CH1 which is one of a large number of input channels, 3 connected in series between the input terminal IN1 and the output terminal OUT.
Two NMOS transistors N41 and N42 and N43
Is a transfer type switching circuit, NMO
NMOS connected to the substrate terminal of the S transistor N42
Transistor N45 and PMOS transistor P45
Controls the voltage of the substrate terminal of the NMOS transistor N42 so that when the CH1 is in the non-selected state, the input terminal I
It has a function of blocking a noise signal input to N1.

Next, the circuit operation of FIG. 5A will be described.
When the control signal terminal INA is at the H level (CH1 is in the selected state), the NMOS transistors N41, N42, N43, N
45 is in the ON state (CH1 is open), and the PMOS transistor P45 is in the OFF state. At this time, N45
Is ON, the substrate potential of N42 is biased to Vcc, and the analog input signal input to the input terminal IN1 is transmitted through N41, N42 and N43 and is output to the output terminal OUT as it is.

On the other hand, the control signal terminal INA is at the L level (C
When H1 is in non-selected state), NMOS transistor N4
Since 1, N42, N43, and N45 are in the OFF state (CH1 is closed), the analog input signal input to the input terminal IN1 is not output to the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
An equivalent circuit for NA = L is shown in (2) of FIG.
When a noise signal larger than Vss is input to the input terminal IN1, the parasitic bipolar transistor RN41 built in the PMOS transistors N41 and N41 is turned off.
Since it is in the state, the noise signal does not affect the output terminal OUT.

Next, when CH1 is in the non-selected state (control signal I
(NA = L), when a noise signal smaller than Vss is input to the input terminal IN1, the parasitic bipolar transistor R built in the NMOS transistor N41.
N41 is turned on, and the potential of the input terminal IN1 is pulled to the base voltage Vss of the parasitic bipolar transistor RN41 and becomes Vss-Vthn41 (Vthn41 is the threshold voltage of the parasitic bipolar transistor RN41). Is Vss-Vt
It becomes hn41. Therefore, the NMOS transistor N42
Since the base (substrate) -emitter (A50) of the parasitic bipolar transistor RN42 built in is forward-biased, it operates as a diode. Therefore, A51
Since the potential at the point does not become lower than Vss which is the base voltage of the parasitic bipolar transistor RN43 built in the NMOS transistor N43, the parasitic bipolar transistor RN43 is held in the OFF state.

Therefore, when a noise signal smaller than Vss is input to the input terminal IN1 when CH1 is in the non-selected state,
The substrate voltage of the NMOS transistor N42 is biased to Vcc by turning on the noise blocking transistor P45, and the potential at the point A51 is made higher than the base voltage (Vss) of the parasitic bipolar transistor PN43 in the subsequent stage. Turn off RN43
This noise signal can be cut off by maintaining the state. Further, the circuit of the present embodiment can reduce the area of these circuits on the integrated circuit to about 4: 600, that is, about 1/150, as in the above, and when used in combination with other circuits. Does not affect other circuits.

Next, a sixth embodiment will be described with reference to the drawings. As shown in FIG. 6, one analog input channel CH1 is formed by connecting the circuit A400 (see FIG. 4) and the circuit B500 (see FIG. 5) in parallel. Further, the control signal INA and the control signal / INA have a complementary relationship with each other.

Next, the circuit operation of FIG. 6 will be described. When the control signal INA is at the L level (selected state), the circuits A400 and B500 are in the selected state, and the analog input signal input to the input terminal IN1 is output to the output terminal OUT.

When the control signal INA is at H level, the circuit A4
00 and the circuit B500 are in the non-selected state, and the input terminal I
The analog input signal input to N1 is not output to the output terminal OUT.

When the control signal INA is at the H level (non-selected state), as described above, in the circuit of this embodiment, the noise signal of Vcc or more or Vss or less is input to the input terminal INA in the circuit of FIG. Even if this occurs, this noise signal can be blocked, the area of these circuits on the integrated circuit can be reduced, and when used in combination with other circuits, the circuit of this embodiment does not affect other circuits. Further, similarly to the above, the transfer gate can be formed by connecting the circuit B500 and the circuit A400 in parallel, and the equivalent resistance value between the input terminal IN and the output terminal OUT can be made substantially constant.

The tenth embodiment is shown in (1) to (3) of FIG. When only a noise signal of Vcc or higher is input to the input terminal IN1, the analog input circuit is the circuit X10 (for example, the circuits A100, A
400, A700) and a circuit Y10 (for example, one or a plurality of transistors) that has not been subjected to noise blocking measures.

The eleventh embodiment is shown in (1) to (3) of FIG. When only a noise signal equal to or lower than Vss is input to the input terminal IN1, the analog input circuit includes a circuit X11 (for example, one or a plurality of transistors) that does not take noise blocking measures and a circuit Y11 (for example, one or more transistors) that does not take noise blocking measures. , Circuits B200, B500, B80
0) and may be included.

Further, according to the present invention, when the channel circuit is in the non-selected state, by controlling the substrate voltage of one of a plurality of transistors connected in series,
The parasitic bipolar transistor built in the transistor at the subsequent stage of the transistor whose substrate voltage is controlled is
By holding the FF state, the noise signal is blocked. Therefore, as shown in (1) to (3) of FIG. 9, a large number of transistors connected in series may be used.
For the above reason, the noise blocking circuit Z may be located anywhere except the transistor (PN) closest to the output terminal OUT.

[0057]

According to the present invention, in one channel in the non-selected state of the analog input circuit, the noise signal input to the input terminal can be cut off, and the area occupied by the noise cutting MOS transistor can be reduced. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram of a tenth embodiment of the present invention.

FIG. 8 is an eleventh embodiment diagram of the present invention.

FIG. 9 is a circuit diagram of a twelfth embodiment of the present invention.

FIG. 10 is a circuit diagram of a conventional embodiment.

FIG. 11 shows Ps connected in series in the conventional embodiment.
Cross-sectional view of MOS transistor on integrated circuit

FIG. 12 is a diagram showing a current flow in a circuit diagram of a conventional embodiment.

[Explanation of symbols]

IN1, IN2, IN3 input terminals PHI1, PHI2, INA first control signal terminal / PHI1, / PHI2, / INA second control signal terminal OUT output terminals P1 to PN, P11 to P14, P41 to P44 P channel MOS transistor N1 to NN, N11 to N14, N41 to N44 N channel MOS transistors 141, 142, PR11, PR12, PN11, PN
12, RP41 to RP43, RN41 to RN44 Parasitic bipolar transistor CH1, CH2, CH3 Input channel A100, A101, A102 Input channel circuit SW1 to SW4 switches

Claims (15)

[Claims] 1. An input terminal to which an analog signal is input, an output terminal for outputting the analog signal input to the input terminal, and two terminals connected in series between the input terminal and the output terminal. The above P-channel MOS transistors, the control means connected to the gate terminals of all the P-channel MOS transistors connected in series and for turning on / off these P-channel MOS transistors, and the serial connection A substrate terminal of at least one P-channel MOS transistor other than the P-channel MOS transistor connected to the output terminal of two or more P-channel MOS transistors, and a substrate terminal of the P-channel MOS transistor To
Noise blocking means for blocking noise signals by biasing to a high level voltage when all the P-channel MOS transistors are ON and to a low level voltage when all the P-channel MOS transistors are OFF; All P channels M in which noise blocking means are not connected to the substrate terminals in the MOS transistors
An analog input circuit having a power supply means for biasing a substrate terminal of an OS transistor to a high level voltage. 2. An input terminal to which an analog signal is input, an output terminal for outputting the analog signal input to the input terminal, and two terminals connected in series between the input terminal and the output terminal. The above N-channel MOS transistors, control means connected to the gate terminals of all the N-channel MOS transistors connected in series, and for turning ON / OFF these N-channel MOS transistors, and the above-mentioned series-connected Connected to the substrate terminal of at least one N-channel MOS transistor excluding the N-channel MOS transistor connected to the output terminal of the two or more N-channel MOS transistors,
Noise for interrupting a noise signal by setting the substrate terminal of the channel MOS transistor to a low level voltage when all the N channel MOS transistors are ON and to a high level voltage when all the N channel MOS transistors are ON Blocking means and all N-channel M's in which the noise blocking means is not connected to the substrate terminal in the N-channel MOS transistor
An analog input circuit having a power supply means for biasing a substrate terminal of an OS transistor to a low level voltage. 3. An input terminal to which an analog signal is input, an output terminal for outputting the analog signal input to the input terminal, and two terminals connected in series between the input terminal and the output terminal. The above P-channel MOS transistors, two or more N-channel MOS transistors connected in series between an input terminal for inputting an analog signal and an output terminal for outputting an analog signal, and all the N-channel MOS transistors connected in series First control means connected to the gate terminals of the P-channel MOS transistors for turning ON / OFF these P-channel MOS transistors, and connected to the gate terminals of all the N-channel MOS transistors connected in series, These N-channel MOS transistors are turned on / off to provide a signal complementary to the first control means. Second control means for outputting and at least one P-channel MOS transistor substrate terminal excluding a P-channel MOS transistor connected to an output terminal of the two or more P-channel MOS transistors connected in series For all P
First noise blocking means for blocking a noise signal by biasing to a high level voltage when the channel MOS transistors are ON and to a low level voltage when all the P channel MOS transistors are OFF, and connected in series Low level voltage when at least one of the N-channel MOS transistors is ON, the substrate terminal of at least one N-channel MOS transistor except the N-channel MOS transistor connected to the output terminal of the two or more N-channel MOS transistors And all the N-channel MOS transistors are O
Second noise blocking means for blocking a noise signal by biasing to a high level voltage in the case of FF, and all Ps in which the first noise blocking means is not connected to the substrate terminal in the P channel MOS transistor. First power supply means for biasing the substrate terminal of the channel MOS transistor to a high level voltage, and all N channel MOS transistors in which the second noise blocking means is not connected to the substrate terminal of the N channel MOS transistors An analog input circuit having a second power supply means for biasing the substrate terminal of the substrate to a low level voltage. 4. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first P-channel MOS transistor, A second P-channel MOS transistor in which a drain terminal is connected to an output terminal for outputting an analog signal input to the input terminal and a substrate terminal is connected to a high-level power supply voltage terminal; and the first and second P-channels Control means connected to the gate terminal of the MOS transistor for turning on / off these P channel MOS transistors, and the first and second P channel M by the control means.
When a high level voltage is applied to the gate terminal of the OS transistor, the voltage of the substrate terminal of the first P-channel MOS transistor is set to a low level voltage, and the control means controls the gates of the first and second P-channel MOS transistors. An analog input circuit comprising: means for setting the voltage of the substrate terminal of the first P-channel MOS transistor to a high level voltage when a low level voltage is applied to the terminal. 5. An input terminal for inputting an analog signal, a first N-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first N-channel MOS transistor, A second N-channel MOS transistor having a drain terminal connected to an output terminal for outputting an analog signal input to the input terminal and a substrate terminal connected to a low-level power supply voltage terminal; and the first and second N-channels Control means connected to the gate terminals of the MOS transistors for turning ON / OFF these N-channel MOS transistors, and the first and second N-channel M by the control means.
When a high level voltage is applied to the gate terminal of the OS transistor, the voltage of the substrate terminal of the first N-channel MOS transistor is set to a low level voltage, and the control means controls the gates of the first and second N-channel MOS transistors. An analog input circuit comprising: means for setting the voltage of the substrate terminal of the first N-channel MOS transistor to a high level voltage when a low level voltage is applied to the terminal. 6. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first P-channel MOS transistor, A second P-channel MOS transistor in which a drain terminal is connected to an output terminal for outputting an analog signal input to the input terminal and a substrate terminal is connected to a high-level power supply voltage terminal; and the first and second P-channels First control means connected to the gate terminal of the MOS transistor for turning on / off these P channel MOS transistors; and the first P channel when a high level voltage is applied to the first control means. A low level voltage is applied to the substrate terminal of the MOS transistor and a low level voltage is applied to the control signal terminal. Wherein when applied first P-channel MO
Means for setting the voltage of the substrate terminal of the S-transistor to a high level voltage, a first N-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal of the first N-channel MOS transistor drain A drain terminal, an output terminal for outputting an analog signal input to the input terminal, and a substrate terminal connected to the low level power supply voltage terminal;
A channel MOS transistor and a second terminal which is connected to the gate terminals of the first and second N-channel MOS transistors, turns on / off these N-channel MOS transistors, and has a complementary relationship with the first control means. And the second control means applies a high level voltage to the gate terminals of the first and second N-channel MOS transistors to lower the voltage of the substrate terminal of the first N-channel MOS transistor. The level voltage is applied to the first and second N-channel MOs by the second control means.
An analog input circuit having means for biasing the voltage of the substrate terminal of the first N-channel MOS transistor to a high level voltage when a low level voltage is applied to the gate terminal of the S transistor. 7. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a high-level power supply voltage terminal, and a source terminal for the first P-channel MOS transistor. Second P-channel MO connected to the drain terminal of the P-channel MOS transistor of
An S transistor, a source terminal to the drain terminal of the second P-channel MOS transistor, a drain terminal to an output terminal for outputting an analog signal input to an input terminal, and a substrate terminal to the high-level power supply voltage terminal. Third P connected
A channel MOS transistor, control means connected to the gate terminals of the first to third P-channel MOS transistors, for turning ON / OFF these P-channel MOS transistors, and the first to third control means by the control means. P channel M
When a high level voltage is applied to the gate terminal of the OS transistor, the voltage of the substrate terminal of the second P channel MOS transistor is set to a low level voltage, and the control means controls the gates of the first to third P channel MOS transistors. An analog input circuit having means for biasing the voltage of the substrate terminal of the second P-channel MOS transistor to a high level voltage when a low level voltage is applied to the terminal. 8. An input terminal for inputting an analog signal, a first N-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a low level power supply voltage terminal, and a source terminal for the first N-channel MOS transistor. Second N-channel MO connected to the drain terminal of the N-channel MOS transistor of
An S transistor, a source terminal to the drain terminal of the second N-channel MOS transistor, a drain terminal to an output terminal for outputting an analog signal input to an input terminal, and a substrate terminal to the low level power supply voltage terminal. Third N connected
A channel MOS transistor, control means connected to the gate terminals of the first to third N-channel MOS transistors, for turning ON / OFF these N-channel MOS transistors, and the first to third control means by the control means. N channel M
When a high level voltage is applied to the gate terminal of the OS transistor, the voltage of the substrate terminal of the second N-channel MOS transistor is set to a low level voltage, and the control means controls the gates of the first to third N-channel MOS transistors. And a means for biasing the voltage of the substrate terminal of the second N-channel MOS transistor to a high level voltage when a low level voltage is applied to the terminal. 9. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a high level power supply voltage terminal, and a source terminal for the first P-channel MOS transistor. A drain terminal of the P-channel MOS transistor, a second P-channel MOS transistor, a source terminal to the drain terminal of the second P-channel MOS transistor, and a drain terminal to an output terminal for outputting an analog signal; A third P-channel MOS transistor whose terminal is connected to the high-level power supply voltage terminal and gate terminals of the first to third P-channel MOS transistors are connected to turn ON / OFF these P-channel MOS transistors. A first control means for, and by the first control means When a high-level voltage is applied to the gate terminals of the first to third P-channel MOS transistors, the voltage of the substrate terminal of the second P-channel MOS transistor is set to a low-level voltage, and the first control means controls the first To third P channel MO
Means for biasing the voltage of the substrate terminal of the second P-channel MOS transistor to a high level voltage when a low level voltage is applied to the gate terminal of the S-transistor; A first N-channel MOS transistor connected to a low level power supply voltage terminal and a second N-channel MO whose source terminal is connected to the drain terminal of the first N-channel MOS transistor.
An S transistor, a source terminal to the drain terminal of the second N-channel MOS transistor, a drain terminal to the output terminal,
A substrate terminal is connected to a third N-channel MOS transistor whose low-level power supply voltage terminal is connected, and gate terminals of the first to third N-channel MOS transistors, which are turned on / off, Second control means complementary to the control means, and the second control means when the high level voltage is applied to the gate terminals of the first to third N-channel MOS transistors by the second control means. The voltage of the substrate terminal of the N-channel MOS transistor is set to a low level voltage by the second control means.
An analog input circuit having means for biasing the voltage of the substrate terminal of the second N-channel MOS transistor to a high level voltage when a low level voltage is applied to the gate terminal of the S transistor. 10. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first P-channel MOS transistor, A second P-channel MOS transistor having a drain terminal for outputting an analog signal input to an input terminal and a substrate terminal connected to a high-level power supply voltage terminal; and the first to second P-channels Control means connected to the gate terminals of the MOS transistors to turn on / off these P-channel MOS transistors, a drain terminal to the substrate terminal of the first P-channel MOS transistor, and a source terminal and a substrate terminal to the high terminal. Is connected to the level power supply voltage terminal and is connected to the first P channel MOS transistor. A third P-channel MOS transistor for controlling the substrate voltage of the registers, the source terminal and the substrate terminal to a low level power supply voltage terminal,
A gate terminal connected to the control means, a drain terminal connected to a substrate terminal of the first P-channel MOS transistor, and an N-channel MOS transistor for controlling the substrate voltage of the first P-channel MOS transistor. An analog input circuit characterized by. 11. An input terminal for inputting an analog signal, a first N-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first N-channel MOS transistor, A second N-channel MOS transistor having a drain terminal connected to an output terminal for outputting an analog signal input to an input terminal, and a substrate terminal connected to a low-level power supply voltage terminal; and the first to second N-channels Control means connected to the gate terminals of the MOS transistors for turning on / off these N-channel MOS transistors; a drain terminal for the substrate terminal of the first N-channel MOS transistor; and a gate terminal for the control means. A source terminal and a substrate terminal are connected to the low level power supply voltage terminal, A third N-channel MOS transistor for controlling the substrate voltage of one N-channel MOS transistor, the source terminal and the substrate terminal to the high level power supply voltage terminal,
A gate terminal connected to the control means, a drain terminal connected to a substrate terminal of the first N-channel MOS transistor, and a P-channel MOS transistor for controlling the substrate voltage of the first N-channel MOS transistor. An analog input circuit characterized by. 12. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal, and a source terminal for a drain terminal of the first P-channel MOS transistor, A second P-channel MOS transistor having a drain terminal for outputting an analog signal input to an input terminal and a substrate terminal connected to a high-level power supply voltage terminal; and the first to second P-channels First control means connected to the gate terminals of the MOS transistors for turning ON / OFF these P-channel MOS transistors; a drain terminal for the substrate terminal of the first P-channel MOS transistor; and a gate terminal for the first P-channel MOS transistor. The source terminal and the substrate terminal are connected to the high-level power supply voltage terminal to one control means. Is, in the third P-channel MOS transistor and the source terminal and the substrate terminal is low level power supply voltage terminal for controlling a substrate voltage of said first P-channel MOS transistors,
A gate terminal is connected to the first control signal terminal, and a drain terminal is connected to the substrate terminal of the first P-channel MOS transistor, and a first N-channel for controlling the substrate voltage of the first P-channel MOS transistor. Channel M
An OS transistor, a second N-channel MOS transistor whose source terminal is connected to the input terminal, and a source terminal which is the second N-channel MOS transistor.
A drain terminal of the channel MOS transistor, a drain terminal for outputting an analog signal input to an input terminal, and a third N-channel MOS transistor having a substrate terminal connected to the low level power supply voltage terminal; Second control means connected to the gate terminals of the first to second N-channel MOS transistors, turning these N-channel MOS transistors ON / OFF, and having a complementary relationship with the first control means; The drain terminal is connected to the substrate terminal of the second N-channel MOS transistor, the gate terminal is connected to the second control means, and the source terminal and the substrate terminal are connected to the low level power supply voltage terminal, and the second N-channel MOS transistor is connected. A fourth N-channel MOS transistor for controlling the substrate voltage of the transistor, Over scan terminals and the substrate terminals to a high level power supply voltage terminal,
A fourth P-channel for controlling the substrate voltage of the second N-channel MOS transistor, the gate terminal of which is connected to the second control means and the drain terminal of which is connected to the substrate terminal of the second N-channel MOS transistor. MOS
An analog input circuit having a transistor. 13. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a high level power supply voltage terminal, and a source terminal for the first P-channel MOS transistor. Second P-channel MO connected to the drain terminal of the P-channel MOS transistor of
An S transistor, a source terminal to the drain terminal of the second P-channel MOS transistor, a drain terminal to an output terminal for outputting an analog signal input to an input terminal, and a substrate terminal to the high-level power supply voltage terminal. Third P connected
A channel MOS transistor, control means connected to the gate terminals of the first to third P-channel MOS transistors, for turning ON / OFF these P-channel MOS transistors, and a source and a substrate terminal are the high-level power supply voltage. To the terminal
A fourth P-channel MOS transistor for controlling the substrate voltage of the second P-channel MOS transistor, the gate terminal of which is connected to the control means and the drain terminal of which is connected to the substrate terminal of the second P-channel MOS transistor. , The source and substrate terminals are low-level power supply voltage terminals, the gate terminal is the control means, and the drain terminal is the second P-terminal.
Connected to the substrate terminal of the channel MOS transistor,
An analog input circuit having an N-channel MOS transistor for controlling the substrate voltage of the second P-channel MOS transistor. 14. An input terminal to which an analog signal is input, a source terminal connected to the input terminal, a substrate terminal connected to a low level power supply voltage terminal, and a first N-channel MOS transistor, and a source terminal connected to the first terminal. Second N-channel MO connected to the drain terminal of the N-channel MOS transistor of
An S transistor, a source terminal to the drain terminal of the second N-channel MOS transistor, a drain terminal to an output terminal for outputting an analog signal input to an input terminal, and a substrate terminal to the low level power supply voltage terminal. Third N connected
A channel MOS transistor, control means connected to the gate terminals of the first to third N-channel MOS transistors, for turning ON / OFF these N-channel MOS transistors, and a source and a substrate terminal are the low-level power supply voltage. To the terminal
A fourth N-channel MOS transistor for controlling the substrate voltage of the second N-channel MOS transistor, the gate terminal of which is connected to the control means and the drain terminal of which is connected to the substrate terminal of the second N-channel MOS transistor. , The source and substrate terminals are high-level power supply voltage terminals, the gate terminal is the control means, and the drain terminal is the second N-terminal.
Connected to the substrate terminal of the channel MOS transistor,
An analog input circuit having a P-channel MOS transistor for controlling the substrate voltage of the second N-channel MOS transistor. 15. An input terminal for inputting an analog signal, a first P-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a high-level power supply voltage terminal, and a source terminal for the first P-channel MOS transistor. Second P-channel MO connected to the drain terminal of the P-channel MOS transistor of
An S transistor, a source terminal connected to the drain terminal of the second P-channel MOS transistor, a drain terminal connected to an output terminal for outputting an analog signal, and a substrate terminal connected to the high level power supply voltage terminal. A P-channel MOS transistor, first control means connected to the gate terminals of the first to third P-channel MOS transistors, for turning ON / OFF these P-channel MOS transistors, and a source and a substrate terminal are provided. High-level power supply voltage terminal,
A gate terminal is connected to the first control means and a drain terminal is connected to the substrate terminal of the second P-channel MOS transistor, and a fourth P-channel for controlling the substrate voltage of the second P-channel MOS transistor. MOS
The transistor, the source and substrate terminals are connected to the low level power supply voltage terminal, the gate terminal is connected to the first control means, and the drain terminal is connected to the substrate terminal of the second P channel MOS transistor, and the second P channel is connected. A first N-channel MOS transistor for controlling the substrate voltage of the MOS transistor, a second N-channel MOS transistor having a source terminal connected to the input terminal and a substrate terminal connected to a low level power supply voltage terminal, and a source terminal Is a third N-channel MO connected to the drain terminal of the second N-channel MOS transistor
An S transistor, a source terminal to the drain terminal of the third N-channel MOS transistor, a drain terminal to the output terminal,
A substrate terminal is connected to a fourth N-channel MOS transistor whose substrate terminal is connected to the low-level power supply voltage terminal and gate terminals of the first to third N-channel MOS transistors, and these N-channel MOS transistors are turned on / off. The second control means having a complementary relationship with the first control means, and the source and substrate terminals to the low level power supply voltage terminal,
A fifth N-channel for controlling the substrate voltage of the third N-channel MOS transistor, the gate terminal of which is connected to the second control means and the drain terminal of which is connected to the substrate terminal of the third N-channel MOS transistor. MOS
A transistor, a source and a substrate terminal are connected to a high level power supply voltage terminal, a gate terminal is connected to the second control means, and a drain terminal is connected to a substrate terminal of the third N-channel MOS transistor, and the third N-channel is connected. An analog input circuit having a fifth P-channel MOS transistor for controlling the substrate voltage of the MOS transistor.