US9590674B2 - Semiconductor devices with switchable ground-body connection - Google Patents

Semiconductor devices with switchable ground-body connection Download PDF

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US9590674B2
US9590674B2 US13715805 US201213715805A US9590674B2 US 9590674 B2 US9590674 B2 US 9590674B2 US 13715805 US13715805 US 13715805 US 201213715805 A US201213715805 A US 201213715805A US 9590674 B2 US9590674 B2 US 9590674B2
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transistor
terminal
switch
body
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Chris Olson
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pSemi Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors

Abstract

Semiconductor devices with switchable connection between body and a ground node are presented. Methods for operating and fabricating such semiconductor devices are also presented.

Description

BACKGROUND

1. Field

The present disclosure relates to semiconductor devices. More particularly, the present disclosure relates to semiconductor devices with switchable ground-body connection.

2. Description of Related Art

Floating body N-channel metal oxide semiconductor (NMOS) devices, whose device bodies float relative to ground, can exhibit higher power added efficiency (PAE) than body tied NMOS devices, whose device bodies are connected (or tied) to ground or a reference potential close to ground, by way of a body tie. However, floating body NMOS devices can also exhibit leakage current that is orders of magnitude worse than body tied NMOS devices.

U.S. Pat. No. 7,910,993 B2, issued on Mar. 22, 2011 which is related to the present disclosure is incorporated by reference herein in its entirety.

SUMMARY

According to a first aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a transistor that is fabricated on a substrate, the transistor having a body; and a switch with a first switch terminal connected to the body and a second switch terminal connected to a reference potential node, the switch configured to be controlled by a control signal to provide a first operating characteristic in the transistor by connecting the body to the reference potential node and to provide a second operating characteristic in the transistor by disconnecting the body from the reference potential node.

According to a second aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a stacked arrangement of transistors that is fabricated on a substrate, each transistor of the stacked arrangement having a body and one or more switches in correspondence of one or more transistors from the stacked arrangement of transistors, each with a first switch terminal connected to the body of a corresponding transistor from the one or more transistors, and a second switch terminal connected to a corresponding reference potential node, the one or more switches configured to be controlled by a control signal to provide a first operating characteristic in the corresponding transistor by connecting the body of the corresponding transistor to the corresponding reference potential node and to provide a second operating characteristic in the corresponding transistor by disconnecting the body from the reference potential node.

According to a third aspect of the present disclosure, a method of operating a transistor is provided, the method comprising: coupling a body of the transistor to a reference potential node when no input signal is provided to the transistor; and decoupling the body from the reference potential node when a radio frequency (RF) signal is provided to the transistor.

According to a fourth aspect of the present disclosure, a method of operating a transistor is provided, the method comprising: fabricating a transistor on a substrate, the transistor having a body; and fabricating a switch on the substrate with a first switch terminal of the switch connected to the body and a second switch terminal of the switch connected to a reference potential node.

According to a fifth aspect of the present disclosure, a method of operating a transistor is provided, the method comprising: coupling a body of one or more transistors from the stacked arrangement of transistors to a corresponding reference potential node when no input signal is provided to an input transistor of the stacked arrangement; and decoupling the body of the one or more transistors from the corresponding reference node when a radio frequency (RF) signal is provided to the input transistor, wherein the one or more transistors comprises the input transistor.

According to a sixth aspect of the present disclosure, a method of fabricating a semiconductor device is provided, the method comprising: fabricating a stacked arrangement of one or more transistors on a substrate, each of the one or more transistors having a body; and fabricating one or more switches on the substrate in correspondence of the one or more transistors with a first switch terminal of each of the one or more switches connected to the body of a corresponding transistor and a second switch terminal of each of the one or more switches connected to a corresponding reference potential node.

Further embodiments are provided in the specification, drawings, and claims of the present application.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure. Like reference numerals indicate corresponding parts in the various figures.

FIG. 1A shows an NMOS device in accordance with an embodiment of the present disclosure. The NMOS device can be constructed with a switch that allows a body terminal of the device to be selectively connected to a reference potential (e.g. ground) or disconnected from the reference potential (e.g. ground), depending on absence or presence of an RF signal, where the switch can be controlled by baseband/transceiver circuitry that is providing RF input.

FIG. 1B shows an exemplary system that utilizes the NMOS device of FIG. 1A as a power amplifier.

FIGS. 2A and 2B show NMOS devices in accordance with embodiments of the present disclosure. The NMOS devices can be constructed with a switch that allows a body terminal of the devices to be selectively connected to a reference potential (e.g. ground) or disconnected from the reference potential, depending on absence or presence of an RF signal. An RF signal can be detected using an RF coupler, as shown in FIG. 2A, or using an RF detector coupled to one or more of the device terminals, as shown in FIG. 2B.

FIG. 3 shows experimental leakage data for a device before and after a connection between device body and ground is cut.

FIGS. 4A and 4B show experimental efficiency and linearity data for a device before and after a connection between device body and ground is cut, respectively.

FIG. 5 shows an exemplary embodiment of the present disclosure wherein instead of the single NMOS device of FIG IA, a stacked arrangement of NMOS devices (e.g. two devices) is used. In this embodiment, each of the NMOS devices may be constructed with a switch that allows the body terminal of the device to be selectively connected to a reference potential depending on the presence or absence of an RF signal at an input node of the stacked arrangement. In the embodiment of FIG. 5, the reference potential for the top device is the source node of the same device, and the reference potential for the bottom (input) device is ground.

FIG. 6 shows an alternate embodiment of the one presented in FIG. 5, wherein the bodies of all devices within the stacked arrangement are selectively connected the same reference potential (e.g. ground).

FIG. 7 shows an alternate embodiment of the one presented in FIG. 5, wherein only one of the devices from the stacked arrangement (input device) is provided with a switch to selectively connect the body of the device to a reference potential (e.g. ground).

DETAILED DESCRIPTION

As used in the present disclosure, the term “body” can refer to a portion of a device between source and drain beneath a conducting channel. The preceding definition applies to both silicon on insulator devices as well as bulk CMOS devices because the portion referred to by the preceding definition describes a portion of a bulk CMOS device that can be considered as both the body and substrate of the bulk CMOS device (e.g. the body and substrate of a bulk CMOS device are generally the same).

As used in the present disclosure, the term “substrate” can refer to an insulating wafer upon which a semiconductor device or devices can be fabricated for the case of silicon on insulator devices. Alternatively, for bulk devices, the term “substrate” may refer to a silicon wafer upon which devices can be fabricated.

As used in the present disclosure, the term “floating body device” can refer to a device whose body floats relative to ground. Examples of devices that can have a floating body configuration include, but are not limited to, “floating body NMOS devices” as well as “floating body PMOS devices”.

As used in the present disclosure, the term “body tied device” can refer to a device whose body is connected (or tied) to a reference potential such as ground. Examples of devices that can have a body tied configuration include, but are not limited to, “body tied NMOS devices” as well as “body tied PMOS devices”.

As used in the present disclosure, the term “efficiency” can refer to a measure of how well a device converts one energy source to another. In a case of an NMOS device configured as a power amplifier and operating at radio frequencies (RF), efficiency of the NMOS device is a metric that quantifies conversion of direct current (DC) power that is input to a drain of the NMOS device to RF power that is output from the drain of the NMOS device. Such efficiency may also be referred to as drain efficiency of the NMOS device. Power added efficiency (PAE) provides a metric of efficiency that takes into consideration that gain of the power amplifier is not infinite.

As used in the present disclosure, the term “channel” can refer to a frequency range. More in particular, the term “channel” as used herein can refer to a frequency range defined by a wireless standard such as, but not limited to, wideband code division multiple access (WCDMA) and long term evolution (LTE). Based on the preceding definition of “channel”, adjacent channel leakage ratio (ACLR) provides a ratio of adjacent channel power to main channel power. For instance, in WCDMA, a channel bandwidth is 5 MHz. Consider power is to be transmitted on/within a main channel of 1925 MHz to 1930 MHz. Adjacent channels would encompass the 5 MHz below the main channel (i.e. 1920 MHz to 1925 MHz) and the 5 MHz above the main channel (i.e. 1930 MHz to 1935 MHz), and the ACLR will be ratio of power leaked into these adjacent channels to power in the main channel. Consequently, the ACLR can be utilized as a measure of linearity of a device since higher ACLR is associated with more frequency smearing (lower linearity).

As used in the present disclosure, the term “operating characteristic” can refer to value of a metric utilized to measure performance of a device (e.g. a transistor). Metrics of the device include measures of efficiency, linearity, and leakage, and others identifiable by a person skilled in the art. Operating characteristics of the device would encompass values of these metrics.

As used in the present disclosure, the “presence” or “absence” of a signal is relative to a threshold value that can be set based on application. Specifically, if a signal that is detected is above the threshold value (e.g. detected signal is of sufficient amplitude), then the signal is considered to be “present”. Similarly, if a signal that is detected is below the threshold value (e.g. detected signal is not of sufficient amplitude), then the signal is considered to be “absent” or “not present”.

It is noted that several embodiments of the present disclosure are described with reference to utilization of NMOS devices. However, reference to NMOS devices is for convenience of discussion only and the embodiments of the present disclosure can also apply to other types of transistors such as PMOS devices. Choice of whether to employ NMOS and PMOS devices is based on considerations that would be known by a person skilled in the art. For example, in RF amplifiers, NMOS devices are generally used since mobility of electrons is higher than mobility of holes. The devices may be constructed using technologies such as, but not limited to, silicon on insulator (SOI) technology, silicon on sapphire (SOS) technology, or bulk complementary metal oxide semiconductor (CMOS) technology.

Various embodiments of the present disclosure can be implemented through NMOS and/or PMOS devices of all thresholds. An exemplary semiconductor process can include one or more of the following types of MOS field effect transistor (FET) types. Example NMOSFETs include regular N (RN) FETs that have a nominal threshold voltage of 450 mV, high doping N (HN) FETs that have a nominal threshold voltage of 700 mV, and intrinsic N (IN) FETs that may have a threshold voltage of approximately 0V. Corresponding PMOSFETs include regular P FETs (RP) that have a nominal threshold voltage of −400 mV, high doping FETs (HP) that have a nominal threshold voltage of −600 mV, and intrinsic P (IP) FETs that may have a threshold voltage of approximately 0 V. In another semiconductor process, HN, RN, HP, and RP FETs may have threshold voltages of 800 mV, 300 mV, −800 mV, and −300 mV, respectively. Details in a circuit are specific to a particular semiconductor process utilized, but the skilled person can adjust details to fit different semiconductor processes.

According to several embodiments of the present disclosure, a semiconductor device, such as an amplifier comprising stacked transistors, can be constructed that comprises one or more transistors and one or more switches. Each transistor within the stack is fabricated on a substrate and has a body whereas a corresponding switch can be configured to either connect the body of the transistor to a reference potential (e.g. ground) node or disconnect the body of the transistor from the reference potential (e.g. ground) node. Although the semiconductor device is discussed with reference to application primarily at RF, teachings of the present disclosure can be applied to operation of the semiconductor device at other frequencies.

Configuration of the switch for each of the transistors, either connecting body to a reference potential or disconnecting body from the reference potential, is generally dependent on operating characteristics desired in the transistor. For example, an application within which the semiconductor device is to be employed may require that the transistor be capable of exhibiting a first operating characteristic (e.g. a particular value or a range of values for PAE of the transistor) when the switch connects the body of the transistor to a reference potential (e.g. ground) and of exhibiting a second operating characteristic (e.g. a particular value or a range of values for loss due to leakage for the transistor) when the switch disconnects the body of the transistor from the reference potential. The first and second operating characteristics may be of different metrics, as in the preceding example, or of the same metric but at different values.

FIG. 1A shows an NMOS device (110) in accordance with an embodiment of the present disclosure. The NMOS device (110) can be constructed with a switch (120) that allows a body of the device (110) to be selectively connected to a reference potential, in this case ground, or disconnected from ground, depending on absence or presence of a primary RF signal (170), where the switch (120) can be controlled by baseband/transceiver circuitry (not shown) that is providing the primary RF signal (170). More specifically, a body tie switch control portion (125) of the transceiver circuitry can send a control signal (145) to the switch (120) to provide appropriate control.

When the transceiver circuitry of a system that comprises the NMOS device (110) is transmitting, the control signal (145) can be a switch de-activation signal configured to open the switch (120) and thereby disconnect the body of the NMOS device (110) from ground. As will be discussed, disconnecting the body of the NMOS device (110) from ground can improve PAE. When the transceiver circuitry of the system is not transmitting, the control signal (145) can be a switch activation signal configured to close the switch (120) and thereby connect the body of the device (110) to ground. As will be discussed, connecting the body of the device (110) to ground or a reference potential close to ground, can reduce leakage current. It is noted that the body tie switch control portion (125) of the transceiver circuitry can be an enable/disable signal generated by the transceiver circuitry and applied to the switch (120) to effect appropriate control depending on whether or not the transceiver circuitry is transmitting.

The switch (120) can be implemented as any one of an NMOS switching transistor, PMOS switching transistor, a diode, or other active device that can be envisioned by a person skilled in the art. Additionally, this embodiment may comprise an impedance element (130)

FIG. 1B shows an exemplary system (190) that utilizes the NMOS device (110) of FIG. 1A as a power amplifier. Specifically, the system (190) may be an RF lineup that comprises a baseband processor (180) that is configured to generate a baseband signal; a transceiver circuit (182) that is configured to receive the baseband signal and upconvert the baseband signal to an RF signal (170); a power amplifier (186) that is configured to receive the RF signal (170); and an antenna (188) that is configured to transmit an output of the power amplifier (186).

In FIG. 1B, the power amplifier (186) may be implemented as the NMOS device (110) constructed with a switch (120), as shown in FIG. 1A, or implemented using a stacked arrangement of NMOS devices each with an associated switch as per FIGS. 5-7. In such a case, the transceiver circuit (182) can be further configured to provide a control signal (184) to the NMOS device (110). In particular, the control signal (184) can be provided to the switch (120) as well as the switches associated to the other devices from the stack, to allow a body terminal of the NMOS device (110) and each of the NMOS devices of the stack associated with a switch, to be selectively connected to a reference potential (e.g. ground) or disconnected from the reference potential based on value of the control signal (184). For example, when the power amplifier (186) is being turned off (e.g. configured not to generate RF power), the control signal (184) can be configured to (e.g. set to a value that can) close the switch (120). When the power amplifier (186) is being turned on (e.g. configured to generate RF power), the control signal (184) can open the switch (120). In other words, the power amplifier (186) can be configured to receive a control signal (184) and logic used to open or close the switch (120) can be derived from the control signal (184). It is noted that, although in the example above the control signal (184) is being provided by the transceiver circuit (182), other components, such as the baseband processor (180), can instead provide the control signal (184).

FIGS. 2A and 2B show NMOS devices (110) in accordance with embodiments of the present disclosure. The NMOS devices (110) can be constructed with a switch (120) that allows a body of the device (110) to be selectively connected to a reference potential, in this case ground, or disconnected from ground, depending on absence or presence of an RF signal (261, 262). With reference to FIG. 2A, an RF signal (261) can be detected using an RF coupler (280). With reference to FIG. 2B, an RF signal (262) can be detected using an RF detector (240) coupled to one or more terminals of the NMOS device (110). Any of the embodiments shown in FIGS. 2A and 2B can detect an RF signal at any one of gate, drain, and source of the device (110). The device (110) in FIGS. 1 and 2A-2B may be constructed using technologies such as, but not limited to, SOI technology, SOS technology, or bulk CMOS technology.

In the embodiment shown in FIG. 2A, the RF coupler (280) is a three port RF coupler (280).However, couplers with more ports may also be used. With reference to the embodiment shown in FIG. 2A, a primary RF signal (170), such as from baseband/transceiver circuitry, is input to port 1 of the RF coupler (280), an output (270) from port 2 of the RF coupler (280) can drive the gate terminal of the NMOS device (110), and an output (261) from port 3 of the RF coupler (280) can be fed to a detector/control circuit (260). The detector/control circuit (260) can generate a control signal based on the output (261) from port 3 of the RF coupler (280) to effect control of switch (120).

The RF coupler (280) can be configured to split the primary RF signal (170) such that a majority of signal power of the primary RF signal (170) is output (270) from port 2 of the RF coupler (280) to drive the gate of the NMOS device (110) while a smaller amount of signal power of the primary RF signal (170) is output (261) from port 3 of the RF coupler (280) to feed into the detector/control circuit (260). By way of example and not of limitation, the RF coupler (280) can be configured to split the primary RF signal (170) such that the output (270) from port 2 of the RF coupler (280) contains 90% of signal power of the primary RF signal (170) and RF signal (261) contains 10% of signal power of the primary RF signal (170). Other designs of RF couplers identifiable by a person skilled in the art may also be utilized with the embodiments of the present disclosure. Furthermore and as previously mentioned, the NMOS device may be replaced with a stacked arrangement of NMOS devices, such as depicted in FIGS. 5-7, found within an amplifier, in which case the RF signal at (270) drives the gate of the input transistor (110) from the stack.

According to several embodiments of the present disclosure, an RF signal can be sampled capacitively or magnetically at one or more terminals (e.g. gate, source, drain) of the NMOS device (110). In the embodiment shown in FIG. 2B, an RF signal can be detected at any one of gate, drain, and source terminals of the NMOS device (110), or an input NMOS device (110) of an amplifier comprising stacked devices as depicted in FIGS. 5-7, using an RF detector coupled to corresponding terminals The RF detection can be performed by electrically sensing voltage or current at one or more of the terminals of the NMOS device (110) and couple the sensed voltage or signal to a detector/control circuit (260). For example, FIG. 2B shows the RF detection performed through capacitive coupling (240) employed at each of the terminals, where the capacitive coupling (240) samples RF signals and couples the sampled RF signals to a detector/control circuit (260). Based on signals coupled or otherwise provided to the detector/control circuit (260), the detector/control circuit (260) can generate a control signal to effect control of switch (120).

According to the embodiment shown in FIG. 2A, the signal (261) represents an RF signal detected by the RF coupler (280). According to the embodiment shown in FIG. 2B, the signal (262) represents an RF signal detected by capacitive coupling (240) employed at terminals of the NMOS device (110). In both embodiments, the detector/control circuit (260) detects an RF signal (261, 262) and generates a control signal (245) based on absence or presence of the detected RF signal (261, 262). The detector/control circuit (260) can be fabricated on the same substrate as the NMOS device (110), although doing so does not necessarily confer benefits in regard to leakage or PAE. However, fabricating the detector/control circuit (260) on the same substrate as the NMOS device (110) may simplify fabrication.

The switch (120), as well as each switch associated to a transistor within the stack as depicted in FIGS. 5-7, can be controlled by the control signal (245). The control signal (245) can be a switch de-activation signal that will open the switches and thereby disconnect the body of each one of the NMOS devices from the corresponding reference potential (e.g. ground). This can result in higher PAE. By way of example, the detector/control circuit (260) can generate the switch de-activation signal if an RF signal (261, 262) of sufficient amplitude is detected in at least one terminal of the NMOS device (110) (e.g. gate, drain, or source). Each switch (120) can be implemented as any one of an NMOS switching transistor, PMOS switching transistor, a diode, or other active device that can be envisioned by a person skilled in the art. Additionally, an impedance element (130) can be connected between the switch (120) and a reference potential such as ground or the source node of the corresponding device (body-tied-to-source (BTS device)). For example, the impedance element (130) can be an inductor or a primarily inductive element, where inclusion of the inductor would cause the body of the device (110) to float relative to AC (e.g. an RF signal) and connect the body to ground relative to DC. The impedance element (130) can also simply be replaced with a short circuit without detrimentally compromising circuit operation.

If an RF signal (261, 262) is not present at one of the terminals of the NMOS device (110) terminals or an RF signal (261, 262) detected is not of sufficient amplitude (e.g. below a threshold), the detector/control circuit (260) can apply a switch activation signal or otherwise remove application of the switch de-activation signal, closing the switch (120) and thereby connecting the body to ground. This can achieve lower leakage. By way of example, the detector/control circuit (260) can replace the switch de-activation signal with the switch activation signal when an RF signal (261, 262) is not present at one of the NMOS device (110) terminals, closing the switch (120) and thereby connecting the body to the reference potential (e.g. ground).

With reference to FIG. 2A, an RF coupler (280) can be used to detect whether or not an RF signal (261) is present at the gate terminal of the NMOS device (110), although RF couplers can also be coupled to source and/or drain terminals of the NMOS device (110) for detection purposes. With reference to FIG. 2B, an RF signal (262) can also be detected via capacitive coupling (240) coupled to at least one of the NMOS device (110) terminals. The switch (120) can be closed when an RF signal (261, 262) is below a certain threshold, corresponding to no RF signal being detected. In example implementations, closing the switch (120) when no RF signal is detected has been shown to achieve leakage in the range of 1 pA per μm to 1 nA per μm of gate width. The switch (120) can be opened when an RF signal (261, 262) is above a certain threshold, corresponding to an RF signal being detected. In example implementations, opening the switch (120) when an RF signal is detected has been shown to achieve PAE in the range of 40% to 60%.

In some applications, an example threshold for detection can be −75 dBm. With reference back to the RF lineup (190) shown in FIG. 1B, the example threshold value of −75 dBm above would be the smallest amplitude of the primary RF signal (170) that can be generated by the transceiver circuit (182). An example gain of the power amplifier (186) is 15 dB, which leads to an example transmitted signal of −60 dBm at the antenna (188).

Note that embodiments of the present disclosure may be part of an RF lineup similar to that shown in FIG. 1B. The RF lineup can include elements such as a transceiver, a filter, a power amplifier, a duplexer, and an antenna. The RF signal (261, 262) could be detected anywhere in the RF lineup that comprises the device (110) in addition to or instead of RF signals detected at the terminals (e.g. gate, drain, source) of the device (110). In other words, the RF signal (261, 262) can be detected at a transceiver, a filter, a power amplifier, a duplexer, an antenna, or some other element of the RF lineup that comprises the NMOS device (110). By way of example, the RF signal (261, 262) can be in the UHF band, the VHF band, or a different high frequency band and can be a WCDMA or an LTE signal. A person skilled in the art will also be able to identify numerous other frequency bands that the RF signal could occupy and numerous other wireless standards that the RF signal could follow.

Implementations of embodiments of the present disclosure were obtained and operating characteristics, such as leakage and efficiency data, were measured. In one implementation, an NMOS device (110) was constructed with its body connected to ground and performance characteristics measured. After the performance characteristics were obtained from the body tied NMOS device, the connection (body tie) between body and ground of the NMOS device (110) was cut (in particular, by a laser) and performance characteristics measured again.

FIG. 3 shows experimental leakage data for a device before and after a connection between device body and ground is cut. In FIG. 3, Ileak represents leakage current whereas VDD represents a DC voltage from a battery that is connected to the NMOS device. In this case, leakage refers to a leakage of current from the battery along a current path from drain to source, thereby reducing battery life. Results shown in FIG. 3 indicate that leakage increases after cutting the connection between device body and ground.

FIGS. 4A and 4B show experimental efficiency and linearity data for a device before and after connection between device body and ground is cut, respectively. In particular, FIGS. 4A and 4B show experimental power added efficiency (PAE) and adjacent channel leakage ratio (ACLR) data. The ACLR data is given with respect to an adjacent channel of frequencies lower than the main channel (denoted as “Lower ACLR”) and an adjacent channel of frequencies higher than the main channel (denoted as “Upper ACLR”). Results shown in FIGS. 4A and 4B indicate that PAE improves after cutting the connection between device body and ground. An example ACLR specification is −40 dBc, which generally signifies that the worse of the two ACLR values needs to be −40 dBc or lower. At an ACLR of −40 dBc, the body tied case (FIG. 4A) is at an efficiency of below 10% whereas the floating body case (FIG. 4B) is at an efficiency of around 60%.

It is noted that data shown in FIGS. 4A and 4B may indicate a larger difference in PAE before and after cutting the connection between device body and ground due to design of the device. In particular, body tied performance of the device was compromised by virtue of the device being designed to be cut with a laser. An alternative RF layout can improve body tied performance and decrease PAE differences between the body tied and floating body cases.

As another example, floating body SOS NMOS devices of threshold between 0.4 V to 0.7 V) have been shown to exhibit PAE of 2% to 5% higher than body tied NMOS devices. However, these floating body SOS NMOS devices also tend to exhibit 2 to 6 orders of magnitude worse leakage than body tied NMOS devices.

Embodiments of the present disclosure can combine benefits of both floating body and body tied devices. According to several embodiments of the present disclosure, a semiconductor device is provided that comprises a transistor configured to have its body tied to a reference potential (e.g. ground) node via a switch or its body disconnected from the reference potential node via the switch. The switch can be configured to be controlled by a control signal. In some embodiments, the control signal can provided from other elements in a system comprising the semiconductor device, such as a transceiver circuit or a baseband processor. In other embodiments, the control signal can be derived from an RF signal detected by the semiconductor device. Logic used to open or close the switch can be derived from the control signal.

Provided in the present disclosure are embodiments for a method of operating an amplifier comprising of one or more transistors arranged in a stack, where each transistor has a body. The method can comprise coupling the body of one or more transistors of the stack to a corresponding reference potential (e.g. ground) node when no input signal is provided to the amplifier and decoupling the body from the reference potential (e.g. ground) node when an RF signal is provided to the amplifier. The coupling and decoupling can be carried out using one or more switches, each associated to one transistor of the stack and all controlled via the same control signal. As indicated previously, the presence or absence of a signal is relative to a threshold value that can be set based on application. If a detected signal is above the threshold value (e.g. detected signal is of sufficient amplitude), then the signal is considered to be “present”. Similarly, if a detected signal is below the threshold value (e.g. detected signal is not of sufficient amplitude), then the signal is considered to be “absent” or “not present”.

Also provided in the present disclosure are embodiments for a method for fabricating a semiconductor device comprising a plurality of transistors and a plurality of switches, where each transistor has a body. The method can comprise fabricating the transistors and the switches on a substrate, where each switch is adapted to connect the body of the corresponding transistor to a reference potential (e.g. ground) node or disconnect the body of the transistor to the reference potential (e.g. ground) node. The method can further comprise fabricating a control circuit on the substrate, where the control circuit is operable to provide a control signal to the switches.

The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the embodiments of the semiconductor devices with switchable ground-body connection of the present disclosure, and are not intended to limit the scope of what the inventor regard as his disclosure. Modifications of the above-described modes for carrying out the disclosure may be used by persons of skill in the art, and are intended to be within the scope of the following claims. All patents and publications mentioned in the specification may be indicative of the levels of skill of those skilled in the art to which the disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.

It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.

A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.

Claims (35)

What is claimed is:
1. A semiconductor device, comprising:
a four terminal transistor that is fabricated on a substrate, the transistor comprising:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) a body terminal in contact with the body region; and
a switch with a first switch terminal connected to the body terminal and a second switch terminal connected to a reference potential node, a closed condition and an open condition of the switch being controlled by a control signal to provide a first operating characteristic in the transistor by connecting the body terminal to the reference potential node when the switch is closed, and to provide a second operating characteristic in the transistor by disconnecting the body terminal from the reference potential node when the switch is open,
wherein:
the switch comprises an inductor operatively connected between the switch and the reference potential node, the inductor configured to cause the body region to float relative to AC and to connect the body region to the reference potential relative to DC,
the first operating characteristic comprises a reduction in a leakage current between the first terminal and the second terminal, and
the second operating characteristic comprises an increase of a power added efficiency (PAE) of the transistor.
2. The semiconductor device according to claim 1, wherein the transistor is a silicon on insulator NMOS transistor or a bulk NMOS transistor.
3. The semiconductor device according to claim 1, wherein in the transistor is configured as one of: a) an amplifier, and b) a power amplifier.
4. The semiconductor device according to claim 1, further comprising:
a control circuit that is configured to generate a switch de-activation signal for disconnecting the body terminal of the transistor from the reference potential node.
5. The semiconductor device according to claim 4, wherein the switch and the control circuit are fabricated on a common substrate.
6. The semiconductor device according to claim 4, further comprising:
a radio frequency (RF) signal detector configured to detect an RF signal in the semiconductor device, wherein the control circuit is configured to receive the detected RF signal and to generate the switch de-activation signal based on the detected RF signal.
7. The semiconductor device according to claim 6, wherein the RF signal is detected in at least one of a source node, a gate node, or a drain node respectively in correspondence of the second terminal, the third terminal and the first terminal of the transistor.
8. The semiconductor device according to claim 7, the control circuit being configured to remove the switch de-activation signal when the RF signal detector fails to detect an RF signal, wherein removal of the switch de-activation signal activates the switch and connects the body terminal of the transistor to the reference potential node.
9. The semiconductor device according to claim 7, the control circuit being configured to replace the switch de-activation signal with a switch activation signal when the RF signal detector fails to detect an RF signal, wherein the switch activation signal is configured to activate the switch and connect the body terminal to the reference potential node.
10. The semiconductor device according to claim 6, wherein:
the RF signal detector comprises an RF coupler configured to split the detected RF signal into at least a first component and a second component,
the transistor is configured to receive the first component and the control circuit is configured to receive the second component, and
the control circuit is configured to generate the switch de-activation signal based on the second component of the detected RF signal.
11. The semiconductor device according to claim 1, wherein the switch comprises an NMOS switching transistor.
12. A semiconductor device, comprising:
a stacked arrangement of transistors that is fabricated on a substrate, each transistor of the stacked arrangement comprising:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal, configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) a body terminal in contact with the body region; and
one or more switches in correspondence of one or more transistors from the stacked arrangement of transistors, each with a first switch terminal connected to the body terminal of a corresponding transistor from the one or more transistors, and a second switch terminal connected to a corresponding reference potential node, a closed condition and an open condition of the one or more switches being controlled by a control signal to provide a first operating characteristic in the corresponding transistor by connecting the body terminal of the corresponding transistor to the corresponding reference potential node when a corresponding switch is closed, and to provide a second operating characteristic in the corresponding transistor by disconnecting the body terminal from the reference potential node when the corresponding switch is open,
wherein:
at least one switch of the one or more switches comprises an inductor operatively connected between the at least one switch and the corresponding reference potential node, the inductor configured to cause the body region of the corresponding transistor to float relative to AC and to connect the body region of the corresponding transistor to the reference potential relative to DC,
the first operating characteristic comprises a reduction in a leakage current between the first terminal and the second terminal, and
the second operating characteristic comprises an increase of a power added efficiency (PAE) of the transistor.
13. The semiconductor device according to claim 12, wherein in the stacked arrangement of transistors is configured as one of: a) an amplifier, and b) a power amplifier.
14. The semiconductor device according to claim 12, wherein at least one of the one or more switches comprises an NMOS switching transistor.
15. The semiconductor device according to claim 12, further comprising:
a control circuit that is configured to generate a switch de-activation signal for disconnecting the body terminal of each of the one or more transistors from the corresponding reference potential node.
16. The semiconductor device according to claim 15, further comprising:
a radio frequency (RF) signal detector configured to detect an RF signal in the semiconductor device, wherein the control circuit is configured to receive the detected RF signal and to generate the switch de-activation signal based on the detected RF signal.
17. A method of operating a transistor that is fabricated on a substrate, the transistor comprising a first terminal in contact with a first region of the transistor, a second terminal in contact with a second region of the transistor, a third terminal configured to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region, and a body terminal in contact with the body region, the method comprising:
coupling a body terminal of the transistor to a reference potential node when no input signal is provided to the transistor, thereby reducing a leakage current between a first terminal and the second terminal; and
decoupling the body terminal from the reference potential node when a radio frequency (RF) signal is provided to the transistor, thereby increasing a power added efficiency (PAE) of the transistor.
18. The method according to claim 17, wherein the transistor is a silicon on insulator NMOS transistor or a bulk NMOS transistor.
19. The method according to claim 18, wherein the coupling and decoupling are carried out via a switch.
20. The method according to claim 19, wherein the switch is an NMOS switching transistor.
21. The method according to claim 17, wherein the RF signal encompasses at least one of a UHF or a VHF band of radio frequencies.
22. The method according to claim 17, wherein the RF signal comprises a WCDMA signal or an LTE signal.
23. A method of fabricating a semiconductor device, comprising:
fabricating a transistor on a substrate, the transistor comprising:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) a body terminal in contact with the body region; and
fabricating a switch on the substrate with a first switch terminal of the switch connected to the body terminal and a second switch terminal of the switch connected to a reference potential node, and
fabricating a control circuit on the substrate, the control circuit operable to provide a switch de-activation signal for operating the switch to selectively disconnect the body terminal from the reference potential node,
wherein the switch de-activation signal is provided to the switch upon detection of an RF signal in the semiconductor device.
24. The method according to claim 23, wherein the switch de-activation signal is provided to the switch upon detection of the RF signal in at least one of a drain node, a source node, a gate node respectively in correspondence of the first terminal, the second terminal and the third terminal of the transistor.
25. A method of operating a stacked arrangement of transistors, comprising:
coupling a body terminal of one or more transistors from the stacked arrangement of transistors to a corresponding reference potential node when no input signal is provided to an input transistor of the stacked arrangement, thereby providing a corresponding reference potential to the body terminal; and
decoupling the body terminal of the one or more transistors from the corresponding reference node when a radio frequency (RF) signal is provided to the input transistor, thereby floating the body terminal, wherein the one or more transistors comprises the input transistor,
wherein:
the one or more transistors are fabricated on a common substrate, and
each of the one or more transistors comprises:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) the body terminal in contact with the body region.
26. The method according to claim 25, wherein one or more transistors from the stacked arrangement of transistors is a silicon on insulator NMOS transistor or a bulk NMOS transistor.
27. The method according to claim 26, wherein the coupling and decoupling are carried out via one or more switches in correspondence of the one or more transistors.
28. The method according to claim 27, wherein a switch from the one or more switches is an NMOS switching transistor.
29. The method according to claim 25, wherein the RF signal encompasses at least one of a UHF or a VHF band of radio frequencies.
30. The method according to claim 25, wherein the RF signal comprises a WCDMA signal or an LTE signal.
31. A method of fabricating a semiconductor device, comprising:
fabricating a stacked arrangement of one or more transistors on a substrate, each of the one or more transistors having a body terminal in contact with a body region of the transistor; and
fabricating one or more switches on the substrate in correspondence of the one or more transistors with a first switch terminal of each of the one or more switches connected to the body terminal of a corresponding transistor and a second switch terminal of each of the one or more switches connected to a corresponding reference potential node;
fabricating a control circuit on the substrate, the control circuit operable to provide a switch de-activation signal for operating the one or more switches in correspondence of the one or more transistors to selectively disconnect the body terminal of each of the one or more transistors from the corresponding reference potential node, the switch de-activation signal being provided to the one or more switches upon detection of an RF signal in the semiconductor device,
wherein each of the one or more transistors comprises:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) the body terminal in contact with the body region.
32. The method according to claim 31, wherein the switch de-activation signal is provided to the one or more switches upon detection of the RF signal in at least one of a drain node, a source node, a gate node respectively in correspondence of the first terminal, the second terminal, and the third terminal of an input transistor of the stacked arrangement of one or more transistors.
33. A method of fabricating a semiconductor device, comprising:
fabricating a stacked arrangement of one or more transistors on a substrate, each of the one or more transistors having a body terminal in contact with a body region of the transistor; and
fabricating one or more switches on the substrate in correspondence of the one or more transistors with a first switch terminal of each of the one or more switches connected to the body terminal of a corresponding transistor and a second switch terminal of each of the one or more switches connected to a corresponding node,
wherein:
the corresponding node of the corresponding transistor different from an input transistor of the stacked arrangement is a source node of the corresponding transistor connected to a drain node of an adjacent transistor of the stacked arrangement,
the corresponding node of the input transistor is a reference potential node connected to a reference potential, and
each of the one or more transistors comprises:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) the body terminal in contact with the body region.
34. The method according to claim 33, wherein for the corresponding transistor different from the input transistor, the second switch terminal is connected to the corresponding node through a series connected inductor.
35. A semiconductor device, comprising:
a stacked arrangement of transistors that is fabricated on a substrate, each transistor of the stacked arrangement comprising:
i) a first terminal in contact with a first region of the transistor;
ii) a second terminal in contact with a second region of the transistor;
iii) a third terminal, configured, during operation of the transistor, to receive a voltage to control a conduction channel in a portion of a body region of the transistor between the first region and the second region; and
iv) a body terminal in contact with the body region; and
one or more switches in correspondence of one or more transistors from the stacked arrangement of transistors, each with a first switch terminal connected to the body terminal of a corresponding transistor from the one or more transistors, and a second switch terminal connected to a corresponding node, a closed condition and an open condition of the one or more switches being controlled by a control signal to provide a first operating characteristic in the corresponding transistor by connecting the body terminal of the corresponding transistor to the corresponding node when a corresponding switch is closed, and to provide a second operating characteristic in the corresponding transistor by disconnecting the body terminal from the corresponding node when the corresponding switch is open,
wherein:
the corresponding node of the corresponding transistor different from an input transistor of the stacked arrangement is a source node of the corresponding transistor connected to a drain node of an adjacent transistor of the stacked arrangement,
the corresponding node of the input transistor is a reference potential node connected to a reference potential, and
the first operating characteristic comprises a reduction in a leakage current between the first terminal and the second terminal, and
the second operating characteristic comprises an increase of a power added efficiency (PAE) of the transistor.
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