WO2007033045A2 - Stacked mosfets - Google Patents

Stacked mosfets Download PDF

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Publication number
WO2007033045A2
WO2007033045A2 PCT/US2006/035227 US2006035227W WO2007033045A2 WO 2007033045 A2 WO2007033045 A2 WO 2007033045A2 US 2006035227 W US2006035227 W US 2006035227W WO 2007033045 A2 WO2007033045 A2 WO 2007033045A2
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WO
WIPO (PCT)
Prior art keywords
mosfets
individual
capacitors
shifter circuit
stack
Prior art date
Application number
PCT/US2006/035227
Other languages
French (fr)
Other versions
WO2007033045A3 (en
Inventor
Erik J. Mentze
Herbert L. Hess
Jennifer E. Phillips
Original Assignee
Idaho Research Foundation, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idaho Research Foundation, Inc. filed Critical Idaho Research Foundation, Inc.
Publication of WO2007033045A2 publication Critical patent/WO2007033045A2/en
Publication of WO2007033045A3 publication Critical patent/WO2007033045A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches

Definitions

  • This disclosure relates to stacked MOSFETs and methods of providing the
  • Fig. 1 is a schematic diagram of an exemplary stacked MOSFET circuit in
  • Fig. 2 illustrates a specific example of an implemented stacked MOSFET in
  • Fig. 3 shows simulated and measured results for the circuit of Fig. 2.
  • Fig. 4 illustrates the simulation results of an 8-device stacked MOSFET.
  • Fig. 5 illustrates an alternate embodiment in accordance with one
  • high- voltage is defined to mean any voltage that is greater than the breakdown voltage of the individual transistors being used.
  • high- voltage would be any voltage greater than 1.8 volts.
  • breakdown voltage of the individual transistors comprising the constituent elements of a stacked arrangement is 12 volts, high- voltage is any voltage greater than 12 volts.
  • specific examples that are used in this document are not intended to limit application of the claimed subject matter to any one particular breakdown voltage. Rather, a number of different transistors having varying breakdown voltages can be utilized without departing from the spirit and scope of the claimed subject matter.
  • the disclosed systems can extend the ability of solid-state transistors to switch voltages greater than their breakdown voltage by arranging a set of transistors in series and causing them to evenly share the high-voltage being controlled.
  • Fig. 1 illustrates an exemplary schematic diagram of a stacked MOSFET arrangement generally at 100.
  • a stacked arrangement can have any practicably suitable number of transistors.
  • MOSFET 108 serves as an input transistor and receives an input v in .
  • the top transistor in the arrangement is connected to a supply voltage V dd through a bias resistor R b j as as shown.
  • Individual transistors in the stack are operatively connected to individual respective resistors across their outputs. For example, transistor 108 is connected with resistor Rl, transistor 106 is connected with resistor R2, transistor 104 is connected with resistor R3 and so on.
  • individual transistors other than the input transistor have a respective capacitor connected between its gate and ground, as well as a diode connected as shown.
  • extra circuitry is added to a stack to turn it on, turn it off, and make it operate reliably which is discussed in more detail below.
  • Fig. 2 illustrates a specific example of an implemented stacked MOSFET generally at 200.
  • This schematic shows a 2-device stacked MOSFET that includes a first transistor or MOSFET 202 connected to a bias voltage through bias resistor R b i as -
  • the gate of transistor 202 is to ground through a capacitor 206.
  • the output of the stacked MOSFET arrangement is taken across a plurality of resistors R as shown.
  • An input transistor 204 is connected as shown as receives an input signal
  • Figs. 3a-d show simulated and measured results of this particular arrangement.
  • the turn on voltage of this circuit is accomplished through a capacitive voltage divider.
  • This voltage divider is realized, in this embodiment, through the inserted gate capacitors (shown in Fig. 2 as C2 and, more generally, in Fig. 1 as C2, C3, ... Cn) and the inherent parasitic capacitances that exist across the gate-source of the MOSFET.
  • the gate capacitors By sizing the gate capacitors according to the design driven by the particular environment in which the circuit is to be employed, precise gate-source voltages which turn on each device in the stack when a logical "high" signal is applied to the bottom device of the stack can be provided. It is this ability to design for an exact on-state gate-source voltage which enables one to keep each device from exceeding its breakdown voltage while the entire stack controls very high voltages.
  • these inserted gate capacitors can take the form of discrete capacitors or parasitic drain-source tied MOSFETs, depending on the particular application.
  • the latter form, drain-source tied MOSFETs is a unique contribution that allows for a reduction in the amount of die space required to implement the circuit as a fully integrated circuit.
  • the turn-off of the circuit occurs when the control signal at the gate of the bottom MOSFET (i.e. the input transistor) goes to a logical "low". When this happens, all the MOSFETs turn off and the intermediate nodes of the circuit are free to take on the voltage dictated by the resistive voltage divider network. These resistances are sized equally and as such, cause each MOSFET to share an equal portion of the total voltage being controlled.
  • this resistive voltage divider network can take many different forms depending on the application. Two specific forms that have been tested are discrete resistors and gate-source connected MOSFETs (diode- connected). The latter form, gate-source connected MOSFETs, is a unique contribution that allows for a reduction in the amount of die space required to implement the circuit as a fully integrated circuit.
  • the various embodiments have unique circuit design advantages from both an economic stand point and a technical stand point. Specifically, whenever an electrical engineer approaches a switching problem he or she must always consider the breakdown voltage of the transistor being used, as will be appreciated by the skilled artisan.
  • the transistor chosen must have a breakdown voltage greater than the voltages being switched. High breakdown voltage transistors are more expensive than low breakdown voltage transistors. As such, using inexpensive, low breakdown voltage, transistors to handle high- voltages can reduce the cost of the circuit.
  • the above-described embodiments can reduce the number of different types of parts needed for a project, allowing for the use of bulk purchased parts in both low voltage and high voltage applications. Economic benefits can also be seen for integrated circuits. Integrated circuit fabrication processes that are capable of handling high- voltages are much more expensive than their low- voltage counterparts. By implementing the described embodiments in the less expensive, low-voltage, fabrication process, high-voltage control can be achieved for significantly less money.
  • the general category of application for the described embodiments is high- voltage switching and control.
  • Two exemplary applications include by way of example and not limitation MEMS (Micro Electro- Mechanical Systems) device control and high voltage pulse width modulation.
  • MEMS Micro Electro- Mechanical Systems
  • MEMS devices are moving machines that are fabricated on the same scale as microelectronics. These small systems require high- voltages to switch them on and off.
  • the described embodiments can enable the switching of these devices directly by microelectronics, further decreasing the overall system size and weight.
  • High- Voltage pulse width modulation is the technique by which many switching feedback control systems operate. These feedback control systems have a logical component to them as well as a switching component to them.
  • the logical component is a digital logic system that samples an output, processes it, and generates a corrective action based on what needs to be done. That corrective action is then fed to the switching component which adjusts the on/off time of the switch for the system.
  • the logical end of this is almost always a fully integrated microelectronic system.
  • the switching end of this is almost always a discrete MOSFET driver.
  • the disclosed systems provide a reliable means of switching high-voltages with solid-state transistors (i.e. MOSFETs).
  • the disclosed systems can extend the ability of solid-state transistors to switch voltages greater than their breakdown voltage by arranging a set of transistors in series and causing them to evenly share the high-voltage being controlled.

Abstract

A stacked MOSFET includes a first transistor or MOSFET (202) connected to a bias voltage through bias resistor Rbias.The gate of transistor (202) is grounded through a capacitor (206) The output of the stacked MOSFET arrangement is taken across a plurality of resistors R. An input transistor (204) is connected as shown to receive an input signal Vin.

Description

STACKED MOSFETS
RELATED APPLICATION
This application claims priority to U.S. Provisional Application Serial No.
60/716,322, filed on 09/12/2005.
GOVERNMENT SPONSORED RESEARCH
This Application resulted from research supported at least in part by NASA EPSCoR under contract NCC5-557.
BACKGROUND OF THE INVENTION
This disclosure relates to stacked MOSFETs and methods of providing the
same.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic diagram of an exemplary stacked MOSFET circuit in
accordance with one embodiment.
Fig. 2 illustrates a specific example of an implemented stacked MOSFET in
accordance with one embodiment.
Fig. 3 shows simulated and measured results for the circuit of Fig. 2.
Fig. 4 illustrates the simulation results of an 8-device stacked MOSFET.
Fig. 5 illustrates an alternate embodiment in accordance with one
embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Overview
The disclosed systems provide a reliable means of switching high-voltages with solid-state transistors (i.e. MOSFETs). In the context of this document, "high- voltage" is defined to mean any voltage that is greater than the breakdown voltage of the individual transistors being used.
For example, if the breakdown voltage of the individual transistors comprising the constituent elements of a stacked arrangement is 1.8 volts, high- voltage would be any voltage greater than 1.8 volts. Similarly, if the breakdown voltage of the individual transistors comprising the constituent elements of a stacked arrangement is 12 volts, high- voltage is any voltage greater than 12 volts. As will be appreciated by the skilled artisan, what defines a high- voltage will differ from application to application. Accordingly, specific examples that are used in this document are not intended to limit application of the claimed subject matter to any one particular breakdown voltage. Rather, a number of different transistors having varying breakdown voltages can be utilized without departing from the spirit and scope of the claimed subject matter.
In the illustrated and described embodiments, the disclosed systems can extend the ability of solid-state transistors to switch voltages greater than their breakdown voltage by arranging a set of transistors in series and causing them to evenly share the high-voltage being controlled.
Exemplary Embodiment
Fig. 1 illustrates an exemplary schematic diagram of a stacked MOSFET arrangement generally at 100. A stacked arrangement can have any practicably suitable number of transistors. In this particular arrangement, four such MOSFETs are shown at 102, 104, 106 and 108. In this embodiment, MOSFET 108 serves as an input transistor and receives an input vin. The top transistor in the arrangement is connected to a supply voltage Vdd through a bias resistor Rbjas as shown. Individual transistors in the stack are operatively connected to individual respective resistors across their outputs. For example, transistor 108 is connected with resistor Rl, transistor 106 is connected with resistor R2, transistor 104 is connected with resistor R3 and so on. In addition, in this example, individual transistors other than the input transistor have a respective capacitor connected between its gate and ground, as well as a diode connected as shown. In the described embodiments, extra circuitry is added to a stack to turn it on, turn it off, and make it operate reliably which is discussed in more detail below.
The concept for this arrangement was originally published in IEEE Transactions on Power Electronics, VOL.15, NO.5, Sept. 2000, "Transformerless Capacitive coupling of Gate Signals for Series Operation of Power MOS Devices". This publication was specifically targeted at discrete part implementations and for stacks of only two or three transistors. The disclosed embodiments develop the circuit further, including applying the circuit to integrated circuits and to stacks of arbitrarily many transistors. Further, the embodiments "stabilize" the stack, giving it significantly greater reliability in operation. The inventive methods are applied to synthesize the necessary passive elements in silicon, elements for turn-on and elements for turn-off, making it possible to realize the embodiments as a fully integrated circuit on a silicon chip, an important improvement unknown to the September 2000 publication mentioned above. In at least one embodiment, means are provided in which the series connection of MOSFETs is turned on, turned off, and stabilized. Fig. 2 illustrates a specific example of an implemented stacked MOSFET generally at 200. This schematic shows a 2-device stacked MOSFET that includes a first transistor or MOSFET 202 connected to a bias voltage through bias resistor Rbias- The gate of transistor 202 is to ground through a capacitor 206. The output of the stacked MOSFET arrangement is taken across a plurality of resistors R as shown. An input transistor 204 is connected as shown as receives an input signal
Figs. 3a-d show simulated and measured results of this particular arrangement. With consideration of both Figs. 2 and 3a-d, consider the following. The turn on voltage of this circuit is accomplished through a capacitive voltage divider. This voltage divider is realized, in this embodiment, through the inserted gate capacitors (shown in Fig. 2 as C2 and, more generally, in Fig. 1 as C2, C3, ... Cn) and the inherent parasitic capacitances that exist across the gate-source of the MOSFET. By sizing the gate capacitors according to the design driven by the particular environment in which the circuit is to be employed, precise gate-source voltages which turn on each device in the stack when a logical "high" signal is applied to the bottom device of the stack can be provided. It is this ability to design for an exact on-state gate-source voltage which enables one to keep each device from exceeding its breakdown voltage while the entire stack controls very high voltages.
In implementation, these inserted gate capacitors can take the form of discrete capacitors or parasitic drain-source tied MOSFETs, depending on the particular application. The latter form, drain-source tied MOSFETs, is a unique contribution that allows for a reduction in the amount of die space required to implement the circuit as a fully integrated circuit. The turn-off of the circuit occurs when the control signal at the gate of the bottom MOSFET (i.e. the input transistor) goes to a logical "low". When this happens, all the MOSFETs turn off and the intermediate nodes of the circuit are free to take on the voltage dictated by the resistive voltage divider network. These resistances are sized equally and as such, cause each MOSFET to share an equal portion of the total voltage being controlled.
The implementation of this resistive voltage divider network can take many different forms depending on the application. Two specific forms that have been tested are discrete resistors and gate-source connected MOSFETs (diode- connected). The latter form, gate-source connected MOSFETs, is a unique contribution that allows for a reduction in the amount of die space required to implement the circuit as a fully integrated circuit.
The above two pieces of the operation are enough to make the circuit function for two and three device MOSFET stacks. When taller stacks are needed or desired, extra circuitry can be added to stabilize the circuit's operation. What is meant by "stabilize" is to improve reliability of operation. In integrated circuit fabrication processes the value of individual capacitors is +/- 20%. Because the gate-source voltage is entirely dependent on the size of the inserted gate capacitor, reliable operation is heavily dependent on this capacitor size. If it varies 20% the gate-source voltage can change by several volts, causing the transistor to burn up. The solution to this problem is adding another capacitor directly across the gate- source of each MOSFET in the stack. This capacitor can be sized, along with the previously discussed gate capacitor, to set how sensitive the stacked MOSFET will be to manufacturing variations. It is this added capacitor that enables arbitrarily tall stacks to operate reliably. Design Considerations
The various embodiments have unique circuit design advantages from both an economic stand point and a technical stand point. Specifically, whenever an electrical engineer approaches a switching problem he or she must always consider the breakdown voltage of the transistor being used, as will be appreciated by the skilled artisan. The transistor chosen must have a breakdown voltage greater than the voltages being switched. High breakdown voltage transistors are more expensive than low breakdown voltage transistors. As such, using inexpensive, low breakdown voltage, transistors to handle high- voltages can reduce the cost of the circuit.
Further, the above-described embodiments can reduce the number of different types of parts needed for a project, allowing for the use of bulk purchased parts in both low voltage and high voltage applications. Economic benefits can also be seen for integrated circuits. Integrated circuit fabrication processes that are capable of handling high- voltages are much more expensive than their low- voltage counterparts. By implementing the described embodiments in the less expensive, low-voltage, fabrication process, high-voltage control can be achieved for significantly less money.
From a technical point of view, there exist certain applications where the use of high breakdown voltage transistors is not possible. The most obvious of these applications is in integrated circuits. Most modern integrated circuit fabrication processes are optimized for minimum power consumption, high speed, and maximum integration density. Optimizing these parameters leads to the fabrication process not being able to meet the system requirements for high-voltage control. To mitigate this, off-chip parts are commonly added. This not only makes the part more expensive, but also adds significantly to the size of the part. The described embodiments can allow for the direct control of these high voltages in the integrated circuit itself. Such on-die high-voltage control can be especially significant in applications where the fabrication process has been specifically chosen for the environment in which it will operate (high temperature, low temperature, high pressure, high radiation, etc). Here, adding external parts is very expensive, and often prohibitive to the correct operation of the system.
In Operation
As discussed previously, the general category of application for the described embodiments is high- voltage switching and control. Two exemplary applications include by way of example and not limitation MEMS (Micro Electro- Mechanical Systems) device control and high voltage pulse width modulation.
MEMS devices are moving machines that are fabricated on the same scale as microelectronics. These small systems require high- voltages to switch them on and off. The described embodiments can enable the switching of these devices directly by microelectronics, further decreasing the overall system size and weight.
High- Voltage pulse width modulation (PWM) is the technique by which many switching feedback control systems operate. These feedback control systems have a logical component to them as well as a switching component to them. The logical component is a digital logic system that samples an output, processes it, and generates a corrective action based on what needs to be done. That corrective action is then fed to the switching component which adjusts the on/off time of the switch for the system. The logical end of this is almost always a fully integrated microelectronic system. The switching end of this is almost always a discrete MOSFET driver. By using the described embodiments in the switching portion of this system, the entire feedback control system can be integrated onto a single microelectronic die, reducing the size, weight, and cost.
Conclusion The disclosed systems provide a reliable means of switching high-voltages with solid-state transistors (i.e. MOSFETs). In the illustrated and described embodiments, the disclosed systems can extend the ability of solid-state transistors to switch voltages greater than their breakdown voltage by arranging a set of transistors in series and causing them to evenly share the high-voltage being controlled.
Although the invention has been described in language specific to structural features and/or methodological steps, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of implementing the claimed invention.

Claims

1. A shifter circuit comprising: a stack of MOSFETs operatively connected in a series arrangement, wherein the stack is configured to switch voltages that are greater than the breakdown voltage of at least one of the MOSFETs; a capacitive voltage divider operatively connected to the stack of MOSFETs and configured to turn on the shifter circuit; and a resistive voltage divider circuit operatively connected to the stack of MOSFETs and configured to provide an output voltage.
2. The shifter circuit of claim 1, wherein the stack is configured to switch voltages that are greater that the breakdown voltages of all of the MOSFETs of the stack.
3. The shifter circuit of claim 1, wherein the stack of MOSFETs is arranged to evenly share the voltage being controlled.
4. The shifter circuit of claim 1 , wherein the capacitive voltage divider comprises a plurality of capacitors, individual capacitors of which being connected with an individual respective gate of one of the MOSFETs.
5. The shifter circuit of claim 1, wherein the capacitive voltage divider comprises a plurality of capacitors, individual capacitors of which being connected with an individual respective gate of one of the MOSFETs, wherein the individual capacitors comprise discrete capacitors.
6. The shifter circuit of claim 1, wherein the capacitive voltage divider comprises a plurality of capacitors, individual capacitors of which being connected with an individual respective gate of one of the MOSFETs, wherein the individual capacitors comprise parasitic drain-source tied MOSFETs.
7. The shifter circuit of claim 1, wherein the resistive voltage divider circuit comprises a plurality of discrete resistors, individual ones of which being connected to individual respective MOSFETs.
8. The shifter circuit of claim 1, wherein the resistive voltage divider circuit comprises a plurality of gate-source connected MOSFETs.
9. The shifter circuit of claim 1 further comprising a plurality of capacitors, individual capacitors of which being connected across the gate-source of individual MOSFETs of the stack of MOSFETs.
10. The shifter circuit of claim 1, wherein the capacitive voltage divider comprises a plurality of capacitors, individual capacitors of which being connected with an individual respective gate of one of the MOSFETs.
11. The shifter circuit of claim 1, wherein the shifter circuit is disposed on a silicon chip.
12. A shifter circuit comprising: a stack of MOSFETs operatively connected in a series arrangement, wherein the stack is configured to switch voltages that are greater than the breakdown voltage of the MOSFETs that comprise the stack; a capacitive voltage divider operatively connected to the stack of MOSFETs and configured to turn on the shifter circuit, wherein the capacitive voltage divider comprises a plurality of capacitors, individual capacitors of which being connected with an individual respective gate of one of the MOSFETs; and a resistive voltage divider circuit operatively connected to the stack of MOSFETs and configured to provide an output voltage; wherein the shifter circuit is disposed on a silicon chip.
13. The shifter circuit of claim 12, wherein the stack of MOSFETs is arranged to evenly share the voltage being controlled.
14. The shifter circuit of claim 12, wherein the individual capacitors comprise discrete capacitors.
15. The shifter circuit of claim 12, wherein the individual capacitors comprise parasitic drain-source tied MOSFETs.
16. The shifter circuit of claim 12, wherein the resistive voltage divider circuit comprises a plurality of discrete resistors, individual ones of which being connected to individual respective MOSFETs.
17. The shifter circuit of claim 12, wherein the resistive voltage divider circuit comprises a plurality of gate-source connected MOSFETs.
18. The shifter circuit of claim 12 further comprising a plurality of capacitors, individual capacitors of which being connected across the gate-source of individual MOSFETs of the stack of MOSFETs.
PCT/US2006/035227 2005-09-12 2006-09-08 Stacked mosfets WO2007033045A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71632205P 2005-09-12 2005-09-12
US60/716,322 2005-09-12

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