JPH11163642A - Semiconductor device and high frequency circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a master slice type monolithic high frequency circuit with high versatility which forms a high frequency circuit that handles a small signal of a receiver level and a high frequency circuit that handles a large signal of a high output amplifier, etc., on the same substrate and a high frequency circuit using the above substrate as a component. SOLUTION: In a substrate provided with transistors which are repeatedly arranged in the order of a source S, a gate G, a drain D and a gate G and grounding conductors 29, this semiconductor device is configured by connecting mutually adjacent sources S of transistors that are not covered with the conductors 29, mutually adjacent gains G and mutually adjacent drains D by conductor in a through-hole 32 and wiring conductors 29 and 30. This high frequency circuit is configured with the semiconductor device as a component.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device for processing a high frequency signal of, for example, 1 GHz or more.

[0002]

2. Description of the Related Art In order to cope with the rapid development of mobile communication in recent years, a master slice monolithic microwave circuit (MMIC) has been developed as a method for realizing a radio IC in a short development period and at a low manufacturing cost. Has been proposed.

In a master slice type MMIC, an active element, a resistor, and a capacitor are previously formed on a semiconductor substrate.
By using the same semiconductor substrate and changing the configuration method of the transmission line formed on the substrate, various high-frequency circuits can be formed. That is, a large number of master slice type MMIC semiconductor substrates are manufactured in advance, and a high-frequency circuit is realized by using a large amount of the semiconductor substrates, so that a short development period and low manufacturing cost can be realized. Therefore, it was necessary to determine the shapes and sizes of the active elements, resistors, and capacitors on the MMIC semiconductor substrate so that the versatility of the substrate became as high as possible.

FIGS. 7 and 8 show a master slice type MMIC.
And a symposium of the Institute of Electrical and Electronics Engineers (IEEE 1996 Microwave and Millimeter-w
1 is a configuration diagram of a master slice type MMIC announced at aveCircuit Symposium. In FIG. 7, a large number of active elements 2, a resistor 21, and a lower electrode conductor 6 for a thin film capacitor are formed on one surface of a semiconductor substrate 1. Here, one active element 2, two resistors 21, and three lower electrode conductors 6 of the thin film capacitor are combined to form one set (unit cell). (Array form). Using this as a common substrate, a dielectric film 23 and a ground conductor 25 are formed on the upper surface. The dielectric film 23 and the ground conductor 25 on the device to be used are opened according to the layout of the functional circuit to be realized. Ground conductor 2
A dielectric film 28 having a thickness of, for example, about 1 to 10 μm is formed on the dielectric film 5, and a wiring conductor 29 is formed on the dielectric film 28. The wiring conductor 29 and the element on the common substrate are connected by a through hole 31. In the MMIC configured as described above, the arrangement of the active elements 2 such as a field effect transistor (FET) is predetermined, so that the semiconductor substrate 1 can be shared by various circuits, thereby reducing manufacturing costs and developing. The period can be shortened. Further, by covering unused elements with a ground conductor, wiring can be formed on these unused elements, so that downsizing of the circuit can be realized.

Further, since the unused elements are covered with the ground conductor, the passive circuits formed on the ground conductor, that is, on the wiring layer are the same as those in which the unused active elements do not exist. For this reason, wiring flexibility is high,
Extra wiring such as bypassing the active element can be avoided, and the influence of parasitic inductance and capacitance can be reduced. FIGS. 8A and 8B show examples of active elements formed on a common substrate. FIG. 8A shows an FET having a gate width of 100 μm and a π-type FET having a gate width of 200 μm. ) Is an FET having a gate width of 200 μm in which a gate width of 50 μm is formed in a comb shape. As described above, in the conventional common substrate for a master slice type MMIC, the unit FET has a gate width of about 200 μm.

[0006]

However, when an attempt is made to realize a high-output amplifier having a relatively high signal level using such a common substrate for a master slice type MMIC, a plurality of high-output amplifiers are required to obtain a desired output power. It is necessary to connect the unit cells described above to synthesize the FETs, so that the length of wiring and the like for synthesizing the FETs becomes longer, and there is a problem that the synthesis loss increases. Also, a method of realizing a circuit that handles a high-level signal using another master slice type MMIC common substrate in which the size of the FET formed in the unit cell is increased, and the size of the FET formed in the unit cell on the same substrate Can be considered as two or more types. However, the versatility of having to prepare another common substrate is reduced, and the FET used in the circuit handling low-level signals and the FET used in the circuit handling high-level signals are different. For this reason, there has been a problem that the use efficiency of the elements on the common substrate is reduced and the degree of circuit integration is reduced.

An object of the present invention is to provide a highly versatile master slice type monolithic high frequency circuit in which a high frequency circuit for handling a small signal at the receiver level and a high frequency circuit for handling a large signal such as a high output power amplifier can be formed on the same substrate. The purpose is to realize a substrate.

[0008]

According to the present invention, a unit transistor in which a source, a gate, a drain, and a gate are repeatedly arranged in this order is integrated, and a substrate provided with a ground conductor is covered with the ground conductor. All sources adjacent to each other of the unit transistors which are not
The above object is attained by a master slice type monolithic high frequency circuit substrate, wherein all adjacent gates and all adjacent drains are connected to each other. Here, the “unit transistor” is a transistor including one adjacent source, one gate, and one drain.

Further, according to the present invention, in a master slice type monolithic high frequency circuit formed using the master slice type monolithic high frequency circuit substrate,
The transistor is characterized by using all the gate electrodes of the unit transistor which are not covered with the ground conductor.

Further, according to the present invention, in a master slice type monolithic high frequency circuit formed using the master slice type monolithic high frequency circuit substrate,
The connection is made so that only a part of the unit transistor is used.

Also, in the master slice type monolithic high frequency circuit formed using the master slice type monolithic high frequency circuit substrate, unit transistors are connected so as to be a combination of at least two or more independent transistors. I do.

Further, according to the present invention, in a master slice type monolithic high frequency circuit formed using the master slice type monolithic high frequency circuit substrate,
The unit transistors are connected to form a combination of at least one or more transistors and at least one or more signal control elements.

In the configuration according to the present invention, the size of the power amplifying transistor on the common substrate for the master slice type MMIC is configured to obtain an output power of at least 20 dBm or more. Therefore, when a power amplifier is configured using this common substrate, it is not necessary to connect a large number of transistors, the combined loss can be suppressed to a small value, and good amplifier characteristics can be obtained. Further, since the transistor can be formed by connecting only a part of the arrangement of the unit transistors, the size of the active element can be freely changed. Further, since the unit transistor can be connected as two or more independent active elements, even if a large-sized active element for high output is formed on the common substrate,
The number of active elements that can be used does not decrease. Therefore, a high-frequency circuit for handling small signals and a high-frequency circuit for handling large signals can be simultaneously formed on the same common substrate, and a very versatile common substrate for a master slice type MMIC can be realized.

[0014]

(Embodiment 1) FIGS. 1 and 2 show a first embodiment of the present invention. This embodiment corresponds to claims 1 and 4.

In FIG. 2A, the master slice type M
FIG. 2 shows a plan view of an arrangement of unit field effect transistors (unit FETs) formed on a semiconductor substrate for MIC by using a semiconductor process. This array has a source S, a gate G,
In this configuration, a combination of the drain D and the gate G is repeatedly arranged. FIG. 2B is an equivalent circuit in which drains or sources of adjacent unit FETs are coupled. In this embodiment, it is assumed that there are ten or more gate electrodes. FIG. 1A shows a case where all the sources, drains, and gates of the unit FET configured as shown in FIG. 2 are coupled to each other. The gates are connected by a wiring conductor 30, and the wiring conductor 30 is formed by the same process as the ground conductor. The source and the drain are connected by a wiring conductor 29 on the dielectric film via a through-hole 32 penetrating through the dielectric film formed on the ground conductor 25 and the wiring conductor 30. The source terminals at both ends are covered with a ground conductor 25 and are electrically connected thereto. Further, the number of the unit FETs connected by the above common wiring is such that a signal is input to the gate of the FET,
When the source is grounded and a signal is output from the drain, the number is set so that the output signal becomes 20 dBm or more. By configuring a group of unit FETs (hereinafter simply referred to as FETs) that operate as one transistor by the common wiring as described above, the number of combined FETs decreases as the output power of one FET increases. Therefore, good high-frequency characteristics can be obtained because the loss at the time of synthesis can be reduced. One FET is one unit FE
It may be T.

Note that the FET is a bipolar transistor,
GaAs substrate, In, MOS transistor, HEMT, etc.
Any device formed on a P substrate or a Si substrate may be used. However, in the case of a bipolar transistor, the emitter, base, and collector are
Corresponding to the source, gate, and drain.

(Embodiment 2) FIG. 3 (a) shows a configuration diagram of a second embodiment of the present invention. This embodiment corresponds to claims 1 and 5.

The present embodiment is characterized in that a part of the unit FET of the first embodiment shown in FIG. FIG. 3B shows an equivalent circuit diagram. With the above configuration, the size of the FET can be changed by increasing or decreasing the area of the portion covered by the ground conductor. Accordingly, since the FET can be easily realized by being divided into a small size for small signals and a large size for large signals, the small signal circuit and the large signal circuit can be formed on the same substrate.

The FET is a bipolar transistor,
GaAs substrate, In, MOS transistor, HEMT, etc.
Any device formed on a P substrate or a Si substrate may be used. However, in the case of a bipolar transistor, the emitter, base, and collector are
Corresponding to the source, gate, and drain.

(Embodiment 3) FIG. 4 (a) shows a configuration diagram of a third embodiment of the present invention. This embodiment corresponds to claims 1, 5, and 6.

In this embodiment, a part of the FET of the first embodiment shown in FIG. 2 is covered with a ground conductor, and at least two combinations of SGDGS constituting the FET are provided. And they are independent of each other by ground conductors.
FIG. 4B shows an equivalent circuit diagram. With the above configuration, two or more independently operating FETs can be formed from an array of unit FETs in a row.
Therefore, the number of FETs that can be used in a circuit can be easily increased or decreased in one master slice substrate, so that both high integration of the circuit and realization of a large signal circuit such as a high-output amplifier can be achieved.

The sizes of FETs that can operate independently may be the same or different. Also,
The FET may be any device formed on a GaAs substrate, InP substrate, or Si substrate, such as a bipolar transistor, a MOS transistor, and a HEMT. However, in the case of a bipolar transistor, the emitter, base, and collector correspond to the source, gate, and drain of the FET, respectively.

(Embodiment 4) FIG. 5A shows a configuration diagram of a fourth embodiment of the present invention. This embodiment corresponds to claims 2 and 7.

In this embodiment, a part of the unit FET of the first embodiment shown in FIG. 2 is covered with a ground conductor 25, and the gate of the S-G-D unit FET in contact with the ground conductor 25 is added. Is independent of the gate of the unit FET. FIG. 5B shows an equivalent circuit diagram, and FIG. 5C shows a simplified equivalent circuit. C and C 'surrounded by broken lines in the figure indicate the same ones. With the above configuration, the SGD FET in contact with the ground conductor can function as a variable resistor by applying a voltage to the gate,
An FET including a control element capable of controlling a signal as the whole array of the unit FETs is obtained. FIG. 6 shows, on a Smith chart, the input impedance of the gate and drain of the FET when the resistance of the variable resistor is changed. The input impedance of the gate does not change even if the resistance of the variable resistor changes. When the resistance value of the variable resistor changes, the input impedance of the drain greatly changes in accordance with the change of the resistance value of the variable resistor. Therefore, with the structure described in this embodiment, an FET including a control element can be easily formed, and the output signal of the FET and the input impedance of the drain can be changed.

Also, in this embodiment, the grounded SGD
Was used as the control element, but the FE of the grounded DGS was
Using T as a control element is equivalent to connecting a resistor to the source of the FET, so that the output signal of the FET can also be controlled by this method.

The FET is a bipolar transistor,
MOS transistors, HHEMT, etc., GaAs substrates and I
Any device formed on an nP substrate or a Si substrate may be used. However, in the case of a bipolar transistor, the emitter, base, and collector are
Corresponding to the source, gate, and drain.

In this embodiment, the grounded SGD FET which operates as a control element is formed only on one side of the array of unit FETs.
The SGD FETs may be configured on both sides of the unit FET array. By configuring as above, the unit FET
This is equivalent to connecting two variable resistors in parallel in this arrangement, and the resistance value of the variable resistor can be changed more greatly, so that the input impedance of the drain of the FET can be changed more greatly.

[0028]

As described above, in the semiconductor device of the present invention, in the structure of the master slice type MMIC substrate, the transistors are formed with a size having an output power of at least 20 dBm. As a result, the number of transistors used in the circuit can be reduced to reduce the combined loss. Also,
By selecting the number of unit transistors that constitute one transistor, the size of the transistor can be freely changed, and a circuit with a small signal level and a circuit with a large signal level can be formed over the same substrate. Therefore, an extremely versatile master slice type MMIC substrate can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration and an equivalent circuit of a first embodiment.

FIG. 2 is a diagram illustrating an arrangement of unit FETs and an equivalent circuit according to the first embodiment.

FIG. 3 is a diagram illustrating a configuration and an equivalent circuit according to a second embodiment.

FIG. 4 is a diagram illustrating a configuration and an equivalent circuit according to a third embodiment.

FIG. 5 is a diagram illustrating a configuration and an equivalent circuit according to a fourth embodiment.

FIG. 6 is a diagram showing a change in the input impedance of the FET when the resistance value of the variable resistor is changed.

FIG. 7 is a three-dimensional view showing a configuration example of a conventional master slice type MMC.

FIG. 8 is a plan view showing a configuration example of a conventional master slice type MMC.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Active element, 6 ... Conductor for the lower electrode of a thin film capacitor, 21 ... Resistor, 23, 28 ... Dielectric film,
25 ... ground conductor, 29, 30 ... wiring conductor, 31, 32 ...
Through hole.

Claims (7)

[Claims] 1. A unit transistor in which unit transistors repeatedly arranged in the order of a source, a gate, a drain, and a gate are integrated and include a substrate provided with a ground conductor, and are not covered with the ground conductor. Wherein all adjacent sources, all adjacent gates, and all adjacent drains are connected to each other. 2. The unit transistor, wherein a unit transistor in which a source, a gate, a drain, and a gate are repeatedly arranged in this order is integrated and includes a substrate provided with a ground conductor, and is not covered with the ground conductor. A semiconductor device, wherein all adjacent sources and all adjacent drains are connected to each other, and all gates except one at one end among all adjacent gates are connected to each other. 3. The unit transistor in which a unit transistor in which a source, a gate, a drain, and a gate are repeatedly arranged in this order is integrated and includes a substrate provided with a ground conductor, and is not covered with the ground conductor. A semiconductor device, wherein all adjacent sources and all adjacent drains are connected to each other, and all gates except for one at both ends of all adjacent gates are connected. 4. A high-frequency circuit comprising the semiconductor device according to claim 1, 2 or 3, wherein all the unit transistors are connected so as to be used. 5. A high-frequency circuit comprising the semiconductor device according to claim 1, 2 or 3, wherein only a part of the unit transistors is connected. 6. A high-frequency circuit including the semiconductor device according to claim 1, wherein the unit transistors are connected such that a combination of at least two or more independent transistors is configured. A high frequency circuit characterized by the following. 7. A high-frequency circuit including the semiconductor device according to claim 1, wherein at least one or more transistors and at least one or more signal control elements are combined. A high-frequency circuit, wherein the unit transistors are connected.