JPH1079467A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1079467A
JPH1079467A JP8233845A JP23384596A JPH1079467A JP H1079467 A JPH1079467 A JP H1079467A JP 8233845 A JP8233845 A JP 8233845A JP 23384596 A JP23384596 A JP 23384596A JP H1079467 A JPH1079467 A JP H1079467A
Authority
JP
Japan
Prior art keywords
circuits
control circuit
substrate
negative voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8233845A
Other languages
Japanese (ja)
Inventor
Yoshinobu Sasaki
善伸 佐々木
Kimimasa Maemura
公正 前村
Kazuya Yamamoto
和也 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8233845A priority Critical patent/JPH1079467A/en
Priority to KR1019970002274A priority patent/KR19980023927A/en
Priority to DE19721448A priority patent/DE19721448A1/en
Publication of JPH1079467A publication Critical patent/JPH1079467A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/7605Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Transceivers (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent leak of an RF signal from being generated by a method, wherein a semiconductor device is provided with a semiconductor substrate, a plurality of circuits provided on the substrate at a prescribed interval, and ground metal films provided on regions which are respectively held between the circuits on the substrate. SOLUTION: An LNA 1, an SW 3, an HPA 5, a control circuit 2 and a negative voltage-generating circuit 4 are arranged on a GaAs substrate 10 at prescribed intervals and, at the same time, the circuits 2 and 4 are arranged adjacent to each other, and ground metal films 6 are respectively arranged on the substrate 10 under a region held between these circuits 2 and 4 and the LNA 1 and the SW 3, and on the substrate 10 under a region held between the circuits 2 and 4 and the HPA 5. These films 6 are earthed, when the fellow circuits on this MMIC 100 are connected with each other or when the circuits on this MMIC 100 and other circuits than the MMIC 100 are connected with each other. Thereby the amount of isolation for the circuits is increased, and a leak of RF signal which is generated between the circuits can be prevented from being generated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は半導体装置に関
し、特に移動体通信に用いられるGaAsIC等の半導
体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a GaAs IC used for mobile communication.

【0002】[0002]

【従来の技術】図5は従来のGaAs基板を用いたMM
IC(Microwave monolithic integrated circuit) の構
造を模式的に示す平面図であり、図において、50はM
MIC、1は−30〜−60dBmの出力レベルで動作
する低雑音増幅器(以下、LNAと称す)、2は0/3
Vの基準電圧で動作する制御回路で、その内部の論理振
幅は約0/0.6Vとなっている。3はスイッチ(以
下、SWと称す)、4は−10dBmの入力信号レベル
で動作する負電圧発生回路、5は20〜22dBmの出
力信号レベルで動作する高出力増幅器(以下、HPAと
称す)で、電圧の振幅は0/6Vとなっている。10は
GaAs基板である。
2. Description of the Related Art FIG. 5 shows an MM using a conventional GaAs substrate.
1 is a plan view schematically showing a structure of an IC (Microwave monolithic integrated circuit), in which 50 denotes M
MIC 1 is a low noise amplifier (hereinafter referred to as LNA) operating at an output level of -30 to -60 dBm, and 2 is 0/3
The control circuit operates at a reference voltage of V, and its internal logic amplitude is about 0 / 0.6V. Reference numeral 3 denotes a switch (hereinafter referred to as SW), 4 denotes a negative voltage generating circuit that operates at an input signal level of -10 dBm, and 5 denotes a high output amplifier (hereinafter referred to as HPA) that operates at an output signal level of 20 to 22 dBm. , And the voltage amplitude is 0 / 6V. Reference numeral 10 denotes a GaAs substrate.

【0003】また、図6は従来のMMICの信号の流れ
を示すブロック図であり、図において、図5と同一符号
は同一または相当する部分を示しており、7はアンテ
ナ、8は信号処理IC、P1〜P9は入力ポート及び出
力ポートである。
FIG. 6 is a block diagram showing a signal flow of a conventional MMIC. In the figure, the same reference numerals as those in FIG. 5 denote the same or corresponding parts, 7 is an antenna, and 8 is a signal processing IC. , P1 to P9 are an input port and an output port.

【0004】このMMIC50は、移動体通信の信号の
送受信部に用いられるMMICであり、このMMIC5
0においては、HPA5,LNA1,SW3,制御回路
2,および負電源発生回路4が互いに所定の間隔を隔て
てGaAs基板10上に配置されている。そして、この
MMIC50は実装基板(図示せず)やパッケージ(図
示せず)等に取り付けられて、図6に示すように、MM
IC50の外部に設けられているアンテナ7や、信号処
理IC8等と接続される。
The MMIC 50 is an MMIC used for a transmission / reception unit of a signal for mobile communication.
At 0, the HPAs 5, LNA 1, SW 3, control circuit 2, and negative power supply generation circuit 4 are arranged on the GaAs substrate 10 at a predetermined interval. The MMIC 50 is attached to a mounting board (not shown), a package (not shown), or the like, and as shown in FIG.
It is connected to the antenna 7 provided outside the IC 50, the signal processing IC 8, and the like.

【0005】次に、従来のMMICの動作について図6
を用いて説明する。まず、受信動作時には、アンテナ7
からの入力波はSW3にて受信系へ切り替えられてLN
A1により増幅されてMMIC50の外部の信号処理I
C8に出力される。つまり、MMIC50外部のアンテ
ナ7から入力された約−40dBmの入力信号は、ポー
トP1からMMIC50に入力され、SW3によりポー
トP1とポートP9とが接続されて、ポートP9から出
力された後、ポートP8からLNA1に入力されて−3
0dBmに増幅され、ポートP7より出力されてMMI
C50外部に設けられた信号処理IC8にRF入力信号
として入力される。
Next, the operation of the conventional MMIC will be described with reference to FIG.
This will be described with reference to FIG. First, during the reception operation, the antenna 7
Input wave is switched to the receiving system by SW3 and LN
A1 which is amplified by A1 and is external to the MMIC 50
Output to C8. That is, the input signal of about −40 dBm input from the antenna 7 outside the MMIC 50 is input from the port P1 to the MMIC 50, the port P1 and the port P9 are connected by the SW3, and is output from the port P9. -3
0dBm, output from port P7, and
It is input as an RF input signal to a signal processing IC 8 provided outside the C50.

【0006】送信動作時においては、SW3は送信系に
切り換えられ、MMICに入力された出力信号がHPA
5により増幅されてアンテナ7から送信される。つま
り、信号処理IC8から出力された約0dBmのRF出
力信号は、ポートP4からMMIC50に入力され、H
PA5において約20dBmに増幅されてポートP3か
ら出力された後、ポートP2からSW3に入力され、ポ
ートP1を経てアンテナから約20dBmの出力信号が
出力される。
At the time of transmission operation, SW3 is switched to the transmission system, and the output signal input to the MMIC is changed to HPA.
5 and transmitted from the antenna 7. That is, the RF output signal of about 0 dBm output from the signal processing IC 8 is input from the port P4 to the MMIC 50,
After being amplified to about 20 dBm in PA5 and output from port P3, it is input from port P2 to SW3, and an output signal of about 20 dBm is output from the antenna via port P1.

【0007】このとき、制御回路2は、送受信のタイミ
ングを図りながらHPA5,LNA1,及びSW3への
バイアスの設定を行い、SW3の接続状態等を切り換え
て送受信の切り換えを行っている。この制御回路2に
は、MMIC50を含む装置の電源電圧,例えば3V
と、接地である0VがポートP5から印加されている。
また、負電圧発生回路4においては、ポートP6から入
力されるMMIC50の外部の発振器により発生される
約−10dBmのRF信号から、制御回路2から出力さ
れるHPA5,SW3へのバイアスのうちの負電圧の基
準電圧−1Vを発生させている。このMMIC50にお
いては、LNA1とHPA5とは同時に動作することは
ないが、制御回路2および負電圧発生回路4は常に動作
している。
At this time, the control circuit 2 sets the bias to the HPAs 5, LNA1, and SW3 while taking the transmission and reception timing into account, and switches the connection state of the SW3 to switch between transmission and reception. The control circuit 2 has a power supply voltage of a device including the MMIC 50, for example, 3V.
And 0 V, which is ground, is applied from the port P5.
Also, in the negative voltage generation circuit 4, the negative of the bias to the HPAs 5 and SW 3 output from the control circuit 2 is obtained from the RF signal of about −10 dBm generated by the external oscillator of the MMIC 50 input from the port P 6. A reference voltage of -1 V is generated. In the MMIC 50, the LNA 1 and the HPA 5 do not operate at the same time, but the control circuit 2 and the negative voltage generation circuit 4 always operate.

【0008】[0008]

【発明が解決しようとする課題】以上のように、従来の
MMICは基板上に複数の回路が所定の間隔を隔て配置
された構造を備えていた。しかしながら、MMICの基
板の大きさを大きくすることは、コスト等の面から限界
があるため、各回路間の間隔を十分に広くすることがで
きず、このため、上記のように基板上の各回路に入力あ
るいは出力される電力が−40dBm〜20dBmと大
きく異なっている場合においては、各回路間のアイソレ
ーションが不十分となり、RF信号の回路間の漏れによ
りMMICの特性が安定しないという問題があった。
As described above, the conventional MMIC has a structure in which a plurality of circuits are arranged at predetermined intervals on a substrate. However, increasing the size of the substrate of the MMIC is limited in terms of cost and the like, and it is not possible to sufficiently increase the interval between the circuits. If the power input to or output from the circuit is significantly different from −40 dBm to 20 dBm, the isolation between the circuits becomes insufficient, and the characteristics of the MMIC become unstable due to leakage between the RF signals. there were.

【0009】一方、このような回路間の信号の漏れを解
消するために、基板上の複数の回路に挟まれた領域に低
抵抗なn型領域を設け、その一部を基板裏面の接地電極
と接続した半導体装置が特開平5−1144931号公
報に、また、フロントエンド回路ブロックと、IF増幅
回路ブロックとを基板上に集積化するとともに、フロン
トエンド回路ブロックの周囲を高濃度分離領域によって
囲むようにしたものが特開平2−23635号公報に、
また、第1の回路ブロックと第2の回路ブロックとを高
濃度拡散領域により素子分離した構造が特開平3−68
53号公報にそれぞれ開示されている。このような構造
の半導体装置においては、接地した低抵抗n型領域や高
濃度分離層や高濃度拡散領域により、回路間のアイソレ
ーションを保って、信号漏れ等の回路間の干渉を防止す
ることが可能となるため、この低抵抗領域等を上記従来
のMMICの各回路間に設けることにより、RF信号の
回路間の漏れを低減させることが可能となる。
On the other hand, in order to eliminate such signal leakage between circuits, a low-resistance n-type region is provided in a region between a plurality of circuits on the substrate, and a part of the n-type region is provided on the back surface of the substrate. Japanese Patent Laid-Open Publication No. 5-1144931, discloses a semiconductor device integrated with a front-end circuit block and an IF amplifier circuit block on a substrate, and surrounds the front-end circuit block with a high-concentration isolation region. Japanese Patent Application Laid-Open No. Hei 23-23635 discloses a method for
A structure in which the first circuit block and the second circuit block are separated by a high-concentration diffusion region is disclosed in Japanese Patent Laid-Open No. 3-68.
No. 53, respectively. In a semiconductor device having such a structure, isolation between circuits is prevented by a grounded low-resistance n-type region, a high-concentration separation layer, or a high-concentration diffusion region, and interference between circuits such as signal leakage is prevented. Therefore, by providing the low resistance region and the like between the circuits of the conventional MMIC, it is possible to reduce the leakage of the RF signal between the circuits.

【0010】しかしながら、このような低抵抗なn型領
域や高濃度分離層や高濃度拡散領域のように、半導体基
板にn型不純物を導入して形成した領域は、その抵抗値
を十分に小さなものとすることができず、アイソレーシ
ョン量を十分に大きくすることができるものではない。
したがって、特に上述した従来のMMIC50のよう
に、約−10dBmの小さい出力の信号で動作する負電
圧発生回路4や0/0.6Vの論理振幅で動作する制御
回路2と、これらよりも出力レベル差の大きい信号で動
作するその他の回路、例えば、約20dBmの出力信号
レベルにより0/6Vの電圧で動作するHPA、約−3
0dBmの出力信号レベルで動作するLNA、約20d
Bmの出力信号レベルと約−40dBmの出力信号レベ
ルとで動作するSWとを備えたものにおいては、制御回
路2及び負電圧発生回路4とその他の回路との間の信号
のレベルが大きく異なるため、回路間に、接地した低抵
抗なn型領域や高濃度分離層等を設けただけでは、制御
回路2及び負電圧発生回路4と、その他の回路とのアイ
ソレーションが不十分となり、小出力信号で動作する回
路がRF信号漏れの影響を受けやすく、特性が安定しな
い場合が多いという問題があった。
However, a region formed by introducing an n-type impurity into a semiconductor substrate, such as a low-resistance n-type region, a high-concentration separation layer, or a high-concentration diffusion region, has a sufficiently small resistance value. Therefore, the isolation amount cannot be sufficiently increased.
Therefore, in particular, as in the above-described conventional MMIC 50, the negative voltage generating circuit 4 which operates with a signal having a small output of about -10 dBm, the control circuit 2 which operates with a logical amplitude of 0 / 0.6V, and an output level higher than these. Other circuits that operate with signals with large differences, such as HPA that operates at a voltage of 0/6 V with an output signal level of about 20 dBm, about -3
LNA operating at 0 dBm output signal level, about 20d
In the case of the one having the SW operating at the output signal level of Bm and the output signal level of about -40 dBm, the signal levels between the control circuit 2 and the negative voltage generation circuit 4 and the other circuits are greatly different. The mere provision of a grounded low-resistance n-type region or a high-concentration separation layer between the circuits results in insufficient isolation between the control circuit 2 and the negative voltage generation circuit 4 and other circuits, and a small output. There is a problem that a circuit operated by a signal is easily affected by RF signal leakage, and characteristics are often unstable.

【0011】この発明は上記のような問題点を解消する
ためになされたものであり、基板上に配置された複数の
回路間で発生するRF信号漏れによる特性の劣化を防ぐ
ことができる半導体装置を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor device capable of preventing deterioration in characteristics due to RF signal leakage occurring between a plurality of circuits arranged on a substrate. The purpose is to provide.

【0012】[0012]

【課題を解決するための手段】この発明に係る半導体装
置は、半導体基板と、半導体基板上に互いに所定の間隔
を隔てて設けられた複数の回路と、半導体基板上の、複
数の回路に挟まれた領域上に設けられた接地金属膜とを
備えるようにしたものである。
A semiconductor device according to the present invention comprises a semiconductor substrate, a plurality of circuits provided on the semiconductor substrate at predetermined intervals, and a plurality of circuits on the semiconductor substrate. And a ground metal film provided on the separated region.

【0013】また、複数の回路は、信号レベルの異なる
複数の回路からなり、接地金属膜は、複数の回路のうち
の他の回路に対する信号レベル差が大きい一つ以上の回
路と、他の回路との間に設けられているようにしたもの
である。
The plurality of circuits include a plurality of circuits having different signal levels, and the ground metal film includes at least one circuit having a large signal level difference with respect to another circuit among the plurality of circuits and another circuit. And between them.

【0014】また、複数の回路は、負電圧発生回路、制
御回路、スイッチ、低雑音増幅器、及び高出力増幅器か
らなり、負電圧発生回路及び制御回路は互いに隣接して
配置されており、接地金属膜は、半導体基板上の負電圧
発生回路及び制御回路と、他の回路とに挟まれた領域上
に設けられているようにしたものである。
The plurality of circuits include a negative voltage generating circuit, a control circuit, a switch, a low noise amplifier, and a high output amplifier. The negative voltage generating circuit and the control circuit are arranged adjacent to each other, The film is provided on a region between the negative voltage generation circuit and the control circuit on the semiconductor substrate and another circuit.

【0015】また、負電圧発生回路を−10dBm以上
−8dBm以下の入力信号レベルで動作するものとし、
制御回路を0Vと3Vの基準電圧で動作するものとし、
低雑音増幅器を−60dBm以上−30dBm以下の出
力信号レベルで動作するものとし、高出力増幅器は20
dBm以上22dBm以下の出力信号レベルで動作する
ものとしたものである。
Further, the negative voltage generating circuit operates at an input signal level of -10 dBm or more and -8 dBm or less,
Assume that the control circuit operates with reference voltages of 0V and 3V,
The low-noise amplifier operates at an output signal level of -60 dBm or more and -30 dBm or less, and
It operates at an output signal level of not less than dBm and not more than 22 dBm.

【0016】また、接地金属膜は、複数の回路のいずれ
かに設けられた金属配線と同じ材料からなるようにした
ものである。
Further, the ground metal film is made of the same material as the metal wiring provided in any of the plurality of circuits.

【0017】また、この発明に係る半導体装置は、半導
体基板と、半導体基板上に互いに所定の間隔を隔てて配
置された負電圧発生回路、制御回路、スイッチ、低雑音
増幅器、及び高出力増幅器とからなり、負電圧発生回路
及び制御回路は、互いに隣接して基板の一端側に配置さ
れており、高出力増幅器及びスイッチは、互いに隣接し
て基板の一端に対して反対側の端部側に配置されてお
り、負電圧発生回路及び制御回路の入力端子及び出力端
子は、基板の一端側に配置され、高出力増幅器及びスイ
ッチの入力端子及び出力端子は、基板の一端に対して反
対側の端部側に配置されているようにしたものである。
Further, according to the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a negative voltage generating circuit, a control circuit, a switch, a low-noise amplifier, and a high-output amplifier disposed on the semiconductor substrate at predetermined intervals from each other. Wherein the negative voltage generating circuit and the control circuit are arranged adjacent to each other on one end side of the substrate, and the high-power amplifier and the switch are arranged adjacent to each other and on the opposite end side to one end of the substrate. The input terminal and the output terminal of the negative voltage generation circuit and the control circuit are disposed on one end side of the substrate, and the input terminal and the output terminal of the high power amplifier and the switch are disposed on the opposite side to one end of the substrate. It is arranged on the end side.

【0018】また、半導体装置において、半導体基板上
の、負電圧発生回路及び制御回路と高出力増幅器及びス
イッチとに挟まれた領域上に、接地金属膜を備えるよう
にしたものである。
Further, in the semiconductor device, a ground metal film is provided on an area between the negative voltage generating circuit and the control circuit, the high-output amplifier and the switch on the semiconductor substrate.

【0019】[0019]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施の形態1.図1は本発明の実施の形態1に係るMM
IC(Microwave monolithic integrated circuit) の構
造を示す平面図であり、図において、100はMMI
C、1は−60以上−30dBm以下の出力レベルで動
作する低雑音増幅器(以下、LNAと称す)、2は0/
3Vの入力レベルにより、内部論理振幅が0/0.6V
で動作する制御回路、3は制御回路2から出力される0
Vと−2以上−1V未満の基準電圧で動作するスイッチ
(以下、SWと称す)、4は−10以上−8dBmの入
力信号レベルで動作する負電圧発生回路、5は20以上
22dBm以下の出力信号レベルで動作する高出力増幅
器(以下、HPAと称す)、6は厚さ約2μmで幅が約
80μmである金等の金属からなる接地金属膜で、この
接地金属膜6はMMIC100の動作時には接地され
る。なお、この接地金属膜6は上記各回路に金等の金属
配線を形成する際に同時に形成する。10はGaAs基
板である。
Embodiment 1 FIG. FIG. 1 shows an MM according to Embodiment 1 of the present invention.
1 is a plan view showing the structure of an IC (Microwave monolithic integrated circuit), in which 100 is an MMI.
C, 1 is a low noise amplifier (hereinafter referred to as LNA) operating at an output level of −60 dBm to −30 dBm, 2 is 0 /
With an input level of 3V, the internal logic amplitude is 0 / 0.6V
, The control circuit 3 operates at 0
A switch (hereinafter, referred to as SW) that operates at V and a reference voltage of −2 to less than −1 V, 4 is a negative voltage generation circuit that operates at an input signal level of −10 to −8 dBm, and 5 is an output of 20 to 22 dBm A high-power amplifier (hereinafter referred to as HPA) operating at a signal level, 6 is a ground metal film made of a metal such as gold having a thickness of about 2 μm and a width of about 80 μm, and this ground metal film 6 is used when the MMIC 100 operates. Grounded. The ground metal film 6 is formed at the same time when a metal wiring such as gold is formed in each circuit. Reference numeral 10 denotes a GaAs substrate.

【0020】また、図2は本発明の実施の形態1に係る
MMICの信号の流れを示すブロック図であり、図にお
いて、図1と同一符号は同一または相当する部分を示し
ており、7はMMIC100の外部に設けられているア
ンテナ、8はMMIC100の外部に設けられている信
号処理IC、P1〜P9は入力ポート及び出力ポートで
ある。
FIG. 2 is a block diagram showing a signal flow of the MMIC according to the first embodiment of the present invention. In FIG. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and FIG. An antenna provided outside the MMIC 100, 8 is a signal processing IC provided outside the MMIC 100, and P1 to P9 are input ports and output ports.

【0021】次に構造について説明する。このMMIC
100は、図1に示すように、GaAs基板10上にL
NA1,SW3,HPA5,制御回路2,及び負電圧発
生回路4を所定の間隔を隔てて配置するとともに、制御
回路2と負電圧発生回路4とを隣接して配置し、この制
御回路2及び負電圧発生回路4と、LNA1及びSW3
とに挟まれた領域、並びに、制御回路2及び負電圧発生
回路4と、HPA5とに挟まれた領域のGaAs基板1
0上に接地金属膜6を配置したものである。この接地金
属膜6はこのMMIC100の各回路同士、あるいはこ
のMMIC100の各回路とこのMMIC100外の回
路とが接続される際に接地される。
Next, the structure will be described. This MMIC
As shown in FIG. 1, L
NA1, SW3, HPA5, control circuit 2, and negative voltage generation circuit 4 are arranged at predetermined intervals, and control circuit 2 and negative voltage generation circuit 4 are arranged adjacent to each other. Voltage generation circuit 4, LNA1 and SW3
And the GaAs substrate 1 in a region sandwiched between the control circuit 2 and the negative voltage generation circuit 4 and the HPA 5
In this example, the ground metal film 6 is disposed on the reference numeral 0. The ground metal film 6 is grounded when each circuit of the MMIC 100 or each circuit of the MMIC 100 is connected to a circuit outside the MMIC 100.

【0022】次に動作について図2を用いて説明する。
このMMIC100は実装基板(図示せず)やパッケー
ジ(図示せず)等に取り付けられて、図2に示すよう
に、MMIC100の外部に設けられているアンテナ7
や、信号処理IC8等と接続され、送受信動作が行われ
るものであり、まず、受信動作時には、アンテナ7から
の入力波はSW3にて受信系へ切り替えられてLNA1
により増幅されてMMIC100の外部の信号処理IC
8に出力される。つまり、MMIC100外部のアンテ
ナ7から入力された約−40dBmの入力信号は、ポー
トP1からMMIC100に入力され、SW3によりポ
ートP1とポートP9とが接続されて、ポートP9から
出力された後、ポートP8からLNA1に入力されて−
30dBmに増幅され、ポートP7より出力されてMM
IC100外部に設けられた信号処理IC8にRF入力
信号として入力される。
Next, the operation will be described with reference to FIG.
The MMIC 100 is attached to a mounting board (not shown), a package (not shown), or the like, and as shown in FIG.
And a signal processing IC 8 or the like to perform a transmission / reception operation. First, at the time of a reception operation, an input wave from the antenna 7 is switched to a reception system by the SW 3 and the LNA 1
A signal processing IC external to the MMIC 100
8 is output. That is, an input signal of about −40 dBm input from the antenna 7 outside the MMIC 100 is input from the port P1 to the MMIC 100, the port P1 and the port P9 are connected by the SW3, and after being output from the port P9, the port P8 is output. Input to LNA1-
Amplified to 30 dBm, output from port P7, and
The signal is input to a signal processing IC 8 provided outside the IC 100 as an RF input signal.

【0023】また、送信動作時においては、SW3は送
信系に切り換えられ、MMICに入力された出力信号が
HPA5により増幅されてアンテナ7から送信される。
つまり、信号処理IC8から出力された約0dBmのR
F出力信号は、ポートP4からMMIC100に入力さ
れ、HPA5において約20dBmに増幅されてポート
P3から出力された後、ポートP2からSW3に入力さ
れ、ポートP1を経てアンテナ7から約20dBmの出
力信号が出力される。
In the transmission operation, SW3 is switched to the transmission system, and the output signal input to the MMIC is amplified by the HPA 5 and transmitted from the antenna 7.
That is, the R of about 0 dBm output from the signal processing IC 8
The F output signal is input from the port P4 to the MMIC 100, is amplified to about 20 dBm in the HPA 5, is output from the port P3, is input from the port P2 to the SW3, and outputs an output signal of about 20 dBm from the antenna 7 through the port P1. Is output.

【0024】このとき、制御回路2は、送受信のタイミ
ングを図りながらHPA5,LNA1,及びSW3への
バイアスの設定を行い、SW3の接続状態等を切り換え
て送受信の切り換えを行っている。この制御回路2に
は、MMIC100を含む装置の電源電圧,例えば3V
と、接地である0VがポートP5から印加されており、
この制御回路2の内部の論理振幅は約0/0.6Vとな
っている。また、負電圧発生回路4においては、ポート
P6から入力されるMMIC100の外部の発振器によ
り発生される約−10dBmのRF信号から、制御回路
2から出力されるHPA5,SW3へのバイアスのうち
の負電圧の基準電圧−1〜−2Vを発生させている。こ
のMMIC100においては、LNA1とHPA5とは
同時に動作することはないが、制御回路2および負電圧
発生回路4は常に動作している。
At this time, the control circuit 2 sets the bias to the HPAs 5, LNA1, and SW3 while taking the timing of transmission and reception, and switches the connection state of SW3 to switch between transmission and reception. The control circuit 2 has a power supply voltage of a device including the MMIC 100, for example, 3V.
And 0V which is ground is applied from the port P5,
The logical amplitude inside the control circuit 2 is about 0 / 0.6V. Also, in the negative voltage generation circuit 4, the negative of the bias to the HPAs 5 and SW 3 output from the control circuit 2 is obtained from the RF signal of about −10 dBm generated by the oscillator external to the MMIC 100 input from the port P 6. The reference voltages -1 to -2 V are generated. In the MMIC 100, the LNA 1 and the HPA 5 do not operate at the same time, but the control circuit 2 and the negative voltage generation circuit 4 always operate.

【0025】この実施の形態1に係るMMICにおいて
は、制御回路2及び負電源発生回路4と、その他のLN
A1,SW3,及びHPA5とに挟まれた領域のGaA
s基板10上には、接地された金属からなる接地金属膜
6が設けられているため、この接地金属膜6を挟んだ回
路間のアイソレーション量は、この接地金属膜6がない
場合の10dBmから40dBmに改善されるととも
に、この接地金属膜6を用いた場合のアイソレーション
は、この接地金属膜6の代わりに低抵抗な不純物拡散領
域を設けた場合のアイソレーションよりも優れている。
このため、負電圧発生回路4とその他の回路との間のR
F信号の漏れは、大きい場合でも−20dBm以下とな
り、負電源発生回路4の信号レベルである−10dBm
に比べて約1/10以下の問題のないレベルとなる。ま
た、同様に、信号レベルの小さい制御回路2もこの制御
回路2とHPA5との間に接地金属膜6が設けられてい
ることにより信号レベルの大きいHPA5の影響を受け
にくくなる。この結果、信号レベルの小さい制御回路2
や負電源発生回路4に他の信号レベルの大きい回路の信
号漏れの影響を与えないようにして、RF信号の漏れの
MMIC100の特性に与える影響を少なくすることが
できる。したがって、上述した従来のMMICにおいて
は、負電源発生回路4及び制御回路2とその他の回路と
の出力レベル差が大きいため、仮に、低抵抗n型領域等
の不純物を拡散して形成した領域を回路間に設けたとし
ても、負電源発生回路及び制御回路と、その他の回路と
の間でRF信号の漏れが発生し、その結果、MMICの
特性が劣化していたが、本発明においては、この出力レ
ベル差の大きい、負電源発生回路4及び制御回路2とそ
の他の回路との部分に接地金属膜6を設けたので、アイ
ソレーション量を大きくしてRF信号の漏れを防いで、
MMIC100の特性の劣化を抑えることができる。
In the MMIC according to the first embodiment, the control circuit 2, the negative power supply generation circuit 4, and the other LN
GaAs in the region sandwiched between A1, SW3 and HPA5
Since the ground metal film 6 made of a grounded metal is provided on the s-substrate 10, the amount of isolation between circuits sandwiching the ground metal film 6 is 10 dBm when the ground metal film 6 is not provided. To 40 dBm, and the isolation when the ground metal film 6 is used is superior to the isolation when a low-resistance impurity diffusion region is provided instead of the ground metal film 6.
For this reason, R between the negative voltage generation circuit 4 and other circuits
The leakage of the F signal is -20 dBm or less even in a large case, and the signal level of the negative power supply generation circuit 4 is -10 dBm.
This is about 1/10 or less of the problem-free level. Similarly, since the ground metal film 6 is provided between the control circuit 2 and the HPA 5, the control circuit 2 having a low signal level is also less likely to be affected by the HPA 5 having a high signal level. As a result, the control circuit 2 having a small signal level
And the negative power supply generating circuit 4 is not affected by signal leakage of other circuits having a large signal level, so that the effect of RF signal leakage on the characteristics of the MMIC 100 can be reduced. Therefore, in the above-described conventional MMIC, since the output level difference between the negative power supply generation circuit 4 and the control circuit 2 and other circuits is large, a region formed by diffusing impurities such as a low-resistance n-type region may be used. Even if provided between the circuits, leakage of the RF signal occurred between the negative power supply generation circuit and the control circuit, and other circuits, and as a result, the characteristics of the MMIC were deteriorated. Since the ground metal film 6 is provided in the portion of the negative power supply generation circuit 4 and the control circuit 2 and other circuits where the output level difference is large, the isolation amount is increased to prevent leakage of the RF signal.
Deterioration of the characteristics of the MMIC 100 can be suppressed.

【0026】また、この接地金属膜6の材料として、上
記各回路内の金属配線と同じ材料の金属を用いるように
すれば、接地金属膜6を上記各回路内の金属配線と同時
に形成できるため、通常のMMICの製造工程と比較し
て製造工程を増加させることなく、容易に回路間のRF
信号の漏れを防ぐことができる。
If the same metal as the metal wiring in each circuit is used as the material of the ground metal film 6, the ground metal film 6 can be formed simultaneously with the metal wiring in each circuit. The RF between the circuits can be easily increased without increasing the number of manufacturing steps as compared with a normal MMIC manufacturing step.
Signal leakage can be prevented.

【0027】このようにこの実施の形態1によれば、制
御回路2及び負電圧発生回路4と、LNA1及びSW3
とに挟まれた領域、並びに、制御回路2及び負電圧発生
回路4と、HPA5とに挟まれた領域のGaAs基板1
0上に接地金属膜6を配置したから、この接地金属膜6
を接地電位とすることができ、出力レベル差の大きい負
電源発生回路4及び制御回路2とその他の回路との間の
アイソレーション量を、負電源発生回路4及び制御回路
2とその他の回路との間に低抵抗な不純物拡散領域を設
けた場合に対しても十分に大きくでき、RF信号の漏れ
を防いで、MMICの特性の劣化を抑えることができ
る。
As described above, according to the first embodiment, the control circuit 2 and the negative voltage generation circuit 4, the LNA 1 and the SW3
And the GaAs substrate 1 in a region sandwiched between the control circuit 2 and the negative voltage generation circuit 4 and the HPA 5
0, the ground metal film 6 is disposed on the ground metal film 6.
Can be set to the ground potential, and the amount of isolation between the negative power generation circuit 4 and the control circuit 2 and other circuits having a large output level difference is different from that of the negative power generation circuit 4 and the control circuit 2 and other circuits. This can be made sufficiently large even when a low-resistance impurity diffusion region is provided between them, thereby preventing leakage of an RF signal and suppressing deterioration of MMIC characteristics.

【0028】なお、上記実施の形態1においては、負電
源発生回路4及び制御回路2とその他の回路との間に接
地金属膜を設けた場合について説明したが、本発明はそ
の他の回路間の領域上に接地金属膜を設けた場合におい
ても適用できるものであり、このような場合において
も、回路間のアイソレーションを向上させることがで
き、上記実施の形態1と同様の効果を奏する。
In the first embodiment, the case where the ground metal film is provided between the negative power supply generating circuit 4 and the control circuit 2 and the other circuits has been described. The present invention can be applied to the case where the ground metal film is provided on the region. In such a case, the isolation between circuits can be improved, and the same effect as that of the first embodiment can be obtained.

【0029】実施の形態2.図3は本発明の実施の形態
2に係るMMICの構造を模式的に示す平面図であり、
図において、図1,図2と同一符号は同一又は相当する
部分を示しており、101はMMICである。
Embodiment 2 FIG. 3 is a plan view schematically showing the structure of the MMIC according to the second embodiment of the present invention.
In the figure, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding parts, and 101 is an MMIC.

【0030】この実施の形態2に係るMMICは、負電
圧発生回路4、制御回路2、SW3、LNA1、及びH
PA5からなるMMICにおいて、制御回路2及び負電
圧発生回路4を基板10の一端側に配置し、上記HPA
5及びSW3を、基板10の制御回路2及び負電圧発生
回路4が配置されている一端側に対して反対側の端部に
配置するとともに、負電圧発生回路4及び制御回路2の
ポートP5,P6と、HPA5及びSW3のポートP1
〜P4,P9を、基板10の端部側の、ポートP5,P
6と、ポートP1〜P4,P9との距離が最も離れる位
置に配置するようにしたものである。
The MMIC according to the second embodiment includes a negative voltage generation circuit 4, a control circuit 2, SW3, LNA1, and H
In the MMIC composed of the PA5, the control circuit 2 and the negative voltage generation circuit 4 are arranged at one end of the substrate 10, and the HPA
5 and SW3 are arranged at an end opposite to the one end on which the control circuit 2 and the negative voltage generation circuit 4 are arranged on the substrate 10, and the ports P5 and N5 of the negative voltage generation circuit 4 and the control circuit 2 are arranged. P6 and port P1 of HPA5 and SW3
To P4, P9 are connected to ports P5, P
6 and the ports P1 to P4, P9 are arranged at the position where the distance is the longest.

【0031】このMMICにおいては、負電圧発生回路
4及び制御回路2の入出力ポートとSW3やHPA5の
入出力ポートとを、互いに離して配置しているため、S
W3やHPA5からのRF信号の漏れは、送信時には動
作しないLNA1とHPA5内部の入力回路部とに阻止
される形となるため、上述した従来のMMICと比較し
て、送信時のアイソレーション量を増加させることがで
き、これにより、新たにアイソレーションのための部材
等を設けることなく、容易にMMICの特性の劣化を抑
えることができる効果を奏する。
In this MMIC, the input / output ports of the negative voltage generation circuit 4 and the control circuit 2 and the input / output ports of the SW3 and HPA5 are arranged apart from each other.
Leakage of RF signals from W3 and HPA5 is prevented by LNA1 which does not operate during transmission and the input circuit inside HPA5. Therefore, compared to the above-described conventional MMIC, the amount of isolation during transmission is reduced. This can provide an effect that deterioration of the characteristics of the MMIC can be easily suppressed without newly providing a member or the like for isolation.

【0032】実施の形態3.図4は本発明の実施の形態
3に係るMMICの構造を模式的に示す平面図であり、
図において、図1,2と同一符号は同一または相当する
部分を示しており、102はMMICである。
Embodiment 3 FIG. FIG. 4 is a plan view schematically showing the structure of the MMIC according to the third embodiment of the present invention.
In the figure, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding parts, and reference numeral 102 denotes an MMIC.

【0033】この実施の形態3に係るMMICは、上記
実施の形態2に係るMMICにおいて、基板10上の制
御回路2及び負電圧発生回路4と、LNA1,SW3,
及びHPA5とに挟まれた領域上に、上記実施の形態1
において説明した接地金属膜6を配置するようにしたも
のであり、これにより、上記実施の形態2と同様の効果
を奏するとともに、接地金属膜6によりアイソレーショ
ン量を確保してLNA1,SW3,及びHPA5からの
RF信号の漏れを減らすことができ、MMICの特性の
劣化を抑えることができる効果を奏する。
The MMIC according to the third embodiment is different from the MMIC according to the second embodiment in that the control circuit 2 and the negative voltage generation circuit 4 on the substrate 10 are connected to the LNA1, SW3,
Embodiment 1 on the region sandwiched between the first embodiment and HPA5
In this configuration, the ground metal film 6 described in the above is arranged, thereby providing the same effect as in the second embodiment, and securing the isolation amount by the ground metal film 6 to make the LNA1, SW3, and This has the effect of reducing the leakage of the RF signal from the HPA 5 and suppressing the deterioration of the characteristics of the MMIC.

【0034】なお、上記実施の形態1〜3においてはM
MICについて説明したが、本発明はその他の高周波を
扱う半導体基板上に複数の回路を備えた半導体装置にお
いても適用できるものであり、このような場合において
も上記実施の形態1〜3と同様の効果を奏する。
In the first to third embodiments, M
Although the MIC has been described, the present invention can also be applied to a semiconductor device having a plurality of circuits on a semiconductor substrate that handles other high frequencies. In such a case, the same as in the first to third embodiments described above. It works.

【0035】[0035]

【発明の効果】以上のようにこの発明によれば、半導体
基板と、該半導体基板上に互いに所定の間隔を隔てて設
けられた複数の回路と、上記半導体基板上の、上記複数
の回路に挟まれた領域上に設けられた接地金属膜とを備
えるようにしたから、接地金属膜を介して対向する回路
間のアイソレーション量を大きくでき、RF信号の漏れ
を防いで、特性の劣化を抑えることができる効果が得ら
れる。
As described above, according to the present invention, a semiconductor substrate, a plurality of circuits provided on the semiconductor substrate at predetermined intervals, and a plurality of circuits on the semiconductor substrate are provided. With the ground metal film provided on the sandwiched area, the amount of isolation between opposing circuits via the ground metal film can be increased, preventing RF signal leakage and deteriorating characteristics. An effect that can be suppressed can be obtained.

【0036】また、この発明によれば、複数の回路は、
信号レベルの異なる複数の回路からなり、接地金属膜
は、上記複数の回路のうちの他の回路に対する信号レベ
ル差が大きい一つ以上の回路と、上記他の回路との間に
設けられているようにしたから、接地金属膜を介して対
向する信号レベル差の大きい回路間のアイソレーション
量を大きくでき、RF信号の漏れを防いで、特性の劣化
を抑えることができる効果が得られる。
According to the present invention, the plurality of circuits include:
The ground metal film includes a plurality of circuits having different signal levels, and the ground metal film is provided between one or more circuits having a large signal level difference with respect to another circuit of the plurality of circuits and the other circuit. With this configuration, the amount of isolation between the circuits having a large signal level difference via the ground metal film can be increased, and the effect of preventing the leakage of the RF signal and suppressing the deterioration of the characteristics can be obtained.

【0037】また、この発明によれば、複数の回路は、
負電圧発生回路、制御回路、スイッチ、低雑音増幅器、
及び高出力増幅器からなり、上記負電圧発生回路及び制
御回路は互いに隣接して配置されており、接地金属膜
は、上記半導体基板上の上記負電圧発生回路及び制御回
路と、他の回路とに挟まれた領域上に設けられているよ
うにしたから、信号レベル差の大きい負電圧発生回路及
び制御回路と、他の回路との間のアイソレーション量を
大きくでき、RF信号の漏れを防いで、特性の劣化を抑
えることができる効果が得られる。
According to the present invention, the plurality of circuits include:
Negative voltage generation circuit, control circuit, switch, low noise amplifier,
The negative voltage generating circuit and the control circuit are disposed adjacent to each other, and the ground metal film is connected to the negative voltage generating circuit and the control circuit on the semiconductor substrate, and to other circuits. Since it is provided on the sandwiched region, the amount of isolation between the negative voltage generation circuit and the control circuit having a large signal level difference and other circuits can be increased, and leakage of the RF signal can be prevented. The effect of suppressing the deterioration of the characteristics can be obtained.

【0038】また、この発明によれば、負電圧発生回路
を−10dBm以上−8dBm以下の入力信号レベルで
動作するものとし、制御回路を0Vと3Vの基準電圧で
動作するものとし、低雑音増幅器を−60dBm以上−
30dBm以下の出力信号レベルで動作するものとし、
高出力増幅器は20dBm以上22dBm以下の出力信
号レベルで動作するものとしたから、信号レベル差の大
きい負電圧発生回路及び制御回路と、他の回路との間の
アイソレーション量を大きくでき、RF信号の漏れを防
いで、特性の劣化を抑えることができる効果が得られ
る。
According to the invention, the negative voltage generating circuit operates at an input signal level of -10 dBm or more and -8 dBm or less, the control circuit operates at a reference voltage of 0 V or 3 V, and a low noise amplifier is provided. Is −60 dBm or more−
It operates at an output signal level of 30 dBm or less,
Since the high-output amplifier operates at an output signal level of 20 dBm or more and 22 dBm or less, the amount of isolation between the negative voltage generating circuit and the control circuit having a large signal level difference and other circuits can be increased, and the RF signal can be increased. Is obtained, and the effect of suppressing the deterioration of characteristics can be obtained.

【0039】また、この発明によれば、接地金属膜は、
複数の回路のいずれかに設けられた金属配線と同じ材料
からなるようにしたから、接地金属膜を回路の金属配線
と同時に形成することができ、新たな製造工程を加える
ことなく、容易に接地金属膜を介して対向する回路間の
アイソレーション量を大きくできる効果が得られる。
Further, according to the present invention, the ground metal film is
Since it is made of the same material as the metal wiring provided in any of the plurality of circuits, the ground metal film can be formed simultaneously with the metal wiring of the circuit, and the ground can be easily grounded without adding a new manufacturing process. The effect of increasing the isolation amount between the circuits facing each other via the metal film can be obtained.

【0040】また、この発明によれば、半導体基板と、
該半導体基板上に互いに所定の間隔を隔てて配置された
負電圧発生回路、制御回路、スイッチ、低雑音増幅器、
及び高出力増幅器とからなり、上記負電圧発生回路及び
制御回路は、互いに隣接して上記基板の一端側に配置さ
れており、上記高出力増幅器及びスイッチは、互いに隣
接して上記基板の一端に対して反対側の端部側に配置さ
れており、上記負電圧発生回路及び制御回路の入力端子
及び出力端子は、上記基板の一端側に配置され、上記高
出力増幅器及びスイッチの入力端子及び出力端子は、上
記基板の一端に対して反対側の端部側に配置されている
ようにしたから、高出力増幅器及びスイッチと、負電圧
発生回路及び制御回路との間のアイソレーション量を大
きくでき、RF信号の漏れを防いで、特性の劣化を抑え
ることができる効果が得られる。
Further, according to the present invention, a semiconductor substrate;
A negative voltage generating circuit, a control circuit, a switch, a low noise amplifier, which are arranged on the semiconductor substrate at a predetermined interval from each other;
And the high-power amplifier, wherein the negative voltage generating circuit and the control circuit are disposed adjacent to each other on one end of the substrate, and the high-output amplifier and the switch are adjacent to each other and provided at one end of the substrate. The input terminal and the output terminal of the negative voltage generation circuit and the control circuit are disposed on one end side of the substrate, and the input terminal and the output terminal of the high power amplifier and the switch are arranged on the opposite end. Since the terminals are arranged on the end opposite to one end of the substrate, the amount of isolation between the high-power amplifier and the switch, the negative voltage generating circuit and the control circuit can be increased. Thus, the effect of preventing the leakage of the RF signal and suppressing the deterioration of the characteristics can be obtained.

【0041】また、この発明によれば、半導体基板上
の、負電圧発生回路及び制御回路と高出力増幅器及びス
イッチとに挟まれた領域上に、接地金属膜を備えるよう
にしたから、高出力増幅器及びスイッチと、負電圧発生
回路及び制御回路との間のアイソレーション量をさらに
大きくでき、RF信号の漏れを防いで、特性の劣化を確
実に抑えることができる効果がある。
According to the present invention, the ground metal film is provided on the region between the negative voltage generating circuit and the control circuit, the high output amplifier and the switch on the semiconductor substrate. The amount of isolation between the amplifier and the switch and the negative voltage generation circuit and the control circuit can be further increased, thereby preventing leakage of an RF signal and reliably suppressing deterioration of characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施の形態1に係る半導体装置の構
造を示す平面図である。
FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

【図2】 本発明の実施の形態1に係る半導体装置の信
号の流れを示すブロック図である。
FIG. 2 is a block diagram illustrating a signal flow of the semiconductor device according to the first embodiment of the present invention;

【図3】 本発明の実施の形態2に係る半導体装置の構
造を示す平面図である。
FIG. 3 is a plan view showing a structure of a semiconductor device according to a second embodiment of the present invention.

【図4】 本発明の実施の形態3に係る半導体装置の構
造を示す平面図である。
FIG. 4 is a plan view showing a structure of a semiconductor device according to a third embodiment of the present invention.

【図5】 従来例の半導体装置の構造を示す平面図であ
る。
FIG. 5 is a plan view showing the structure of a conventional semiconductor device.

【図6】 従来例の半導体装置の信号の流れを示すブロ
ック図である。
FIG. 6 is a block diagram showing a signal flow of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 LNA、2 制御回路、3 SW、4 負電圧発生
回路、5 HPA,接地金属膜、7 アンテナ、8 信
号処理IC 10 GaAs基板、50,100〜10
2 MMIC。
Reference Signs List 1 LNA, 2 control circuit, 3 SW, 4 negative voltage generating circuit, 5 HPA, ground metal film, 7 antenna, 8 signal processing IC 10 GaAs substrate, 50, 100 to 10
2 MMIC.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板と、 該半導体基板上に互いに所定の間隔を隔てて設けられた
複数の回路と、 上記半導体基板上の、上記複数の回路に挟まれた領域上
に設けられた接地金属膜とを備えたことを特徴とする半
導体装置。
A semiconductor substrate; a plurality of circuits provided on the semiconductor substrate at predetermined intervals; and a ground provided on a region of the semiconductor substrate sandwiched between the plurality of circuits. A semiconductor device comprising a metal film.
【請求項2】 請求項1に記載の半導体装置において、 複数の回路は、信号レベルの異なる複数の回路からな
り、 接地金属膜は、上記複数の回路のうちの他の回路に対す
る信号レベル差が大きい一つ以上の回路と、上記他の回
路との間に設けられていることを特徴とする半導体装
置。
2. The semiconductor device according to claim 1, wherein the plurality of circuits include a plurality of circuits having different signal levels, and the ground metal film has a signal level difference with respect to another of the plurality of circuits. A semiconductor device provided between one or more large circuits and the other circuit.
【請求項3】 請求項1に記載の半導体装置において、 複数の回路は、負電圧発生回路、制御回路、スイッチ、
低雑音増幅器、及び高出力増幅器からなり、 上記負電圧発生回路及び制御回路は互いに隣接して配置
されており、 接地金属膜は、半導体基板上の上記負電圧発生回路及び
制御回路と、他の回路とに挟まれた領域上に設けられて
いることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the plurality of circuits include a negative voltage generation circuit, a control circuit, a switch,
A low-noise amplifier and a high-output amplifier, wherein the negative voltage generating circuit and the control circuit are arranged adjacent to each other, and a ground metal film is formed on the semiconductor substrate by the negative voltage generating circuit and the control circuit. A semiconductor device provided over a region sandwiched between circuits.
【請求項4】 請求項3に記載の半導体装置において、 負電圧発生回路は−10dBm以上−8dBm以下の入
力信号レベルで動作するものであり、 制御回路は0Vと3Vの基準電圧で動作するものであ
り、 低雑音増幅器は−60dBm以上−30dBm以下の出
力信号レベルで動作するものであり、 高出力増幅器は20dBm以上22dBm以下の出力信
号レベルで動作するものであることを特徴とする半導体
装置。
4. The semiconductor device according to claim 3, wherein the negative voltage generating circuit operates at an input signal level of -10 dBm or more and -8 dBm or less, and the control circuit operates at a reference voltage of 0 V and 3 V. Wherein the low-noise amplifier operates at an output signal level of -60 dBm or more and -30 dBm or less, and the high-output amplifier operates at an output signal level of 20 dBm or more and 22 dBm or less.
【請求項5】 請求項1に記載の半導体装置において、 接地金属膜は、複数の回路のいずれかに設けられた金属
配線と同じ材料からなることを特徴とする半導体装置。
5. The semiconductor device according to claim 1, wherein the ground metal film is made of the same material as a metal wiring provided in any of the plurality of circuits.
【請求項6】 半導体基板と、 該半導体基板上に互いに所定の間隔を隔てて配置された
負電圧発生回路、制御回路、スイッチ、低雑音増幅器、
及び高出力増幅器とからなり、 上記負電圧発生回路及び制御回路は、互いに隣接して上
記基板の一端側に配置されており、 上記高出力増幅器及びスイッチは、互いに隣接して上記
基板の一端に対して反対側の端部側に配置されており、 上記負電圧発生回路及び制御回路の入力端子及び出力端
子は、上記基板の一端側に配置され、 上記高出力増幅器及びスイッチの入力端子及び出力端子
は、上記基板の一端に対して反対側の端部側に配置され
ていることを特徴とする半導体装置。
6. A semiconductor substrate, and a negative voltage generating circuit, a control circuit, a switch, a low noise amplifier, which are arranged on the semiconductor substrate at a predetermined interval from each other.
And the high-power amplifier, wherein the negative voltage generation circuit and the control circuit are disposed adjacent to each other on one end side of the substrate, and the high-output amplifier and the switch are adjacent to each other and provided at one end of the substrate. The input terminal and the output terminal of the negative voltage generation circuit and the control circuit are disposed on one end side of the substrate, and the input terminal and the output of the high power amplifier and the switch are disposed on the opposite end side. The semiconductor device, wherein the terminal is arranged on an end opposite to one end of the substrate.
【請求項7】 請求項6に記載の半導体装置において、 半導体基板上の、負電圧発生回路及び制御回路と高出力
増幅器及びスイッチとに挟まれた領域上に、接地金属膜
を備えたことを特徴とする半導体装置。
7. The semiconductor device according to claim 6, wherein a ground metal film is provided on an area between the negative voltage generation circuit and the control circuit, the high-power amplifier, and the switch on the semiconductor substrate. Characteristic semiconductor device.
JP8233845A 1996-09-04 1996-09-04 Semiconductor device Pending JPH1079467A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8233845A JPH1079467A (en) 1996-09-04 1996-09-04 Semiconductor device
KR1019970002274A KR19980023927A (en) 1996-09-04 1997-01-27 Semiconductor devices
DE19721448A DE19721448A1 (en) 1996-09-04 1997-05-22 Semiconductor module, e.g. MMIC gallium arsenide integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8233845A JPH1079467A (en) 1996-09-04 1996-09-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1079467A true JPH1079467A (en) 1998-03-24

Family

ID=16961477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8233845A Pending JPH1079467A (en) 1996-09-04 1996-09-04 Semiconductor device

Country Status (3)

Country Link
JP (1) JPH1079467A (en)
KR (1) KR19980023927A (en)
DE (1) DE19721448A1 (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8954902B2 (en) 2005-07-11 2015-02-10 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9024700B2 (en) 2008-02-28 2015-05-05 Peregrine Semiconductor Corporation Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device
US9087899B2 (en) 2005-07-11 2015-07-21 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US9130564B2 (en) 2005-07-11 2015-09-08 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US9177737B2 (en) 2007-04-26 2015-11-03 Peregrine Semiconductor Corporation Tuning capacitance to enhance FET stack voltage withstand
US9225378B2 (en) 2001-10-10 2015-12-29 Peregrine Semiconductor Corpopration Switch circuit and method of switching radio frequency signals
US9369087B2 (en) 2004-06-23 2016-06-14 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9419565B2 (en) 2013-03-14 2016-08-16 Peregrine Semiconductor Corporation Hot carrier injection compensation
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
JP2019033366A (en) * 2017-08-08 2019-02-28 日本電信電話株式会社 Radio transmitter, radio receiver and radio communication system
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
KR20190040041A (en) 2016-12-14 2019-04-16 가부시키가이샤 무라타 세이사쿠쇼 Switch IC, front-end module and communication device
JP2019145675A (en) * 2018-02-21 2019-08-29 新日本無線株式会社 High frequency semiconductor integrated circuit
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
KR20200018624A (en) 2017-09-29 2020-02-19 가부시키가이샤 무라타 세이사쿠쇼 Semiconductor devices, high frequency circuits, and communication devices
US10790390B2 (en) 2005-07-11 2020-09-29 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US10804892B2 (en) 2005-07-11 2020-10-13 Psemi Corporation Circuit and method for controlling charge injection in radio frequency switches
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9225378B2 (en) 2001-10-10 2015-12-29 Peregrine Semiconductor Corpopration Switch circuit and method of switching radio frequency signals
US10790820B2 (en) 2001-10-10 2020-09-29 Psemi Corporation Switch circuit and method of switching radio frequency signals
US10797694B2 (en) 2001-10-10 2020-10-06 Psemi Corporation Switch circuit and method of switching radio frequency signals
US10812068B2 (en) 2001-10-10 2020-10-20 Psemi Corporation Switch circuit and method of switching radio frequency signals
US10622993B2 (en) 2001-10-10 2020-04-14 Psemi Corporation Switch circuit and method of switching radio frequency signals
US9680416B2 (en) 2004-06-23 2017-06-13 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US9369087B2 (en) 2004-06-23 2016-06-14 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
USRE48944E1 (en) 2005-07-11 2022-02-22 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETS using an accumulated charge sink
US9130564B2 (en) 2005-07-11 2015-09-08 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US10797691B1 (en) 2005-07-11 2020-10-06 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US8954902B2 (en) 2005-07-11 2015-02-10 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10622990B2 (en) 2005-07-11 2020-04-14 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US9608619B2 (en) 2005-07-11 2017-03-28 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10790390B2 (en) 2005-07-11 2020-09-29 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US10797172B2 (en) 2005-07-11 2020-10-06 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US9087899B2 (en) 2005-07-11 2015-07-21 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US10818796B2 (en) 2005-07-11 2020-10-27 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10680600B2 (en) 2005-07-11 2020-06-09 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US10804892B2 (en) 2005-07-11 2020-10-13 Psemi Corporation Circuit and method for controlling charge injection in radio frequency switches
US10951210B2 (en) 2007-04-26 2021-03-16 Psemi Corporation Tuning capacitance to enhance FET stack voltage withstand
US9177737B2 (en) 2007-04-26 2015-11-03 Peregrine Semiconductor Corporation Tuning capacitance to enhance FET stack voltage withstand
US9197194B2 (en) 2008-02-28 2015-11-24 Peregrine Semiconductor Corporation Methods and apparatuses for use in tuning reactance in a circuit device
US9293262B2 (en) 2008-02-28 2016-03-22 Peregrine Semiconductor Corporation Digitally tuned capacitors with tapered and reconfigurable quality factors
US9106227B2 (en) 2008-02-28 2015-08-11 Peregrine Semiconductor Corporation Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
US9024700B2 (en) 2008-02-28 2015-05-05 Peregrine Semiconductor Corporation Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US9419565B2 (en) 2013-03-14 2016-08-16 Peregrine Semiconductor Corporation Hot carrier injection compensation
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
KR20190040041A (en) 2016-12-14 2019-04-16 가부시키가이샤 무라타 세이사쿠쇼 Switch IC, front-end module and communication device
US11270961B2 (en) 2016-12-14 2022-03-08 Murata Manufacturing Co., Ltd. Switch IC, front-end module, and communication apparatus
JP2019033366A (en) * 2017-08-08 2019-02-28 日本電信電話株式会社 Radio transmitter, radio receiver and radio communication system
US11121733B2 (en) 2017-09-29 2021-09-14 Murata Manufacturing Co., Ltd. Semiconductor device, radio-frequency circuit, and communication apparatus
KR20200018624A (en) 2017-09-29 2020-02-19 가부시키가이샤 무라타 세이사쿠쇼 Semiconductor devices, high frequency circuits, and communication devices
JP2019145675A (en) * 2018-02-21 2019-08-29 新日本無線株式会社 High frequency semiconductor integrated circuit
US11018662B2 (en) 2018-03-28 2021-05-25 Psemi Corporation AC coupling modules for bias ladders
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US10862473B2 (en) 2018-03-28 2020-12-08 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US11418183B2 (en) 2018-03-28 2022-08-16 Psemi Corporation AC coupling modules for bias ladders
US11870431B2 (en) 2018-03-28 2024-01-09 Psemi Corporation AC coupling modules for bias ladders
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch
US12081211B2 (en) 2020-01-06 2024-09-03 Psemi Corporation High power positive logic switch

Also Published As

Publication number Publication date
DE19721448A1 (en) 1998-03-12
KR19980023927A (en) 1998-07-06

Similar Documents

Publication Publication Date Title
JPH1079467A (en) Semiconductor device
US7995972B2 (en) Electronic component for communication device and semiconductor device for switching transmission and reception
US5878331A (en) Integrated circuit
JP4037029B2 (en) Semiconductor integrated circuit device
US5973377A (en) Semiconductor device having FETs with shared source and drain regions
EP1351379B1 (en) High-frequency semiconductor device
US7221228B2 (en) Radio frequency power amplifier module
JPH09121173A (en) Semiconductor device containing power amplifier
JP2580966B2 (en) Semiconductor device
US7821031B2 (en) Switch circuit, semiconductor device, and method of manufacturing said semiconductor device
EP0552701A2 (en) Package for microwave device
JP4005846B2 (en) High frequency switch device
JP3702189B2 (en) Compound semiconductor switch circuit device
US6448616B1 (en) Adaptive biasing of RF power transistors
JPH09186533A (en) Transmitter
JPH06120414A (en) Microwave integrated circuit element
JP2005244850A (en) High frequency switch apparatus
US5852316A (en) Complementary heterojunction amplifier
JP2002261593A (en) Compound semiconductor switching circuit
JPH09139630A (en) Portable communication equipment and power amplifier in portable communication equipment
JPH10224158A (en) High-frequency circuit
JPH11354709A (en) Semiconductor device and amplifier
JP2006033539A (en) High-frequency signal switching circuit
JP2002313817A (en) Compound semiconductor device
JPH10178305A (en) High frequency circuit

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20040106