JP2002261593A - Compound semiconductor switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of preventing a printed board from increasing in mounting area because a control terminal is provided for each FET for making it carry out switching operations, in a conventional semiconductor switching circuit. SOLUTION: A compound semiconductor switching circuit is equipped with a first and a second FET, a common input terminal connected to the source electrodes or drain electrodes of the FETs, a first and a second output terminal connected to the drain electrodes or the source electrodes of the FETs, a biasing means for applying a prescribed bias to the first output terminal of the first FET, a connecting means for connecting the control terminal to the second output terminal, a grounding means for grounding the gate electrode of the second FET, and an isolating means for isolating the common input terminal from the source electrode or drain electrode of the second FET in terms of a direct current; and the connecting means is extended along pads, and control signals are applied to the control terminal connected to the gate electrode of the first FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor switch circuit device used for high-frequency switching, and more particularly to a compound semiconductor switch circuit device having one control terminal.

[0002]

2. Description of the Related Art In mobile communication devices such as cellular phones, G
In many cases, microwaves in the Hz band are used, and switch elements for switching these high-frequency signals are often used in antenna switching circuits and transmission / reception switching circuits (for example, Japanese Patent Application Laid-Open No. Hei 9-181624). issue). As the element, a high-frequency field-effect transistor (hereinafter, FE) using gallium arsenide (GaAs) is used.
In many cases, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated has been developed.

FIG. 7A is a sectional view of a GaAs MESFET. An N-type channel region 2 is formed by doping the surface of a non-doped GaAs substrate 1 with an N-type impurity.
Is formed, and a gate electrode 3 which is in Schottky contact with the surface of the channel region 2 is arranged.
a source / drain electrode 4 in ohmic contact with the s surface,
5 are arranged. In this transistor, a depletion layer is formed in the channel region 2 immediately below by the potential of the gate electrode 3, thereby controlling a channel current between the source electrode 4 and the drain electrode 5.

FIG. 7 (B) shows a principle circuit diagram of a compound semiconductor switch circuit device called a SPDT (Single Pole Double Throw) using a GaAs FET.

The sources (or drains) of the first and second FETs 1 and 2 are connected to a common input terminal IN, and each F
The gates of ET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2,
The drain (or source) of each FET is the first and second
Are connected to the output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which the H-level signal is applied turns ON, and the signal applied to the input terminal IN The signal is transmitted to one of the output terminals. The resistances R1 and R2 are connected to a control terminal Ctl which is AC grounded.
-1 and Ctl-2 are arranged for the purpose of preventing a high-frequency signal from leaking through the gate electrode with respect to the DC potential.

FIG. 8 shows an example of a compound semiconductor chip in which the compound semiconductor switch circuit device shown in FIG. 7B is integrated.

[0007] FET1 and FET2 for switching on a GaAs substrate are arranged at the center, and resistors R1 and R2 are connected to the gate electrodes of each FET. Further, the common input terminal IN, the output terminals OUT1, OUT2, the control terminal Ctl-
1, pads corresponding to Ctl-2 are provided around the substrate. The wiring of the second layer indicated by the dotted line is
The gate metal layer (Ti / Pt / Au) 20 formed simultaneously with the formation of the T gate electrode is shown. The third layer wiring shown by the solid line is a pad metal layer (Ti) for connecting each element and forming a pad. / Pt / Au) 30. An ohmic metal layer (AuG) in ohmic contact with the first layer substrate
e / Ni / Au) 10 forms a source electrode, a drain electrode of each FET, and extraction electrodes at both ends of each resistor, and is not shown in FIG. 8 because it overlaps with the pad metal layer.

FIG. 9A is an enlarged plan view of a portion of the FET 1 shown in FIG. In this figure, a rectangular region surrounded by a chain line is a channel region 12 formed on the substrate 11. A third comb-shaped pad metal layer 30 extending from the left side is the source electrode 13 (or drain electrode) connected to the output terminal OUT1, and is formed below the first ohmic metal layer 10. Source electrode 14
(Or drain electrode). The third comb-shaped pad metal layer 30 extending from the right side is a common input terminal I.
A drain electrode 15 (or a source electrode) connected to the first N-type ohmic metal layer 10
Drain electrode 16 (or source electrode) formed of
There is. These electrodes are arranged in a comb-toothed shape, and a gate electrode 17 formed of the second-layer gate metal layer 20 is arranged in a comb-like shape on the channel region 12 between them.

FIG. 9B is a sectional view of a part of the FET. A substrate 11 has an n-type channel region 12 and source and drain regions 18 and 19 formed on both sides thereof.
A + type high concentration region is provided, a gate electrode 17 is provided in the channel region 12, and a drain electrode 14 and a source electrode 16 formed of the first ohmic metal layer 10 are provided in the high concentration region. . Further, as described above, the drain electrode 13 and the source electrode 15 formed by the third-layer pad metal layer 30 are provided thereon, and wiring and the like of each element are performed.

[0010]

In the above-described compound semiconductor switch circuit device, the gates of the FETs 1 and 2 are connected to the first and second control terminals Ctl via the resistors R1 and R2.
-1 and Ctl-2, the two control signals, which are complementary signals, are transmitted to the first and second control terminals Ctl-1 and Ctl-1.
It must be applied to tl-2. Therefore, in an integrated circuit incorporating a compound semiconductor switch circuit device, two
External leads for the first and second control terminals Ctl-1 and Ctl-2 are required, which is a factor that hinders the miniaturization of the integrated circuit in a package. In order to avoid this, there is a method of realizing a single control terminal by incorporating an inverter circuit. However, an extra FET constituting the inverter circuit is required, and there are problems such as an increase in power consumption and an increase in package size.

Each of FET1 and FET2 is made of GaAs.
Since the MESFET is used, the switching operation is performed by applying a voltage to the gate electrode and controlling the opening and closing of the channel depletion layer. Usually, a GaAs MESFET is a depletion-type FET, and thus requires a negative voltage as a control voltage. Therefore, the compound semiconductor switch circuit device described above has a problem that a separate negative voltage generating circuit is required in order to operate at a negative voltage.

Further, when one control terminal is realized, there is a possibility that an intersecting wiring is generated and the chip area is increased.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various circumstances, and realizes one control terminal without using an inverter circuit.

That is, a source electrode is provided on the surface of the channel layer,
First and second provided with a gate electrode and a drain electrode
A common input terminal connected to the source electrode or the drain electrode of the two FETs, a first and a second output terminal connected to the drain electrode or the source electrode of the two FETs, and the first FET Biasing means for applying a predetermined bias to the first output terminal, connection means for connecting a control terminal to the second output terminal, grounding means for grounding the gate electrode of the second FET, A separating means for separating a common input terminal and a source electrode or a drain electrode of the second FET from each other in a direct current manner, wherein the connecting means extends along a pad;
A control signal is applied to the control terminal connected to the gate electrode of the FET.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a compound semiconductor switch circuit device according to the present invention. A first FE having a source electrode, a gate electrode and a drain electrode provided on a surface of a channel layer;
T1 and the second FET 2, a common input terminal IN connected to the source electrodes (or drain electrodes) of both FETs 1 and 2, and a first output connected to the drain electrodes (or source electrodes) of both FETs 1 and 2. A terminal OUT1 and a second output terminal OUT2, bias means for applying a predetermined bias to the first output terminal OUT1 of the first FET 1, connection means for connecting the control terminal and the second output terminal OUT2, Grounding means for grounding the gate electrode of the second FET 2, separation means for separating the common input terminal IN from the source electrode (or drain electrode) of the second FET 2 in a DC manner, and only the gate electrode of the first FET 1. And a control terminal Ctl-1 for applying a control signal.

The first FET 1 and the second FET 2 have G
It is composed of an aAs MESFET (depletion type FET) and is integrated on a GaAs substrate (see FIG. 5). Note that the first FET 1 and the second FET 2 are shown in FIG.
The structure is the same as that shown in FIG.

The bias means is one of the features of the present invention, and is a means for constantly applying a constant positive DC voltage, for example, 3 V, to the first output terminal OUT1 via the resistor R.

The grounding means is also one of the features of the present invention, and is a means for grounding the gate electrode of the second FET 2 with a resistor R. The gate electrode of the second FET 2 is always fixed to the ground potential. .

The connection means is also one of the features of the present invention, and is a means for connecting the control terminal Ctl-1 and the second output terminal OUT2 with a resistor R.

The separating means is also one of the features of the present invention, and includes a common input terminal IN and a source electrode of the second FET 2.
(Or a drain electrode) is formed by a capacitor C that separates the direct current. The capacitor C has a function of separating the first FET 1 and the second FET 2 in a DC manner.

The control terminal Ctl-1 is also one of the features of the present invention, and is formed by one terminal.

A resistor R is connected to each of the gate electrodes, connection means, and bias means of each of the FETs 1 and 2, and a high-frequency signal leaks through the gate electrode with respect to the DC potential of the control terminal Ctl-1 which becomes AC ground. It is arranged for the purpose of preventing that.

Next, the operation principle of the compound semiconductor switch circuit device of the present invention will be described with reference to FIGS.

In the case of the SPDT switch, in order to reduce the number of control terminals to one, the control voltage applied to the control terminals must be 0V.
When either of the FETs is on, the other F
When ET is turned off and the control voltage is a positive voltage, the state may be reversed.

FIG. 2 shows a circuit portion corresponding to the second FET 2. Since the FET is grounded by the grounding means via the resistor R, the gate voltage is fixed at 0V. This F
The bias condition for turning on the ET is a state in which the respective potential differences between the gate and the drain and between the gate and the source are equal. That is, since V _g = V _d = V _s and the gate voltage V _g is 0 V, the FET is turned on when V _g = V _d = V _s = 0 V.

Conversely, the bias condition that the FET is turned off when the gate voltage is 0 V can be obtained by applying a potential difference between the gate and the drain and between the gate and the source that turns the FET off. Therefore, in this circuit, when 0 V is applied to the control terminal, the FET is turned on, and when a positive voltage (for example, 3 V) is applied, the FET is turned off.

FIG. 3 shows a circuit portion corresponding to the first FET 1. The bias condition for turning off the FET at a gate voltage of 0 V may be such that a potential difference that turns off between the gate and the drain and between the gate and the source is applied. Therefore,
What is necessary is just to connect the circuit (bias means) which always applies a bias to the source or drain side.

Conversely, when a potential equal to the bias voltage is applied from the control terminal to the gate, the FET is turned on.
Therefore, in this circuit, when the control terminal is at 0V, the FET is turned off, and at 3V, the FET is turned on.

The combination of the circuits of FIGS. 2 and 3 is the compound semiconductor switch circuit device of the present invention shown in FIG. A first FET 1 and a second FET 2 with a capacitance C
Are separated in a DC manner to prevent interference between the bias conditions, and the control terminal shown in FIG.
It should be connected to -1.

The feature of the circuit of FIG. 1 is that one of the FETs (FE
T2), the gate of which is grounded via the resistor R, and the bias of the FET whose gate is grounded (FET2)
The point common to the control terminal Ctl-1 of the ET (FET1), the point that the bias of the FET (FET1) is always supplied at a constant voltage E, and the fact that the FET (FET1) and F
ET (FET2) is DC-separated by the capacitor C.

Next, the operation result will be described with reference to FIGS.

FIG. 4A shows the _case where the control voltage V _Ctl of the control terminal Ctl-1 is 0 V, that is, when the first FET 1 is in the ON state, the common input terminal IN-the output terminal OUT1 and the common input terminal IN- Insertion loss between output terminals OUT2 (Ins
ertion Loss) and isolation (Isolation) characteristics. The insertion loss is good up to 2.2 GHz, and the isolation is the same.

FIG. 4B shows the _case where the control voltage V _Ctl of the control terminal Ctl-1 is 3 V, that is, when the second FET 2 is on, the common input terminal IN-the output terminal OUT2 and the common input terminal IN- Insertion loss between output terminals OUT1 (Ins
ertion Loss) and isolation (Isolation) characteristics. The Insertion Loss is good up to 2.8 GHz, as is the Isolation.

FIG. 5 shows a compound semiconductor chip 1 in which the compound semiconductor switch circuit device of the present invention shown in FIG. 1 is integrated.
An example is shown.

FET1 and FET2 for switching are arranged on the GaAs substrate on the left and right, a capacitor terminal C, a common input terminal IN and one control terminal CTL are on the upper side, and an output terminal OUT2, a ground terminal GND and an output terminal OUT are on the lower side.
2 are provided around the periphery of the substrate. Note that the second-layer wiring indicated by the dotted line is a gate metal layer (Ti / Pt
/ Au) 20, and the third layer wiring shown by the solid line is a pad metal layer (T
(i / Pt / Au) 30. An ohmic metal layer (AuGe / Ni / A) in ohmic contact with the first substrate
u) 10 forms a source electrode, a drain electrode of each FET, and extraction electrodes at both ends of each resistor.

The capacitor C is externally connected between the capacitor terminal C and the common input terminal IN.
Is also externally connected between the output terminal OUT1 and the ground terminal GND.

In particular, in the compound semiconductor switch circuit device of the present invention, the means for connecting the control terminal Ctl-1 and the second output terminal OUT2, which are the connection means, with the resistor R is the first output terminal OUT1 in terms of the circuit. To the second output terminal O
Since the wiring crosses the wiring to UT2, there is a possibility that the chip area may be increased due to the arrangement of the resistor R. In the compound semiconductor chip in which the compound semiconductor switch circuit device of the present invention shown in FIG. 6 is integrated, various devices described below are added.

First, in the arrangement of the resistor R of the connection means, the resistor R is linearly extended in the lateral direction between the pad of the upper common input terminal IN and one control terminal CTL and the FET1. One end of the resistor R is connected to a pad of one control terminal CTL, and the other end is connected to a drain electrode (or a source electrode) of the FET2. As a result, the resistor R fits exactly along the pad of the common input terminal IN and one control terminal CTL, and hardly increases the chip area.

Second, in the arrangement of the resistor R of the grounding means, the resistor R is bent in the space between the FET1 and the FET2 above the pad of the ground terminal GND. One end of the resistor R is connected to the pad of the ground terminal GND, and the other end is connected to the gate electrode of the FET2. This resistance R is the resistance R of the connection means described above.
The resistance R can be arranged at the center of the chip, and there is an advantage that the chip area can be significantly reduced as compared with the case where the resistance R is turned around the chip.

Here, referring to FIG.
The multilayer structure of the drain electrode of the FET 2 will be described.
The resistance R of the grounding means is formed by an n + -type high concentration region 40 which is ion-implanted at the same time when the source region and the drain region are formed in the substrate 11. At both ends of the n + -type high-concentration region 40, a first-layer ohmic metal layer 10 is provided, and the other portions are covered with an oxide film 41 and contact the first-layer ohmic metal layer 10. The pad metal layer 30 of the layer is provided at the same time when the drain electrode and the source electrode are formed. Therefore, the drain electrode 18 of the FET 2
Since the resistance R and the drain electrode 18 of the FET 2 are interlayer-insulated by the oxide film 41, the intersection can be realized.

[0042]

As described in detail above, according to the present invention, the following effects can be obtained.

First, an SPDT (Singl) using a GaAs FET at one control terminal without using an inverter circuit.
e Pole Double Throw) can be realized. This eliminates the need to prepare inverter circuits for the number of control terminals, simplifies the circuit arrangement, and reduces the mounting area of the printed circuit board. In addition, power consumption can be reduced.

Second, in the compound semiconductor switch circuit device of the present invention, the control signal can be switched with a single positive power supply of 3 V / 0 V, and a negative voltage generation circuit required when using a GaAs FET is omitted. Can be operated by one type, so that the mounting area can be reduced.

Third, in the present invention, the ground terminal GND and the capacitance terminal C are increased, but the number of control terminals is reduced to one. As a result, the chip size of the compound semiconductor switch circuit device can be made almost equal to the current one, The ease of handling with a single control terminal can greatly contribute to mounting on a set.

Fourth, insertion loss and isolation characteristics can be assured as in current products.

Fifth, since the arrangement of the resistor R of the connecting means extends linearly in the lateral direction between the pad of the upper common input terminal IN and one control terminal CTL and the FET1,
The resistor R fits exactly along the pad of the common input terminal IN and one control terminal CTL and hardly increases the chip area.

Sixth, the resistor R of the grounding means is bent in the space between the FET1 and the FET2 above the pad of the ground terminal GND, and the drain connected to the other end of the resistor R of the connecting means. Since the resistor R can be arranged at the center of the chip so as to intersect with the electrodes, the chip area can be significantly reduced as compared with the case where the resistor R is arranged around the periphery of the chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining the present invention.

FIG. 2 is a circuit diagram for explaining the present invention.

FIG. 3 is a circuit diagram for explaining the present invention.

4A and 4B are characteristic diagrams for explaining the present invention, and FIG.
It is a characteristic diagram.

FIG. 5 is a plan view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

7A is a cross-sectional view for explaining a conventional example, and FIG.
It is a circuit diagram.

FIG. 8 is a plan view for explaining a conventional example.

9A is a plan view for explaining a conventional example, and FIG.
It is sectional drawing.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F102 FA00 GA01 GA17 GB01 GC01 GD01 GS02 GS09 GT03 5J012 BA03 5J055 AX47 AX54 AX66 BX04 CX03 DX25 DX65 DX73 DX83 EX07 EX21 EY01 EY10 EY24 FX12 FX17 FX35 GX01 GX06 GX07

Claims (8)

[Claims] 1. First and second FETs provided with a source electrode, a gate electrode and a drain electrode on a surface of a channel layer
A common input terminal connected to the source electrode or the drain electrode of the two FETs; first and second output terminals connected to the drain electrode or the source electrode of the two FETs; Bias means for applying a predetermined bias to a first output terminal; connection means for connecting a control terminal to the second output terminal;
Grounding means for grounding the gate electrode of the ET; and separating means for direct current separation between the common input terminal and the source electrode or the drain electrode of the second FET, wherein the connecting means extends along the pad. Wherein a control signal is applied to the control terminal connected to a gate electrode of the first FET. 2. The compound semiconductor switch circuit device according to claim 1, wherein said connection means is formed by a resistor. 3. A first and a second FET having a source electrode, a gate electrode and a drain electrode provided on a surface of a channel layer.
A common input terminal connected to the source electrode or the drain electrode of the two FETs; first and second output terminals connected to the drain electrode or the source electrode of the two FETs; Bias means for applying a predetermined bias to a first output terminal; connection means for connecting a control terminal to the second output terminal;
Grounding means for grounding the gate electrode of the ET; and separating means for DC-separating the common input terminal and the source electrode or the drain electrode of the second FET, wherein the grounding means is provided at the center of the chip. Extending the first FET
Wherein a control signal is applied to said control terminal connected to said gate electrode. 4. The compound semiconductor switch circuit device according to claim 3, wherein said grounding means is formed by a resistor. 5. The compound semiconductor switch circuit device according to claim 4, wherein the resistance of the grounding means is formed in a high concentration region on the substrate and intersects with the drain electrode of the second FET. 6. The compound according to claim 1, wherein said first and second FETs comprise a gate electrode in Schottky contact with said channel layer and source and drain electrodes in ohmic contact with said channel layer. Semiconductor switch circuit device. 7. The method according to claim 1, wherein the first and second FETs are MESF
The compound semiconductor switch circuit device according to claim 1, wherein the compound semiconductor switch circuit device is formed of ET. 8. The semiconductor device according to claim 1, wherein said first and second FETs are formed integrally on a same semiconductor substrate, and said bias means and separation means are formed externally.
The compound semiconductor switch circuit device according to claim 1.