JP2001326333A - Compound semiconductor switch circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve the problems of a conventional compound semiconductor switch circuit device such as that a design method of lowering the ON resistance of an FET by taking the gate width Wg large so as to minimize insertion loss as far as possible has been adopted and that 20 μm or over has been taken as an interval between adjacent wiring layers. SOLUTION: The reduction of the ON resistance of an FET until now is considered secondarily, fixing eyes upon the design of securing isolation, omitting a shunt FET in a high frequency band of 2.4 GHz or over. That is, in a compound semiconductor switch circuit device, the size is made small, by setting the gate width of the FET for a switch, and also the coupling of high frequency signals and the security of breakdown strength are performed in small space, by providing a high concentration region right under a pad. As a result, the chip size can be made remarkably small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor switch circuit device particularly used for high-frequency switching, and more particularly to a compound semiconductor switch circuit device used in the 2.4 GHz band or higher.

[0002]

2. Description of the Related Art In mobile communication devices such as cellular phones, G
In many cases, microwaves in the Hz band are used, and switch elements for switching these high-frequency signals are often used in antenna switching circuits and transmission / reception switching circuits (for example, Japanese Patent Application Laid-Open No. Hei 9-181624). issue). As the element, a high-frequency field-effect transistor (hereinafter, FE) using gallium arsenide (GaAs) is used.
In many cases, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated has been developed.

FIG. 7A is a sectional view of a GaAs FET. An N-type impurity is doped into a surface portion of a non-doped GaAs substrate 1 to form an N-type channel region 2, and a gate electrode 3 in Schottky contact is disposed on the surface of the channel region 2. Source / drain electrodes 4 and 5 which are in ohmic contact with the GaAs surface are arranged. This transistor has a gate electrode 3
A depletion layer is formed in the channel region 2 immediately below by the potential, and thus a channel current between the source electrode 4 and the drain electrode 5 is controlled.

FIG. 7B is a circuit diagram showing the principle of a compound semiconductor switch circuit device called a SPDT (Single Pole Double Throw) using a GaAs FET.

The sources (or drains) of the first and second FETs 1 and 2 are connected to a common input terminal IN, and each F
The gates of ET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2,
The drain (or source) of each FET is the first and second
Are connected to the output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which the H-level signal is applied turns ON, and the signal applied to the input terminal IN The signal is transmitted to one of the output terminals. The resistances R1 and R2 are connected to a control terminal Ctl which is AC grounded
-1 and Ctl-2 are arranged for the purpose of preventing a high-frequency signal from leaking through the gate electrode with respect to the DC potential.

FIG. 8 shows an equivalent circuit diagram of such a compound semiconductor switch circuit device. In microwaves, the characteristic impedance is set to 50Ω, and the impedance of each terminal is represented by R1 = R2 = R3 = 50Ω resistance. When the potential of each terminal is V1, V2, V3, the insertion loss (Inser
tion Loss) and Isolation are represented by the following equations.

[0007] Insertion Loss = 20 log (V2 / V1) [dB] This is an insertion loss when a signal is transmitted from the common input terminal IN to the output terminal OUT1, and Isolation = 20 log (V3 / V1) [dB] Is an isolation between the common input terminal IN and the output terminal OUT2. In a compound semiconductor switch circuit device, it is required to reduce the above-mentioned insertion loss (Insertion Loss) as much as possible and to improve the isolation (Isolation), and it is important to design a FET inserted in series in a signal path. The reason for using a GaAs FET as this FET is that GaAs has a higher electron mobility than Si, so that resistance is small and low loss can be achieved. Since GaAs is a semi-insulating substrate, high isolation between signal paths can be achieved. Because it is suitable. On the other hand, a GaAs substrate is more expensive than Si, and if an equivalent device such as a PIN diode is made of Si, it will be defeated by cost competition.

FIG. 9 is a circuit diagram of a compound semiconductor switch circuit device which has been put to practical use. In this circuit, shunt FETs 3 and 4 are connected between the output terminals OUT1 and OUT2 of the FETs 1 and 2 to be switched and ground, and FE is connected to the gates of the shunt FETs 3 and 4.
Complementary signals of control terminals Ctl-2 and Ctl-1 to T2 and FET1 are applied. As a result, when FET1 is ON, shunt FET4 is ON, and FET2 and shunt FET3 are OFF.

In this circuit, when the signal path between the common input terminal IN and the output terminal OUT1 turns on and the signal path between the common input terminal IN and the output terminal OUT2 turns off, the shunt F
Since the ET4 is on, the leakage of the input signal to the output terminal OUT2 escapes to the ground via the grounded capacitor C, and the isolation can be improved.

FIG. 10 shows an example of a compound semiconductor chip in which such a compound semiconductor switch circuit device is integrated.

FET1 and FET2 for switching on a GaAs substrate are arranged at the left and right central portions, and a shunt FET is provided.
3 and shunt FETs 4 are arranged near the lower left and right corners, and resistors R1, R2, R3,
R4 is connected. Further, a common input terminal IN, output terminals OUT1, OUT2, control terminals Ctl-1, Ctl-
2. Pads corresponding to the ground terminal GND are provided around the substrate. Further, shunt FET3 and shunt F
The source electrode of ET4 is connected to the ground terminal GND via a capacitor C for grounding. In addition,
The second-layer wiring shown by the dotted line is a gate metal layer (Ti / Pt / A) formed simultaneously with the formation of the gate electrode of each FET.
u), and a third layer wiring shown by a solid line is a pad metal layer (Ti / Pt) for connecting each element and forming a pad.
/ Au). The ohmic metal layer (AuGe / Ni / Au) that makes ohmic contact with the first substrate is
A source electrode, a gate electrode of T, and extraction electrodes at both ends of each resistor are formed, and are not shown in FIG. 10 because they overlap with the pad metal layer.

FIG. 11A is an enlarged plan view of a portion of the FET 1 shown in FIG. In this figure, a rectangular region surrounded by a chain line is a channel region 12 formed on the substrate 11. Four comb-shaped third pad metal layers 30 extending from the left side are the source electrodes 13 (or drain electrodes) connected to the output terminal OUT1, and below the first ohmic metal layers 10 There is a source electrode 14 (or drain electrode) to be formed. Further, four comb-shaped third pad metal layers 30 extending from the right side are drain electrodes 15 (or source electrodes) connected to the common input terminal IN, and a first layer of ohmic metal is formed below the drain electrodes 15 (or source electrodes). There is a drain electrode 16 (or source electrode) formed in layer 10. These two electrodes are arranged in a shape in which the comb teeth are engaged with each other.
Are formed on the channel region 12 in a comb shape.

FIG. 11B is a sectional view of a part of the FET. The substrate 11 is provided with an n-type channel region 12 and n + -type high-concentration regions forming source and drain regions 18 and 19 on both sides thereof. The channel region 12 is provided with a gate electrode 17. Is provided with a drain electrode 14 and a source electrode 16 formed of the first ohmic metal layer 10. Further, as described above, the drain electrode 13 and the source electrode 15 formed by the third-layer pad metal layer 30 are provided thereon, and wiring and the like of each element are performed.

In the above-described compound semiconductor switch circuit device, the insertion loss (Insertion Loss) of FET1 and FET2 is
In order to reduce s) as much as possible, a design method has been adopted in which the gate width Wg is increased and the on-resistance of the FET is reduced. For this reason, due to the increase in the gate width Wg, the sizes of the FET1 and the FET2 have increased, and the development has been proceeding in the direction of increasing the chip size.

In the compound semiconductor switch circuit device, a GaAs substrate which is a semi-insulating substrate is used, and a wiring for directly forming a conductive path and a pad for thermally bonding a bonding wire are provided on the GaAs substrate. However, since signals to be handled are high frequencies in the GHz band, it is necessary to provide a separation distance of 20 μm or more in order to ensure isolation between adjacent wirings. The isolation required for the compound semiconductor switch circuit device is 20 dB or more, and a separation distance of 20 μm or more is necessary to experimentally secure the isolation of 20 dB or more.

Although this theoretical support is poor, the breakdown voltage has been considered to be infinite from the idea that a semi-insulating GaAs substrate is an insulating substrate. However, actual measurements showed that the withstand voltage was finite. For this reason, it is considered that the depletion layer extends in the semi-insulating GaAs substrate, and a change in the depletion layer distance according to the high-frequency signal causes the leakage of the high-frequency signal when the depletion layer reaches an adjacent electrode. . Therefore, it has been determined that a separation distance of 20 μm or more is necessary to ensure the isolation of 20 dB or more.

As is apparent from FIG. 10, in the conventional compound semiconductor switch circuit device, the common input terminal IN, the output terminals OUT1, OUT2, the control terminals Ctl-1, Ctl-
2. Pads corresponding to the ground terminal GND are provided around the substrate. Forming a wiring layer at a distance of at least 20 μm from this pad tends to further increase the chip size.

[0018]

In the above-described compound semiconductor switch circuit device, the gate width Wg is increased to minimize the insertion loss (Insertion Loss) of the FET1 and the FET2, and the design method for reducing the ON resistance of the FET is adopted. As a result, the size of each FET becomes large, and a separation distance of 20 μm is required for the design for securing the isolation between the pad and the wiring layer.

For this reason, the conventional compound semiconductor switch circuit device has become increasingly larger in chip size, and as long as a GaAs substrate which is more expensive than a silicon substrate is used, the compound semiconductor switch circuit device can be replaced with a low-cost silicon chip. Replacement was progressing, losing the market.

[0020]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been made to reduce the size of the FET by reducing the gate width and also reduce the distance between the pad and the wiring layer. Thus, a feature is to realize a compound semiconductor switch circuit device having a reduced chip size.

That is, a source electrode is provided on the surface of the channel layer,
First and second provided with a gate electrode and a drain electrode
Are formed, the source electrode or drain electrode of both FETs is used as a common input terminal, the first and second output terminals connected to the drain electrode or source electrode of both FETs, and connected to the gate electrodes of both FETs. A compound semiconductor switch circuit device that forms a signal path with the common input terminal and any one of the first and second output terminals by applying a control signal to a control terminal to make one of the FETs conductive. A high-concentration region is provided below the common input terminal, the first and second output terminals, and the pad serving as the control terminal, and the pattern is formed with another pattern of the compound semiconductor switch circuit device provided directly on the semi-insulating substrate. Separation distance is 2
The feature is that the thickness is set to 0 μm or less.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a compound semiconductor switch circuit device according to the present invention. First FET 1 and second F
The source electrode (or drain electrode) of ET2 is connected to the common input terminal IN, and the gate electrodes of FET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2, respectively. And FE
The drain electrodes (or source electrodes) of T1 and FET2 are connected to the first and second output terminals OUT1 and OUT2. First and second control terminals Ctl-1,
The control signal applied to Ctl-2 is a complementary signal,
The FET to which the level signal is applied is turned on, and the input signal applied to the common input terminal IN is transmitted to one of the output terminals. Resistance R1, R2
Are arranged for the purpose of preventing a high-frequency signal from leaking through the gate electrode with respect to the DC potential of the control terminals Ctl-1 and Ctl-2 to be AC grounded.

The circuit shown in FIG. 1 corresponds to the Ga shown in FIG.
SPDT (Single Pole Double Th Th) using As FET
row), which is substantially the same as the basic circuit of the compound semiconductor switch circuit device, except that the gate width Wg of the gate electrodes of the FET1 and the FET2 is designed to be 700 μm or less, and the pad and the wiring layer This is a significant reduction in the distance.

Reducing the gate width Wg as compared with the conventional one means increasing the on-resistance of the FET, and reducing the gate electrode area (Lg × Wg) to reduce the gate electrode and the channel region. Means that the parasitic capacitance due to the Schottky junction becomes smaller, and there is a large difference in circuit operation.

Further, greatly reducing the distance between the pad and the wiring layer greatly contributes to reducing the size of the compound semiconductor chip.

FIG. 2 shows an example of a compound semiconductor chip in which the compound semiconductor switch circuit device of the present invention is integrated.

FET1 and FET2 for switching on the GaAs substrate are arranged at the center, and resistors R1 and R2 are connected to the gate electrodes of each FET. Further, the common input terminal IN, the output terminals OUT1, OUT2, the control terminal Ctl-
1, pads corresponding to Ctl-2 are provided around the substrate. The wiring of the second layer indicated by the dotted line is
The gate metal layer (Ti / Pt / Au) 20 formed simultaneously with the formation of the T gate electrode is shown. The third layer wiring shown by the solid line is a pad metal layer (Ti) for connecting each element and forming a pad. / Pt / Au) 30. An ohmic metal layer (AuG) in ohmic contact with the first layer substrate
e / Ni / Au) 10 forms a source electrode, a gate electrode of each FET, and extraction electrodes at both ends of each resistor, and is not shown in FIG. 2 because it overlaps with a pad metal layer.

As is apparent from FIG. 2, the components are FETs
1, FET2, resistors R1, R2, common input terminal IN, output terminals OUT1, OUT2, control terminals Ctl-1, Ct
It is only a pad corresponding to 1-2, and is composed of the minimum components compared to the conventional compound semiconductor switch circuit device shown in FIG.

In the present invention, since the gate width of the FET 1 (same for the FET 2) is 700 μm or less, which is less than half of the conventional size, the FET 1 can be reduced to half the size of the conventional type. That is, the FET 1 shown in FIG. 2 is formed in a rectangular channel region 12 surrounded by a chain line. The three third comb-shaped pad metal layers 30 extending from the lower side are the source electrodes 13 (or drain electrodes) connected to the output terminal OUT1. Source electrode 14 formed of
(Or drain electrode). Also, three comb-shaped third pad metal layers 30 extending from the upper side are the drain electrode 15 (or source electrode) connected to the common input terminal IN, and below this, the first ohmic metal There is a drain electrode 14 (or source electrode) formed in layer 10. These two electrodes are arranged in a comb-toothed shape, and a gate electrode 17 formed of the second-layer gate metal layer 20 is arranged between the two electrodes on the channel region in a four-tooth shape. The middle comb-shaped drain electrode 13 (or source electrode) extending from the upper side is shared by the FET1 and the FET2, further contributing to miniaturization. Here, the meaning that the gate width is 700 μm or less means that the total sum of the gate widths of the comb-shaped gate electrodes 17 of each FET is 700 μm or less.

FIG. 11 shows the sectional structure of FET1 and FET2.
Since it is the same as the conventional one shown in FIG.

Next, a description will be made as to whether or not it is possible to omit the shunt FET in a high frequency band of 2.4 GHz or more and secure a design for ensuring isolation.

FIG. 3 shows that the gate length Lg of the FET is 0.5 μm.
The relationship between the gate width Wg and the insertion loss (Insertion Loss) at the time of m is shown.

For an input signal of 1 GHz, the gate width Wg
Is reduced from 1000 μm to 600 μm.
Insertion loss of 5 dB to 0.55 dB and 0.2 dB (Inser
tionLoss) gets worse. However, for an input signal of 2.4 GHz, the gate width Wg is 1000 μm to 600 μm.
When it is reduced to 0.65 dB, the insertion loss (Insertion Loss) of only 0.05 dB from 0.60 dB to 0.65 dB is sufficient. This is due to the insertion loss (Insertion Loss) for a 1 GHz input signal.
s) is greatly affected by the on-resistance of the FET,
For an input signal of 2.4 GHz, the insertion loss (Insertion L
oss) was not significantly affected by the on-resistance of the FET.

The reason is that an input signal of 2.4 GHz has a higher frequency than that of 1 GHz.
This is because the influence of the capacitance component caused by the gate electrode of the FET is considered to be greater than the on-resistance of the FET. For this reason, if the capacitance component has a greater influence on the insertion loss than the on-resistance of the FET at a high frequency of 2.4 GHz or more, it is better to design the circuit by focusing on reducing the capacitance component rather than the on-resistance. That is, an idea of completely reversing the conventional design was required.

On the other hand, FIG. 4 shows that when the gate length Lg of the FET is 0.5 μm, the gate width Wg-isolation (I
solation).

For an input signal of 1 GHz, the gate width Wg
Is reduced from 1000 μm to 600 μm.
The isolation from 5 dB to 23.5 dB and 4.0 dB is improved. Similarly, when the input signal is 2.4 GHz, the gate width Wg is from 1000 μm to 60 μm.
When it is reduced to 0 μm, it is 14 dB to 18 dB and 4.0
dB Isolation is improved. That is, it can be seen that the isolation is improved depending on the on-resistance of the FET.

Therefore, in a high frequency band of 2.4 GHz or more, as is apparent from FIG. 3, insertion loss (Insertion Loss) is obtained.
Taking into account that there is only a slight deterioration in the size of the compound semiconductor chip, the design with priority given to the isolation shown in FIG. That is, when the input signal is 2.4 GHz, if the gate width Wg is 700 μm or less, the isolation (Isolation) of 16.5 dB or more can be ensured, and further 600 μm.
If the gate width Wg is less than m, an isolation of 18 dB or more can be secured.

Specifically, in the compound semiconductor switch circuit device of the present invention whose actual pattern is shown in FIG. 2, an FE having a gate length Lg of 0.5 μm and a gate width Wg of 600 μm is used.
Designed for T1 and FET2, insert loss (Insertion Loss)
s) is 0.65 dB and isolation is 1
8 dB is secured. This feature allows Bluetooth (mobile phones, laptops, personal digital assistants, digital cameras, and other peripherals to wirelessly interconnect,
2.4GH including communication specifications to improve business environment)
z-band ISM Band (Industrial Scientific and Medi
It is used as a communication switch in the application field of spread spectrum communication using cal f requency band).

Next, a description will be given of how to greatly reduce the distance between the pad and the wiring layer.

FIGS. 2 and 6 show the structure of the pads of the compound semiconductor switch circuit device of the present invention. As shown in the plan view of FIG. 2, the common input terminal IN, the output terminals OUT1, OU
Five pads T2 and control terminals Ctl-1 and Ctl-2 are arranged around the substrate. As shown in FIG. 6, each pad has an n + type high concentration region 40 (shown by a two-dot chain line in FIG. 2), a gate metal layer 20, and a pad metal layer 3 on a substrate 11.
It is characterized by being formed with three layers of 0. High concentration area 4
0 is simultaneously formed in an ion implantation step for forming a source region and a drain region. Gold bonding wire 4
1 is ball bonded onto the pad metal layer of the pad.

Thus, unlike the case where the conventional pad is formed directly on the substrate 11, the substrate 11
The high concentration region 40 is provided on the surface. Therefore, the substrate 11 not doped with impurities (semi-insulating,
Substrate resistance is 1 × 10 ⁷ Ω · cm. Unlike the surface, the impurity concentration is high (ion type 29Si ⁺ and the concentration is 1 to 5 × 1).
Since the depletion layer immediately below the pad does not extend at a rate of 0 ⁸ cm ^-3 ), the distance between the pad and the adjacent wiring layer can be reduced from 20 μm to 5 μm at which isolation of 20 d can be ensured. As is apparent from FIG. 2, five pads occupy nearly half of the semiconductor chip. Therefore, if the structure of the pad of the present invention is adopted, the wiring layer can be arranged to the vicinity of the pad, which contributes to the reduction of the semiconductor chip. it can.

As a result, the size of the compound semiconductor chip of the present invention could be reduced to 0.37 × 0.30 mm 2. This is equivalent to a conventional compound semiconductor chip size of 20
% Can be reduced.

Further, in the compound semiconductor switch circuit device of the present invention, various circuit characteristics were improved. First, a VSWR (Voltage Standing-Wave Ratio) representing reflection at a switch with respect to high-frequency input power is 1.1 to 1.1.
1.2 has been achieved. VSWR represents a ratio between the maximum value and the minimum value of a voltage standing wave generated between a reflected wave generated at a discontinuous portion in the high-frequency transmission line and an input wave.
R = 1 means reflection 0. In a conventional compound semiconductor switch circuit device having a shunt FET, VSWR =
It is about 1.4, and in the present invention, the voltage standing wave ratio was significantly improved. The reason for this is that in the compound semiconductor switch circuit device of the present invention, a switching FET is provided in the high-frequency transmission line.
This is due to the fact that there are only FETs 1 and 2 and only FETs of a very small size in terms of circuit and device.

Secondly, the linearity characteristic representing the distortion level of the output signal with respect to the high frequency input signal realizes 30 dBm as P _IN 1 dB. FIG. 5 shows the linearity characteristics of the input and output power. Although the input / output power ratio is ideally 1, the output power is reduced by the insertion loss (InsertionLoss). Since the output power is distorted as the input power increases, the point at which the output power is lower by 1 dB than the input power is represented as _PIN 1 dB. In a compound semiconductor switch circuit device with a shunt FET, _PIN 1 dB is 26 dB
Bm, but 30 dBm in the compound semiconductor switch circuit device of the present invention without a shunt FET, which is about 4 dB.
The above improvements can be achieved. The reason for this is that when there is a shunt FET, the pinch-off voltage of the switch for turning off and the shunt FET are synergistically affected, whereas in the case of the present invention without the shunt FET, the F for the switch which is turned off is used.
This is because it is only the effect of the ET.

[0046]

As described in detail above, according to the present invention, the following effects can be obtained.

First, in a high frequency band of 2.4 GHz or more, shunt FET is omitted and isolation is performed.
Focusing on the design for securing the gate width, using the reversal idea means that considers the reduction of the on-resistance of the FET in a conventional manner, the gate width Wg of the gate electrodes of the FET1 and the FET2 used for the switch is designed to be 700 μm or less. That is. As a result, it is possible to obtain an advantage that the size of the FET1 and the FET2 used for the switch can be reduced, the insertion loss can be suppressed, and the isolation can be secured.

Second, since the compound semiconductor switch circuit device of the present invention can be designed without the shunt FET, the components are FET1, FET2, resistors R1, R
2, common input terminal IN, output terminals OUT1, OUT2,
Only the pads corresponding to the control terminals Ctl-1 and Ctl-2 are provided, which has an advantage that it can be configured with a minimum number of components as compared with the conventional compound semiconductor switch circuit device.

Third, by providing a high-concentration region immediately below a pad occupying almost half of the size of a semiconductor chip, a wiring layer adjacent to the pad can be arranged as close as 5 μm. Has the advantage that it can be made in a small space and a large shrink is possible.

Fourth, as described above, the semiconductor chip size can be reduced by 20% compared to the conventional compound semiconductor switch circuit device by reducing the distance between the minimum component, the pad and the wiring layer.
%, And the price competitiveness with silicon semiconductor chips can be greatly improved. In addition, since the chip size can be reduced, a smaller package (SMCP6, 1.6 mm × 1.6), which is smaller than a conventional small package (MCP6, 2.1 mm × 2.0 mm × 0.9 mm).
mm × 0.75 mm).

Fifth, the insertion loss (Insertion Loss) is 2.
Even if the frequency becomes higher than 4 GHz, it does not increase much, so even if the shunt FET is omitted, the isolation (Isola
option). For example, 3GH
shunt FE even if gate width is 300μm with input signal of z
Without T, sufficient isolation can be ensured.

Sixth, in the compound semiconductor switch circuit device of the present invention, the voltage standing wave ratio VSWR (Voltage Standing-Wav) representing the reflection of the high frequency input power at the switch.
e Ratio) of 1.1 to 1.2, and a switch with less reflection can be provided.

Seventh, in the compound semiconductor switch circuit device of the present invention, the linearity characteristic _PIN 1 dB representing the distortion level of the output signal with respect to the high-frequency input signal can be improved to 30 dBm, and the linearity characteristic of the switch can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a characteristic diagram for explaining the present invention.

FIG. 5 is a characteristic diagram for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

7A is a cross-sectional view for explaining a conventional example, and FIG.
It is a circuit diagram.

FIG. 8 is an equivalent circuit diagram for explaining a conventional example.

FIG. 9 is a circuit diagram for explaining a conventional example.

FIG. 10 is a plan view for explaining a conventional example.

FIG. 11A is a plan view for explaining a conventional example,
(B) It is sectional drawing.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 17/693 (72) Inventor Koichi Hirata 2-5-5 Keihanhondori, Moriguchi-shi, Osaka SANYO ELECTRIC F term (reference) 5F102 FA10 GA01 GA17 GB01 GC01 GD01 GJ05 GR07 GS02 GS04 GS09 GT03 GV03 5J012 BA02 5J055 AX47 BX12 CX03 DX25 DX53 EX07 EX21 EY01 EY23 FX12 FX17 FX35 GX01 GX06 GX07 GX08

Claims (4)

[Claims] 1. First and second FETs provided with a source electrode, a gate electrode and a drain electrode on a surface of a channel layer
And a control electrode connected to the gate electrodes of both FETs, using the source electrode or the drain electrode of both FETs as a common input terminal, the first and second output terminals connected to the drain electrode or the source electrode of both FETs. In a compound semiconductor switch circuit device, a control signal is applied to a terminal to make one of the FETs conductive to form a signal path with the common input terminal and one of the first and second output terminals. Input terminal, said first and second
A high-concentration region is provided below the output terminal and the pad serving as the control terminal, and a separation distance from another pattern of the compound semiconductor switch circuit device directly provided on the semi-insulating substrate is 20 μm.
A compound semiconductor switch circuit device characterized by the following. 2. The compound semiconductor switch circuit device according to claim 1, wherein a diffusion region of a source region and a drain region is used as said high concentration region. 3. The compound semiconductor switch circuit device according to claim 1, wherein a GaAs substrate is used as said semi-insulating substrate, and said channel layer is formed on a surface thereof. 4. The compound according to claim 1, wherein said first and second FETs comprise a gate electrode in Schottky contact with said channel layer and source and drain electrodes in ohmic contact with said channel layer. Semiconductor switch circuit device.