JPH09139630A - Portable communication equipment and power amplifier in portable communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the power amplifier capable compensating a temperature without provision of a temperature compensation circuit. SOLUTION: The power amplifier is provided with a self-bias type gate bias circuit in which an amplifier FET amplifying a received high frequency power, a resistor and a temperature compensation FET formed on a GaAs substrate are connected in series. One terminal of the gate bias circuit connects to a voltage power supply and the other terminal connects to ground. A connecting point between the resistor and the temperature compensation FET in the gate bias circuit connects to a gate of the amplifier FET. A gate azimuth of the amplifier FET with respect to orientation flat of the GaAs substrate is selected to e 90 deg. and a gate azimuth of the temperature compensation FET with respect to orientation flat of the GaAs substrate is selected to be 0 deg., and the temperature characteristic of the amplifier FET is selected to be reverse to that of the temperature compensation FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier in a portable communication device, and more particularly to a high frequency power amplifier used in a small and low cost portable communication device.

[0002]

2. Description of the Related Art In recent years, portable communication devices, especially mobile phones, have become widespread, and there has been an increasing demand for higher performance of high frequency power amplifiers used in the portable communication devices.

FIG. 13 shows a conventional example of a two-stage power amplifier device having a gate bias circuit formed on a compound semiconductor such as gallium arsenide (GaAs) used in a mobile phone. In FIG. 13, reference numeral 1 denotes a source-grounded front-stage amplification F that serves as a front-stage power amplification circuit.
ET, 2 are FETs for amplification in the latter stage of the source grounded to be the power amplification circuit in the latter stage, and 3 is, for example, 5 of the high frequency power of the input signal.
An input matching circuit for converting an impedance of 0Ω into an optimum impedance for the amplification FET 1 in the preceding stage, and 4 is an interstage for converting the impedance of the high frequency power output from the amplification FET 1 in the preceding stage into the optimum impedance for the amplification FET 2 in the subsequent stage. Matching circuit, 5 is a post-stage amplification F
An output matching circuit for converting the impedance of the high frequency power output from the ET2 into the impedance of the antenna side wiring, for example, 50Ω, 6 is a high frequency power so that the drain voltage of the amplification FET1 in the preceding stage is not affected by the high frequency power of the input signal. The drain bias circuit in the front stage set to be open (open), 7 is the FE for amplification in the rear stage
The drain bias circuit of the latter stage is set so that the drain voltage of T2 is opened in high frequency so as not to be affected by the high frequency power of the input signal, and 8E converts the high frequency power of the input signal into direct current. FET1 for amplification in the previous stage
The gate bias circuit in the front stage for inputting the high frequency power of the input signal into a direct current and input to the gate of the amplification FET 2 in the rear stage is input to the gate bias circuit in the front stage. In the gate bias circuits 8E and 9E in the front and rear stages, the amplification F in the front and rear stages is used.
The gate bias voltage is obtained by resistance division so that optimum voltages are applied to the gates of ET1 and ET2, respectively.

FIG. 14 shows the temperature dependence of the operating current and the gain in the power amplifier circuit device of the two-stage configuration. From FIG. 14, the operating current changes when the ambient temperature of the power amplifier circuit device changes. It can be seen that the gain also changes with. If the power amplification circuit device is used in, for example, a mobile phone without considering the temperature dependence of the power amplification circuit device, a difference occurs in transmission power between when the temperature is low and when the temperature is high. It may not be possible to achieve good performance.

In order to compensate the temperature dependence of the power amplifier circuit device, the gate bias voltage of the FET may be controlled according to the temperature, but the gate bias circuits 8E and 8E on the front and rear stages shown in FIG. In 9E, since the gate bias voltage is applied to the amplification FETs 1 and 2 in the front stage and the rear stage by resistance division, the gate bias voltage is hardly affected by the temperature change.

Therefore, a temperature compensating circuit using a thermistor as shown in FIG. 15 is connected to the gate voltages V _g1 and V _g2 of the front and rear gate bias circuits 8E and 9E shown in FIG. The gate bias voltages of the amplification FETs 1 and 2 are controlled. That is, the temperature compensating circuit shown in FIG. 15 has an FE in which the operating current decreases as the temperature rises.
In the case of an amplifier circuit using T, the operating current decreases as the temperature rises, so the output gate voltage V _g rises. As a result, the operating current in the amplifier circuit hardly changes in the operating temperature range.

FIG. 16 is a block diagram of a transmitter of a portable telephone equipped with the temperature compensation circuit described above. In FIG. 16, 10C is a two-stage amplification type power amplification circuit shown in FIG. The temperature compensating circuit shown in 12 is an up converter for converting the frequency of the audio signal into the transmission frequency,
Reference numeral 13 is a pre-stage amplifier that amplifies the output from the up-converter 12, 14 is an isolator that prevents the high-frequency power output from the power amplification circuit 10C from flowing in the opposite direction, 1
Reference numeral 5 is an RF switch for switching between the transmission side and the output side, 16 is a filter for passing only high frequency power of a predetermined frequency,
Reference numeral 17 denotes an antenna that outputs a transmission signal and inputs a reception signal.

[0008]

However, when the temperature compensating circuit 11 is connected to the power amplifying circuit 10C as shown in FIG. 16, the temperature compensating circuit 11 requires a large space. The area of the power amplification device including the compensating circuit 11 becomes large, which hinders downsizing of the portable communication device and causes the cost increase of the portable communication device by the temperature compensating circuit 11. There is.

In view of the above, the present invention realizes a power amplification device capable of temperature compensation without including a temperature compensation circuit,
Accordingly, it is an object of the present invention to reduce the size and cost of the power amplification device and thus the portable communication device.

[0010]

In order to achieve the above object, the present invention replaces a part of the resistance of a gate bias circuit composed of a plurality of divided resistances with a temperature compensating FET, and at the same time, for amplification. The temperature characteristic of the FET and the temperature characteristic of the temperature compensating FET are made opposite to each other.

Specifically, a solution means taken by the invention of claim 1 is a power amplifying device for a portable communication device, which is formed on a compound semiconductor substrate and has an amplifying FET for amplifying inputted high frequency power. A series circuit including a resistor and a temperature compensating FET formed on the compound semiconductor substrate, and a crystal orientation of a gate of the amplifying FET with respect to the compound semiconductor substrate on which the amplifying FET is formed, and the temperature compensating The crystal orientation of the gate of the temperature-compensating FET with respect to the compound semiconductor substrate on which the temperature-compensating FET is formed is set so that the temperature characteristic of the amplifying FET and the temperature characteristic of the temperature-compensating FET are opposite to each other. Has been done,
One end of the series circuit is connected to a voltage power source and the other end of the series circuit is grounded, and the connection point between the resistance and the temperature compensation FET in the series circuit is the gate of the amplification FET. It is configured to be connected to.

According to the structure of claim 1, one end of the series circuit composed of the resistance and the temperature compensation FET is connected to the voltage power supply and the other end is grounded, and the resistance and the temperature compensation FET in the series circuit are connected to each other. Since the connection point of is connected to the gate of the amplification FET, the series circuit becomes a resistance-divided gate bias circuit. The crystal orientation of the gate of the amplification FET and the crystal orientation of the gate of the temperature compensation FET are
Since the temperature characteristic of the amplifying FET and the temperature characteristic of the temperature compensating FET are set to be opposite to each other, when the temperature rises and the operating current of the amplifying FET is about to increase, When the operating current of the compensating FET is reduced to suppress the increase of the operating current of the amplifying FET, and the temperature is lowered to try to reduce the operating current of the amplifying FET,
Since the operating current of the temperature compensating FET increases and the decrease of the operating current of the amplifying FET is suppressed, the change amount of the operating current of the amplifying FET due to the temperature decreases.

According to a second aspect of the present invention, the amplification FET and the temperature compensation FET are formed on the same compound semiconductor substrate in addition to the structure of the first aspect.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, a configuration in which the transconductance of the amplification FET is higher than that of the temperature compensation FET is added.

According to a fourth aspect of the present invention, there is provided a solving means for a portable communication device having a two-stage power amplifying device for amplifying input high frequency power, the two-stage power amplifying device being configured. At least one power amplifying means of the former power amplifying means and the latter power amplifying means is formed on the compound semiconductor substrate and has an amplifying FET for amplifying the inputted high frequency power, a resistor and the compound semiconductor substrate. A series circuit including a temperature compensation FET formed above, and a crystal orientation of a gate of the amplification FET with respect to a compound semiconductor substrate on which the amplification FET is formed,
The crystal orientation of the gate of the temperature compensating FET with respect to the compound semiconductor substrate on which the temperature compensating FET is formed is the temperature characteristic of the amplifying FET and the temperature compensating FE.
The temperature characteristics of T are set to be opposite to each other, one end of the series circuit is connected to a voltage power supply, and the other end of the series circuit is grounded. The connection point between the resistor and the temperature compensation FET is connected to the gate of the amplification FET.

According to a fifth aspect of the present invention, in addition to the configuration of the fourth aspect, the amplification FET and the temperature compensation FET are formed on the same compound semiconductor substrate.

According to a sixth aspect of the present invention, in addition to the configuration of the fourth or fifth aspect, a configuration in which the transconductance of the amplification FET is higher than the transconductance of the temperature compensation FET is added.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A power amplifier device and a portable communication device in a portable communication device according to an embodiment of the present invention will be described below. As a premise, a power amplifier circuit commonly used in each embodiment. Will be described.

FIG. 1 shows a first power amplifier circuit commonly used in the respective embodiments. In FIG. 1, the same reference numerals are used for the circuits similar to those of the power amplifier device described with reference to FIG. The description is omitted by adding.

The characteristic of the first power amplifier circuit is shown in FIG.
The first gate bias circuit 8A in the front stage and the first gate bias circuit 9A in the rear stage (not shown) are provided as shown in FIG. The first gate bias circuit 9A in the subsequent stage has the same circuit configuration as the first gate bias circuit 8A in the previous stage, and therefore only the first gate bias circuit 8A in the previous stage will be described below.

As shown in FIG. 2 (a), the first gate bias circuit 8A includes a first resistor 21 and a second resistor 22.
And a temperature compensation FET 23 are connected in series to form a bias series circuit. One end of the first resistor 21, which is one end of the bias series circuit, is grounded, and the grounding side capacitor 24 is connected in parallel with the first resistor 21. The source of the temperature compensating FET 23, which is the other end of the bias series circuit, is connected to the gate voltage power supply V _g and is also grounded via the power supply side capacitor 25. Ground side capacitor 24 and power source side capacitor 2
Reference numeral 5 has a function as a pass capacitor that releases high frequency components.

The connection point 26 between the second resistor 22 and the temperature compensating FET 23 is connected to the gate of the amplification FET 1 in the preceding stage, and the connection point 26 gives the gate voltage V _gg1 to the amplification FET 1 in the preceding stage. The threshold voltage of the temperature compensating FET 23 is set higher than the threshold value of the amplifying FET 1 in the previous stage, and the operating current of the temperature compensating FET 23 changes depending on the temperature.
Acts as a temperature compensating resistor.

FIG. 2B shows the circuit configuration of the second gate bias circuit 8B used in the second power amplifier circuit. The second gate bias circuit 8B is different from the first gate bias circuit 8A in that one end of the first resistor 21, which is one end side of the bias series circuit, is connected to the gate voltage power supply V _g and the first resistor is also connected. A power supply side capacitor 25 is connected in parallel with the capacitor 21. The source of the temperature compensating FET 23 on the other end side of the bias series circuit is directly grounded. The second resistor 22 and the temperature compensating FET 2
_Similar to the first gate bias circuit 8A, the connection point 26 with 3 gives a gate voltage _Vgg1 to the amplification FET.

FIG. 2C shows a circuit configuration of the third gate bias circuit 8C used in the third power amplifier circuit. The third gate bias circuit 8C has a circuit configuration in which the first resistor 21 is removed from the first gate bias circuit 8A, one end of the second resistor 22 is directly grounded, and the grounding side capacitor 24 is connected. Grounded through.

FIG. 2D shows the circuit configuration of the fourth gate bias circuit 8D used in the fourth power amplifier circuit. The fourth gate bias circuit 8D has a circuit configuration in which the first resistor 21 is removed from the second gate bias circuit 8B, and one end of the second resistor 22 has a gate voltage power supply V _g.
And is grounded via the power supply side capacitor 25.

In the first to fourth embodiments described below, the case of using the first gate bias circuit 8A will be described. However, instead of the first gate bias circuit 8A, the second to fourth embodiments are used. Gate bias circuits 8B, 8C, 8
You may use D.

(First Embodiment) FIG. 3 shows a planar structure of an MCM (multi-chip module) which is a power amplifying device in a portable communication device according to a first embodiment of the present invention. As shown in FIG. 3, on the printed circuit board 30, a first FET 31 serving as a front-stage amplification FET 1, a second FET 32 serving as a rear-stage amplification FET 2, an input matching circuit 3, an inter-stage matching circuit 4, An output matching circuit 5, a front stage drain bias circuit 6, a rear stage drain bias circuit 7, a front stage gate bias circuit 8A and a rear stage gate bias circuit 9A are mounted. Although not shown, the drain bias circuit 6 at the front stage and the drain bias circuit 7 at the rear stage are each configured by a wiring pattern and a chip capacitor. The input matching circuit 3, the inter-stage matching circuit 4, and the output matching circuit 5 are each composed of a wiring pattern, a chip capacitor, and a chip resistor, though not shown.

Further, on the printed circuit board 30, the input pad 3a of the input matching circuit 3, the wiring pattern 3b connecting the input pad 3a and the input matching circuit 3,
The output pad 5a of the output matching circuit 5, the wiring pattern 5b connecting the output pad 5a and the output matching circuit 5, the drain pad 6a of the pre-stage side drain bias circuit 6, the drain pad 6a and the pre-stage side drain bias circuit 6 are provided. A wiring pad 6b to be connected, a drain pad 7a of the rear side drain bias circuit 7 and a wiring pattern 7b for connecting the drain pad 7a and the rear side drain bias circuit 7 are formed.

As a feature of the first embodiment, on the printed circuit board 30, a gate pad 8a serving as a gate voltage power source V _g , a ground pad 8b serving as a ground, which constitutes the first gate bias circuit 8A, The first chip resistor 8c serving as the first resistor 21, the second chip resistor 8d serving as the second resistor 22, and the third FET serving as the temperature compensating FET 23.
33 and a wiring pattern 8e for connecting them, and the first gate bias circuit 9A in the subsequent stage.
, The gate pad 9a, the ground pad 9b,
A first chip resistor 9c, a second chip resistor 9d, a fourth FET 34 and a wiring pattern 8e are formed.
The ground-side capacitor 24 and the power-source-side capacitor 25 do not affect the direct current, and therefore are not shown in order to simplify the drawing.

The above-mentioned first to fourth FETs 31 to 34 are
It is individually formed on the semi-insulating compound semiconductor substrate made of GaAs shown in FIG. The compound semiconductor substrate has a plane orientation of (100) and an orientation flat (hereinafter, abbreviated as orientation flat) orientation is a [0 -1 -1] direction.

Since GaAs is composed of two elements unlike Si (silicon), Ga and As have weak polarities (+ and-). For this reason, it is known that even if FETs of the same size are manufactured under the same conditions and on the same GaAs substrate, gm and a threshold value differ due to the piezo effect when the gate orientation is different (for example, reference: P.
Asbeck et al. "Piezoelectric Effects in GaAs FET's
and Their Role in Orientation-Dependent Device Cha
racteristics "IEEE Transactions on Electron Devic
es, Vol.ED-31, No.10, pp.1377-1380, 1984).
Therefore, the temperature characteristic of the FET also differs depending on the gate orientation.

In FIG. 6, the gate orientation is 0 ° with respect to the orientation flat.
([0 -1 -1] direction) and the gate orientation is 9
An example of the temperature dependence of the operating current of the FET that is 0 ° ([0 −1 1] direction) is shown. From Figure 6, the gate direction is 0
It can be seen that the operating current of the FET of 90 ° increases as the temperature rises, but the operating current of the FET of which the gate orientation is 90 ° decreases as the temperature rises.

FIG. 7 shows an example of the gate voltage dependence of gm per unit gate width of an FET having a gate orientation of 0 ° and an FET having a gate orientation of 90 °. From FIG. 7, it can be seen that, when the gate voltage is the same, the gm (transconductance) per unit gate width is larger in the FET having a gate orientation of 90 ° than in the FET having a gate orientation of 0 °.

FIG. 8 shows gm per unit gate width of FET.
Shows the gate orientation dependency of. As can be seen from FIG. 8, gm increases as the gate orientation changes from 0 ° to 90 °.

The description will be made again with reference to FIG. A first FET 31 and a second FET 32 that are amplification FETs
Set the gate azimuth of the device to 90 ° with respect to the orientation flat, and the third FET 33 and the fourth FET which are temperature compensation FETs.
The gate azimuth of 34 is set to 0 ° with respect to the orientation flat.
The third FET 33 of the first gate bias circuit 8A and the fourth FET 34 of the second gate bias circuit 9A are
In both cases, as shown in FIG. 2A, the source and the gate are directly connected to each other, and the self-bias type is used, and the resistance between the source and the drain (R ₃ , R ₆ in FIG. 1) is 500Ω to 2k.
Set to about Ω. Then, the first shown in FIG.
And the resistors R ₁ and R ₂ and the resistors R ₄ and R ₅ in the second gate bias circuits 8A and 8B are set appropriately,
So that a desired gate bias for the FET 31 and the second FET 32 can be obtained.

As described above, the gate orientations of the third and fourth FETs 33 and 34, which are FETs for temperature compensation, and the first and second FETs 31 and 32, which are FETs for amplification, are different from each other by 90 °. As the temperature rises, the operating currents of the first and second FETs 31 and 32 tend to increase, but the operating currents of the third and fourth FETs 33 and 34 tend to decrease. Therefore, V _gg1 and V _gg2 in FIG.
The respective potentials of 1 become lower as the temperature rises.

FIG. 9 shows the temperature dependence of the operating current of the power amplifying device according to the first embodiment. As can be seen from FIG. 9, the first amplifying FET 1 and the second amplifying FET 2 In such a power amplifier circuit, it is possible to reduce a change in operating current due to temperature.

Contrary to the first embodiment, the gate orientation of the first FET 31 and the second FET 32, which are amplification FETs, is set to 0 ° with respect to the orientation flat, and is a temperature compensation FET. Third FET 33 and fourth FET 34
The gate azimuth may be set to 90 ° with respect to the orientation flat. Also in this case, the first amplification FET 1 and the second amplification FET 2 are operated according to the same principle as that of the first embodiment.
The change in operating current due to temperature can be reduced.

As described with reference to FIGS. 7 and 8, the gm per unit gate width is larger in the FET having a gate orientation of 90 ° than in the FET having a gate orientation of 0 °. If the gate orientations of the FET 31 and the second FET 32 are set to 0 ° with respect to the orientation flat, the first F
This is disadvantageous in that the gain of the power amplification circuit is lower than in the case where the gate orientations of the ET 31 and the second FET 32 are set to 90 ° with respect to the orientation flat.

Therefore, in the first embodiment, the first FET 31 which is an amplifying FET requiring high gain is used.
Also, the gate direction of the second FET 32 is set to 90 ° with respect to the orientation flat, and the temperature compensating FET does not contribute to amplification.
The gate orientations of the third FET 33 and the fourth FET 34 are set to 0 ° with respect to the orientation flat.

As described above, according to the first embodiment,
Since the temperature compensating FET serving as a resistance is used in the gate bias circuit and the gate orientations of the temperature compensating FET and the amplifying FET are optimized, the temperature of the gate bias circuit has a temperature compensating function. It is possible to provide a power amplification device in which a change in the operating current is reduced even if it changes and the high gain originally possessed by the amplification FET formed on the substrate made of GaAs is not reduced.

In the first embodiment, the gate directions of the temperature compensating FET and the amplifying FET are set to 0 ° and 90 ° with respect to the orientation flat, respectively.
Since the gate orientation dependency of the temperature characteristics of the FET may depend on the manufacturing process of the FET, the gate orientation does not necessarily have to be set to 0 ° and 90 ° with respect to the orientation flat. After grasping the gate orientation dependency of the temperature characteristics of the FET, a FET having a gate orientation having a high gm is used as an amplifying FET, and a FET having a gate orientation having a temperature characteristic opposite to that of the amplifying FET is temperature-compensated. It is preferable to use it for an FET.

Further, in the first embodiment, GaAs is used as the compound semiconductor in which the temperature compensating FET and the amplifying FET are formed, but instead of this, another compound semiconductor such as InP (indium phosphide) is used. May be used.

(Second Embodiment) FIG. 10 shows a second embodiment of the present invention.
2 shows a planar structure of an MMIC (Microwave Monolithic IC) which is a power amplification device in the portable communication device according to the embodiment. As shown in FIG. 10, the GaAs substrate 4
On the top of 0, the first FET 4 which becomes the amplification FET 1 of the previous stage
1, a second FET 42 serving as a subsequent amplification FET 2, an input matching circuit 3, an interstage matching circuit 4, an output matching circuit 5, a front stage side gate bias circuit 8B and a rear stage side gate bias circuit 9B are formed. Although not shown, the input matching circuit 3, the inter-stage matching circuit 4, and the output matching circuit 5 each include a wiring pattern, a chip capacitor, and a chip resistor. Although not shown in the drawings, the drain bias circuits in the front stage and the rear stage each include a wiring pattern and a chip capacitor, and the drain pad 6
a, 7a. Also, on the GaAs substrate 40, the source pads 6c and 7c, as in the first embodiment,
An input pad 3a, a wiring pattern 3b, an output pad 5a and a wiring pattern 5b are formed.

A feature of the second embodiment is that, on the GaAs substrate 40, the first gate bias circuit 8A is constituted by the gate pad 8a serving as the gate voltage power supply V _g and the first resistor 21 serving as the first resistor 21. 1 chip resistor 8c, 2nd chip resistor 8d to become the second resistor 22, temperature compensating FET 2
The third FET 43 serving as the third FET 3 and the wiring pattern 8e for connecting these are formed, and the gate pad 9a, the first chip resistor 9c, and the second chip resistor that configure the second gate bias circuit 9A are formed. 9d, 4th FET
44 and the wiring pattern 9e are formed. That is, the feature of the second embodiment is that the first embodiment becomes the amplification FET.
FET 41 and second FET 42, and FE for temperature compensation
The third FET 43 and the fourth FET 44, which are T, are formed on the same GaAs substrate 40. The ground-side capacitor 24 and the power-source-side capacitor 25 do not affect the direct current, and therefore are not shown in order to simplify the drawing.

Also in the second embodiment, as shown in FIG. 5, the GaAs substrate 40 has a substrate surface orientation of (100) and an orientation flat orientation of [0 -1 -1]. Also,
Also in the second embodiment, the gate directions of the first FET 41 and the second FET 42, which are amplification FETs, are set to 90 ° with respect to the orientation flat, and the third FET 43 and the fourth FET, which are temperature compensation FETs, are set. The gate direction of the FET 44 is set to 0 ° with respect to the orientation flat. Each of the third FET 43 of the first gate bias circuit 8A and the fourth FET 44 of the second gate bias circuit 9A is a self-bias type in which the source and the gate are directly connected, and the resistance between the source and the drain ( R ₃ and R ₆ in FIG. 1 is 500Ω
It should be about 2 kΩ. Then, in the first and second gate bias circuits 8A and 8B shown in FIG. 1, the resistances R ₁ and R ₂ and the resistances R ₄ and R ₅ are appropriately set to obtain the desired values for the first FET 41 and the second FET 42. So that the gate bias of is obtained.

As described above, since the third and fourth FETs 43 and 44, which are the temperature compensating FETs, and the first and second FETs 41 and 42, which are the amplifying FETs, have different gate orientations from each other by 90 °. As the temperature rises, the operating currents of the first and second FETs 41432 tend to increase, but the operating currents of the third and fourth FETs 43, 44 tend to decrease. Therefore, V _gg1 and V _gg2 in FIG.
The respective potentials of 1 become lower as the temperature rises. Therefore, FIG.
1st amplification FET1 and 2nd amplification FET2 shown in FIG.
In the power amplifier circuit having the two-stage configuration, the change in operating current due to temperature can be reduced as shown in FIG.

In the second embodiment, the gate directions of the first FET 31 and the second FET 32, which are amplification FETs, are set to 90 ° with respect to the orientation flat, and the third FET, which is a temperature compensation FET, is set. FET 33 and fourth FET 3
The reason why the gate azimuth of No. 4 is set to 0 ° with respect to the orientation flat is the same as in the first embodiment.

As described above, according to the second embodiment,
Since the temperature compensating FET serving as a resistance is used in the gate bias circuit and the gate directions of the temperature compensating FET and the amplifying FET are optimized, the gate bias circuit has a temperature compensating function. It is possible to provide a power amplifying device in which the change in the operating current is reduced even when is changed, and the high gain originally possessed by the amplifying FET formed on the substrate made of GaAs is not reduced.

In the second embodiment, the gate orientations of the temperature compensating FET and the amplifying FET are set to 0 ° and 90 ° with respect to the orientation flat, but the temperature characteristic of the FET depends on the gate orientation. The gate orientation may not necessarily be set to 0 ° and 90 ° with respect to the orientation flat because the characteristics may depend on the FET manufacturing process. After grasping the gate orientation dependence of the temperature characteristics of the FET, an FET with a gate orientation having a high gm is used for amplification FE.
It is preferable to use a FET having a gate direction having a temperature characteristic opposite to that of the amplifying FET as the temperature compensating FET, as well as being used for T.

In the second embodiment, GaAs is used as the compound semiconductor in which the temperature compensating FET and the amplifying FET are formed, but instead of this, another compound semiconductor such as InP (indium phosphide) is used. May be used.

Further, since the compound semiconductor substrate is generally expensive, it is desirable to make the area of the compound semiconductor chip as small as possible in order to reduce the cost of parts. Therefore, instead of the second embodiment, the first FET that is an amplification FET is used.
And the second FETs 41 and 42 and the third and fourth FETs 43 and 44 which are temperature compensating FETs are formed on the same compound semiconductor substrate, and other resistors, matching circuits and the like are formed on the compound semiconductor substrate. May be formed on different substrates.

(Third Embodiment) FIG. 11 shows a third embodiment of the present invention.
FIG. 12 is a block diagram of a transmission unit of a mobile phone which is a portable communication device according to the embodiment of the present invention. In FIG. 11, 10A is a transmission amplifier (MCM) according to the first embodiment, and 12 is a frequency of an audio signal. An up-converter for converting to a high frequency suitable for the amplification FET of the amplifier 10A, a pre-amplifier 13 for amplifying the output from the up-converter 12,
14 is an isolator for preventing the high frequency power output from the transmission amplifier 10A from flowing in the opposite direction, 15 is an RF switch for switching between the transmission side block and the output side block,
Reference numeral 16 is a filter that passes only high-frequency power of a predetermined frequency, and 17 is an antenna that outputs a transmission signal and inputs a reception signal.

FIG. 16 shows a mobile phone according to the third embodiment.
The difference from the conventional mobile phone described above is that the transmission amplifier 10A does not have a temperature compensation circuit, and the transmission amplifier 10A has a temperature compensation FET built therein.

(Fourth Embodiment) FIG. 12 shows a fourth embodiment of the present invention.
3 is a block diagram of a transmission unit of a mobile phone which is a mobile communication device according to the embodiment of FIG. The fourth embodiment is different from the third embodiment in that the transmission amplifier (M
It is that the transmission amplifier (MMIC) 10B according to the second embodiment is provided instead of the CM) 10A.

According to the mobile phones according to the third and fourth embodiments, the transmission amplifiers 10A and 10B do not have a temperature compensation circuit, and therefore the transmission amplifiers 10A and 10B are not provided.
The mounting area of B can be reduced, and the cost of the transmission amplifiers 10A and 10B, and thus of the mobile phone, can be reduced by the amount of the temperature compensation circuit.

[0057]

According to the power amplification device in the portable communication device of the first aspect of the present invention, the crystal orientation of the gate of the amplification FET and the crystal orientation of the gate of the temperature compensation FET are:
The temperature characteristic of the amplifying FET and the temperature characteristic of the temperature compensating FET are set to be opposite to each other, and
Since the temperature compensating FET that constitutes the gate bias circuit has the temperature compensating function of the amplifying FET, it is not necessary to provide the temperature compensating circuit separately from the amplifying circuit, so that the number of parts is reduced, and as a result, It is possible to reduce the size and cost of the power amplifier device and thus the portable communication device.

According to the power amplification device in the portable communication device of the second aspect of the invention, since the amplification FET and the temperature compensation FET are formed on the same compound semiconductor substrate, the amplification on the compound semiconductor substrate is performed. By making the gate width direction of the temperature-use FET and the gate width direction of the temperature-compensation FET different from each other, the temperature characteristics of the amplification FET and the temperature characteristics of the temperature-compensation FET can be made opposite to each other. At the same time, the MMIC can be realized.

According to the power amplifying device in the portable communication device of the third aspect of the invention, since the mutual conductance of the amplifying FET is higher than that of the temperature compensating FET, the gain of the amplifying FET becomes high, while The temperature compensating FET, which does not contribute to amplification, may be low in transconductance, which is efficient.

According to the portable communication device of the fourth aspect of the present invention, since the portable communication device is provided with the power amplification device of the first aspect of the invention, it is possible to reduce the size and cost. Further, since the temperature compensation of the amplification FET can be performed without increasing the number of parts, it becomes easy to provide the temperature compensation FET in both the gate bias circuits in the front stage and the rear stage, and thus the temperature compensation function is provided. Can be reliably realized.

According to the portable communication device of the fifth aspect of the present invention, the portable communication device having the MMIC can be realized because it has the power amplifying device of the second aspect of the invention.

According to the portable communication device of the sixth aspect of the present invention, since the power amplifier device of the third aspect is provided, the gain of the amplifying FET can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a power amplifier circuit commonly used in each embodiment of the present invention.

FIG. 2 is a first view commonly used in each embodiment of the present invention.
FIG. 6 is a diagram showing first to fourth gate bias circuits forming a fourth power amplifier circuit.

FIG. 3 is a block diagram of an MCM that is a power amplification device in the portable communication device according to the first embodiment of the present invention.

FIG. 4 is an amplification F used in the MCM that is the power amplification device in the portable communication device according to the first embodiment of the present invention.
It is a figure explaining the gate direction of FET for ET and temperature compensation.

FIG. 5 is a diagram illustrating gate directions of an amplification FET and a temperature compensation FET used in an MMIC that is a power amplification device in a portable communication device according to a second embodiment of the present invention.

FIG. 6 is an FE with a gate orientation of 0 ° with respect to orientation flats.
It is a characteristic view which shows the temperature dependence of the operating current of FET which T and a gate direction are 90 degrees.

FIG. 7: FE with a gate orientation of 0 ° with respect to orientation flat
It is a characteristic view which shows the gate voltage dependence of transconductance of FET which T and the gate direction are 90 degrees.

FIG. 8 is a characteristic diagram showing the gate voltage dependence of the mutual conductance of the power amplification device in the portable communication device according to the first embodiment of the present invention.

FIG. 9 is a characteristic diagram showing the temperature dependence of the operating current of the power amplification device in the portable communication device according to the first embodiment of the present invention.

FIG. 10 is a block diagram of an MMIC that is a power amplification device in a portable communication device according to a second embodiment of the present invention.

FIG. 11 is a block diagram of a high frequency transmitter in a mobile phone according to a third embodiment of the present invention.

FIG. 12 is a block diagram of a high frequency transmitter in a mobile phone according to a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram of a power amplification device in a conventional mobile phone.

FIG. 14 is a characteristic diagram showing the temperature dependence of the operating current of the power amplification device in the conventional mobile phone.

FIG. 15 is a diagram showing a temperature compensation circuit used in a power amplification device in a conventional mobile phone.

FIG. 16 is a block diagram of a high frequency transmitter in a conventional mobile phone.

[Explanation of symbols]

 1 front-stage amplification FET 2 rear-stage amplification FET 3 input matching circuit 4 interstage matching circuit 5 output matching circuit 6 front-stage drain bias circuit 7 rear-stage drain bias circuit 8A front-stage first gate bias circuit 8B front-stage first 2 gate bias circuit 8C 3rd gate bias circuit in the previous stage 8D 4th gate bias circuit in the previous stage 8a Gate pad 8b Ground pattern 8c First chip resistor 8d Second chip resistor 8e Wiring pattern 9a Gate pad 9b Ground pattern 9c 1st chip resistance 9d 2nd chip resistance 9A 1st gate bias circuit of the latter stage 10A Transmitter amplifier 10B Transmitter amplifier 12 Upconverter 13 Front stage amplifier 14 Isolator 15 RF switch 16 Filter 17 Antenna 21 1 resistance 22 2nd resistance 23 Temperature compensation FET 24 Grounding side capacitor 25 Power supply side capacitor 26 Connection point of 2nd resistance and temperature compensation FET 30 Printed circuit board 31 1st FET 32 2nd FET 33th 3rd FET 34 4th FET 40 GaAs substrate 41 1st FET 42 2nd FET 43 3rd FET 44 4th FET

Claims (6)

[Claims] 1. An amplification FET formed on a compound semiconductor substrate for amplifying input high-frequency power, and a series circuit comprising a resistor and a temperature compensation FET formed on the compound semiconductor substrate, The crystal orientation of the gate of the amplification FET with respect to the compound semiconductor substrate on which the amplification FET is formed and the crystal orientation of the gate of the temperature compensation FET with respect to the compound semiconductor substrate on which the temperature compensation FET is formed The temperature characteristics of the amplifying FET and the temperature characteristics of the temperature compensating FET are set to be opposite to each other, and one end of the series circuit is connected to a voltage power supply and The other end is grounded, and the resistance in the series circuit and the temperature compensation FET
A power amplification device in a portable communication device, wherein a connection point with is connected to the gate of the amplification FET. 2. The amplification FET and the temperature compensation FE
The power amplification device in a portable communication device according to claim 1, wherein T is formed on the same compound semiconductor substrate. 3. The power amplification device in a portable communication device according to claim 1, wherein the transconductance of the amplification FET is higher than the transconductance of the temperature compensation FET. 4. A portable communication device having a two-stage power amplifying device for amplifying input high-frequency power, comprising: a front-stage power amplifying means and a second-stage power constituting the two-stage power amplifying device. At least one power amplification means of the amplification means includes an amplification FET that is formed on the compound semiconductor substrate and amplifies the input high frequency power, and a resistor and a temperature compensation FET that is formed on the compound semiconductor substrate. And a crystallographic orientation of the gate of the amplification FET with respect to the compound semiconductor substrate on which the amplification FET is formed, and the temperature compensation FET of the gate of the temperature compensation FET is formed. The crystal orientation with respect to the compound semiconductor substrate is set so that the temperature characteristics of the amplification FET and the temperature characteristics of the temperature compensation FET are opposite to each other. One end of the series circuit is connected to a voltage power supply, and the other end of the series circuit is grounded. The resistor and the temperature compensation FET in the series circuit are connected to each other.
A portable communication device, wherein a connection point with is connected to the gate of the amplification FET. 5. The amplification FET and the temperature compensation FE
The portable communication device according to claim 4, wherein T is formed on the same compound semiconductor substrate. 6. The portable communication device according to claim 4, wherein the transconductance of the amplification FET is higher than the transconductance of the temperature compensation FET.