JPH0255950B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device constituted by insulated gate transistors, and more particularly to an insulated gate semiconductor device using miniaturized transistors.

[Technical background of the invention and its problems] In the field of semiconductor devices, the miniaturization of elements of MOS type integrated circuits has been remarkable. In particular, efforts are being made to reduce the channel length from the viewpoint of improving the switching speed of MOS transistors. However, as the channel length is reduced, the following problems have arisen in terms of device characteristics.

First, as the channel length decreases, the threshold voltage of the transistor in the short channel region becomes shallower, which is the so-called short channel effect. Specifically, the gate channel length L and the threshold voltage
As shown in the characteristic curve diagram in Figure 6 showing the relationship with Vth, the threshold voltage of the transistor in the short channel region is
Vth decreases rapidly, and the threshold voltage fluctuates significantly due to slight changes in the device manufacturing process. This is because the distance between the source and drain regions becomes shorter.
This is explained by the fact that in the channel region, the influence of the depletion layer generated near the source and drain regions cannot be ignored, and as a result, the gate voltage required to effectively invert the surface of the channel region becomes lower. Generally, the potential of the substrate forming the channel region is equal to or very close to the potential of the source region, so the electric field between the source and drain regions becomes concentrated and strong at the surface of the channel region near the drain region. Therefore, the influence on the reduction of the threshold voltage is also strongest in this part.

Also, as the channel length decreases, the source,
The voltage applied between the drain regions increases the electric field generated in the channel region, which increases the probability that impact ionization will occur due to channel current. Some of the electrons or holes generated in this impact ionization cross the energy barrier between the semiconductor substrate and the gate insulator, jump into the gate insulator, flow out to the gate electrode, and generate a gate current. Some of it gets trapped in the gate insulator.
This changes the operating characteristics of the transistor, such as a change in the threshold voltage of the transistor or a change in channel conductance, which is a major cause of deterioration of device reliability. However, since the electric field between the source and drain regions becomes concentrated and strong in the channel region near the drain region, impact ionization mainly occurs in this region. For this reason, as shown in the cross-sectional view of FIG. ) structure has been developed. That is, in FIG. 7, 80 is, for example, a P-type semiconductor substrate, and an island region in this substrate 80 separated by a field insulating film 81 has N as a source region.
Type impurity diffusion regions 82 and 83 and N type impurity diffusion regions 84 and 85, which become drain regions, are provided separately from each other. Of the N type impurity diffusion regions 82 to 85 constituting the source and drain regions, regions 82 and 84 are N ⁺ type regions having a relatively high impurity concentration, for example, ~10 ²⁰ /
It is about cm ³ . On the other hand, areas 83 and 8
5 is an N ^- type region with relatively low impurity concentration,
Its concentration is, for example, approximately 10 ¹⁸ /cm ³ .
A gate electrode 87 is provided on the substrate 80 between these source and drain regions with a gate insulating film 86 interposed therebetween. An interlayer insulating film 88 is provided over the entire surface, and wiring 90 made of aluminum is provided in this insulating film 88 to connect to the source and drain regions 82 and 84, respectively, through contact holes 89.

In a MOS transistor with such a structure, the portion of the drain region in contact with the channel region is made into an N-type impurity diffusion region 85 with a low impurity concentration, so that part of the voltage applied between the source and drain is transferred to this portion. The electric field concentrated in the channel region near the drain region can be weakened. Therefore, it is possible to improve the fluctuation of the threshold voltage due to the decrease in channel length as described above and the reliability of the device.

However, in a MOS transistor having a structure as shown in FIG. 7, since the source and drain regions in contact with the channel region are formed of low concentration impurity diffusion regions, the resistance value of those portions inevitably becomes high. Therefore, the switching speed of the transistor decreases, causing loss of high speed performance. This phenomenon of increased resistance due to lower concentration in the source and drain regions of the transistor significantly reduces the operating speed, especially when transistors are connected in series over many stages. That is, FIG. 8 shows two enhancement-type N-channel MOS transistors 101 and 102 whose source and drain regions each consist of a high-concentration diffusion region and a low-concentration diffusion region as described above, and a depletion-type N-channel MOS transistor for load. MOS transistor 103
FIG. 2 is a cross-sectional view showing an element structure when a two-input NAND circuit is constructed using the following. In the figure, 11
0 is a P-type semiconductor substrate, 111 and 112 are high-concentration and low-concentration N-type impurity diffusion regions that constitute the source region of one MOS transistor 102;
113 and 114 are this MOS transistor 1
115 is the gate electrode of this MOS transistor 102, 116 and 1 are
Reference numeral 17 indicates high concentration and low concentration N type impurity diffusion regions that constitute the source region of the other MOS transistor 101, and 118 and 119 indicate high concentration and low concentration N type impurity diffusion regions that constitute the drain region of this MOS transistor 101. , 120 is the gate electrode of this MOS transistor 101, 12
1 is an N-type impurity diffusion region which is the source region of the load MOS transistor 103, and 122 is this region.
123 is a channel diffusion region of this MOS transistor 103, and 124 is a gate electrode. and the N-type impurity diffusion region 1
22 is connected to a high potential power supply voltage _VDD , and the impurity diffusion region 111 is connected to a low potential power supply voltage _VSS.The gate electrodes 120 and 115 are connected to an input signal A.
1 and A2 are respectively input, N-type impurity diffusion regions 113 and 116 are commonly connected, and gate electrode 124 and N-type impurity diffusion regions 121 and 1 are connected in common.
18 are commonly connected and from here the above input signal A
1, A2, a logical output signal Yout is taken out.

FIG. 9 shows an equivalent circuit of a two-input NAND circuit having such an element structure. In Figure 9,
The triangular portions of the sources and drains of the MOS transistors 101 and 102 are structured to have low concentration N-type impurity diffusion regions as described above, and the resistance value is high in these portions. These two inputs
In the NAND circuit, a voltage of V _SS or V _DD is input as input signals A1 and A2, for example, corresponding to a logic level of "0" level or "1" level,
Both input signals A1 and A2 are used as the output signal Vout.
A NAND logic signal is output. That is, when normal 5V and 0V are used as the power supply voltages V _DD and V _SS , for example, 5V is applied to the drain region side of the enhancement type MOS transistor 101 whose gate input is the signal A1 via the depletion type MOS transistor 103. voltage is applied,
MOS depending on the logic level of input signals A1 and A2
Transistors 101 and 102 are controlled to be conductive,
When both MOS transistors 101 and 102 are conductive, 0V is output as the output signal Vout,
When either one of the MOS transistors 101 and 102 is non-conductive, the output signal Vout is output.
5V is output. Since both of the MOS transistors 101 and 102 have an LDD structure, each of the source and drain regions has a high resistance value. These resistors are connected in series between the output terminal of the signal Vout and V _SS , and these resistors prevent the discharging operation when discharging Vout from 5V to 0V. Therefore,
The operating speed of this NAND circuit will drop significantly. This speed reduction increases as the number of MOS transistors connected in series between the output terminal of the signal Vout and V _SS increases. This problem occurs not only in circuits that use depletion-type load MOS transistors, but also in circuits that use high-potential power supply voltages.
The same applies to a circuit with a CMOS structure in which a P-channel MOS transistor is provided on the V _DD side.

[Purpose of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor device using miniaturized insulated gate transistors without impairing the characteristics of each transistor. An object of the present invention is to provide an insulated gate semiconductor device that can improve operating speed.

[Summary of the invention] In this invention, the N
A part of the drain region of the channel transistor is composed of a diffusion region with a relatively low impurity concentration, and this N
The source region of a channel transistor is composed only of a diffusion region with a relatively high impurity concentration, and the impurity concentration is compared with each of the drain region and source region of another N-channel transistor connected between this N-channel transistor and a low potential. It is made up of only highly targeted diffusion regions. In other words, we focused on the fact that in miniaturized insulated gate transistors, impact ionization becomes a problem only in the part where a high potential power supply voltage is directly applied to the drain region. By configuring a part of the drain region of the N-channel transistor directly connected to the output terminal, which is the position where the power supply voltage is directly applied, as a diffusion region with a relatively low impurity concentration, the output terminal and the low potential power supply can be connected. The value of the low resistor inserted between the two is significantly reduced, thereby improving the operating speed of the circuit.

[Embodiments of the Invention] Hereinafter, embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an element structure according to an embodiment of an insulated gate semiconductor device according to the present invention.
This invention is implemented in a two-input NAND circuit. In the figure, 10 is a P-type semiconductor substrate.
This substrate 10 is separated by a field insulating film 11, and three island regions 12, 13, and 14 are formed. One of the island regions 12 has a relatively high impurity concentration, and a pair of N-type impurity diffusion regions 15 and 16, which become the source and drain regions of the MOS transistor, are formed separately from each other. A gate electrode 17 is formed on the substrate 10 between these regions 15 and 16 via a gate insulating film (not shown).
is provided. The impurity concentration is relatively high in the island region 13, and the source of the MOS transistor,
A pair of N-type impurity diffusion regions 1 serving as drain regions
8 and 19 are formed separately from each other, and one N-type impurity diffusion region 1 which becomes a drain region
On the side of the channel region 9, an N-type impurity diffusion region 20, which is part of the drain region and has a relatively low impurity concentration, is formed so as to be in contact with this region 19. A gate electrode 21 is provided on the substrate 10 between the regions 18 and 20 via a gate insulating film (not shown). Further, the remaining island region 14 has a relatively high impurity concentration,
A pair of N-type impurity diffusion regions 22 and 23, which become the source and drain regions of the MOS transistor, are formed separated from each other. In the substrate 10 between the two regions 22 and 23, an impurity diffusion region 24 of the same conductivity type as the substrate, that is, P type, is formed. Further, a gate electrode 25 is provided on the substrate 10 between the regions 22 and 23 via a gate insulating film (not shown).
is provided. Here, among the N-type impurity diffusion regions, the region where the impurity concentration is relatively high has a concentration of, for example, about 10 ²⁰ /cm ³ , and the region where the impurity concentration is relatively low has a concentration of, for example, about 10 20 /cm 3 . ~ ¹⁰¹⁸ / ^cm3 .

The N-type impurity diffusion region 23 is connected to a high-potential power supply voltage _VDD , and the N-type impurity diffusion region 15 is connected to a low-potential power supply voltage _VSS , and the gate electrodes 21 and 17 receive input signals A1 and A2. The N-type impurity diffusion regions 16 and 18 are commonly connected, and the gate electrode 25 and the N-type impurity diffusion regions 23 and 19 are commonly connected to output a logic output signal corresponding to the input signals A1 and A2.
Vout is now being taken out.

FIG. 2 is an equivalent circuit diagram of the semiconductor device of the above embodiment. In the figure, a MOS transistor 31 is formed in the island region 13 and is of an enhancement type whose gate is supplied with a signal A1.
The MOS transistor 32 is formed in the island region 12 and is an enhancement type transistor whose gate is supplied with the signal A2. Furthermore, the MOS transistor 33 is formed in the island region 14 and is a load transistor whose gate is connected to the source. It is a depression type.

In such a two-input NAND circuit, only the drain of the N-channel MOS transistor 31, which is directly connected to the terminal of the output signal Vout, is connected to the high concentration and low concentration as shown by the circle in the figure. It has a structure with an N-type impurity diffusion region,
The resistance value is high only in this part. Therefore, the resistor connected between the output terminal of the signal Vout and V _SS becomes one of these resistors, and Vout is changed from 5V to
The discharge speed when discharging to 0V can be made sufficiently faster than before. Therefore, high-speed operation can be achieved.

In addition, regarding the MOS transistor 31 directly connected to the output signal Vout, where the deterioration of characteristics due to impact ionization near the drain region due to transistor miniaturization is the most problematic,
Since the drain region has an LDD structure, it is possible to prevent a decrease in reliability due to the generation of hot carriers.

FIG. 3 is an equivalent circuit diagram when the device of the above embodiment is implemented in a 3-output NAND circuit. In the circuit according to this embodiment, the MOS transistor 3 whose gate is supplied with the signal A2 in the circuit of FIG.
2 and V _SS , the source and drain regions are MOS
Like the transistor 32, the enhancement type N transistor is composed of only a high concentration N type impurity diffusion region.
Insert the channel MOS transistor 34 and
Input signal A3 to the gate of MOS transistor 34
It is designed to supply In this case as well, the only resistor connected between the output terminal of the signal Vout and V _SS is the drain portion of the MOS transistor 31, so that the discharge speed when discharging Vout from 5V to 0V is sufficiently faster than before. This makes it possible to achieve faster operation. Furthermore, regarding the deterioration of characteristics due to impact ionization near the drain region due to miniaturization of transistors, this problem is greatest in the MOS transistor 3 directly connected to the output signal Vout.
Regarding No. 1, since its drain region has an LDD structure, it is possible to prevent a decrease in reliability due to the generation of hot carriers.

FIG. 4 is a sectional view showing the element structure of another embodiment of the insulated gate type semiconductor device according to the present invention, in which the present invention is implemented in a two-input CMOS-NAND circuit. A P-type semiconductor substrate 40 is also used in the device of this embodiment, and an N-well region 41 is formed in this substrate 40. P-type substrate 40
Two island regions 43 and 44 separated by a field insulating film 42 are formed. One of the island regions 43 has a relatively high impurity concentration, and a pair of N-type impurity diffusion regions 45 and 46 which become the source and drain regions of the MOS transistor.
are formed separately from each other. These areas 4
A gate electrode 47 is provided on the substrate 40 between 5 and 46 via a gate insulating film (not shown). Another island region 44 has a relatively high impurity concentration, and a pair of N-type impurity diffusion regions 4 that become the source and drain regions of the MOS transistor.
8, 49 and the substrate 40 are separately formed.
On the channel region side of the type impurity diffusion region 49, an N type impurity diffusion region 51, which is part of the drain region and has a relatively low impurity concentration, is formed so as to be in contact with this region 49. And the above area 4
A gate electrode 52 is provided on the substrate 40 between 8 and 51 via a gate insulating film (not shown). In this case as well, the region where the impurity concentration is relatively high among the N-type impurity diffusion regions is set at a concentration of, for example, approximately 10 ²⁰ /cm ³ , and the region where the impurity concentration is relatively low is set at that concentration. The concentration is, for example, approximately 10 ¹⁸ /cm ³ .

Two island regions 53 and 54 separated by a field insulating film 42 are formed in the N-well region 41 . A pair of P-type impurity diffusion regions 55 and 56 that become the source and drain regions of the MOS transistor and a P-type impurity diffusion region 57 for contacting the N-well region 41 are separated from one of the island regions 53. It is formed as follows. N-well region 4 between the regions 55 and 56
A gate electrode 58 is provided on the gate electrode 1 via a gate insulating film (not shown). Another island area 5
4 also has a pair of P-type impurity diffusion regions 59 and 6 which become the source and drain regions of the MOS transistor.
0 are formed separately from each other. A gate electrode 61 is placed on the N-well region 41 between the regions 59 and 60 via a gate insulating film (not shown).
is provided.

The P-type impurity diffusion regions 61, 55 and 57
are connected to a high-potential power supply voltage V _DD , and N-type impurity diffusion regions 45 and 50 are connected to a low-potential power supply voltage V _SS , respectively. The input signal A2 is input to each of
Furthermore, the N-type insulating diffusion regions 46 and 48 are commonly connected, and the N-type impurity diffusion region 49 and the P-type impurity diffusion regions 56 and 60 are commonly connected, from which a logic output signal Vout corresponding to the input signals A1 and A2 is output. taken out.

FIG. 5 is an equivalent circuit diagram of the semiconductor device of the above embodiment. In the figure, a MOS transistor 71 is formed in the island region 44 and is an enhancement type N-channel type whose gate is supplied with an input signal A1, and a MOS transistor 72 is formed in the island region 43 and has a gate supplied with an input signal A2. Further, the MOS transistor 73 is formed in the island region 54 and is an enhancement type P-channel transistor whose gate is supplied with the input signal A1. It is formed in the island region 53 and is of an enhancement type and P channel whose gate is supplied with an input signal A2.

In such a two-input NAND circuit, only the drain of the N-channel MOS transistor 71, which is directly connected to the terminal of the output signal Vout, is connected to the high concentration and low concentration as shown by the circle in the figure. The structure is made up of an N-type impurity diffusion region, and the resistance value is high only in this part. Therefore, in this embodiment as well, the output terminal of the signal Vout and
The resistor connected between V _SS becomes one of these resistors, and the discharge speed when discharging Vout from 5 V to 0 V can be made sufficiently faster than before, achieving faster operation. be able to.

In addition, regarding deterioration of characteristics due to impact ionization near the drain region due to miniaturization of transistors, the drain region of the MOS transistor 71, which is directly connected to the output signal Vout and is the most problematic, has an LDD structure. Deterioration in reliability due to the occurrence of hot carriers can be prevented.

Note that also in the case of this embodiment device, the signal Vout
As the number of stages of N-channel MOS transistors between the output terminal of and V _SS increases, the effect becomes larger than in the past.

[Effects of the Invention] As explained above, according to the present invention, it is possible to improve the operating speed of a semiconductor device using miniaturized insulated gate transistors without impairing the characteristics of each transistor. An insulated gate semiconductor device can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an element structure according to an embodiment of an insulated gate semiconductor device according to the present invention, and FIG.
The figure is an equivalent circuit diagram of the semiconductor device of the above embodiment, FIG. 3 is an equivalent circuit diagram of the device of the above embodiment implemented in a 3-input NAND circuit, and FIG. 4 is an equivalent circuit diagram of the insulated gate semiconductor device according to the present invention. 5 is an equivalent circuit diagram thereof, FIG. 6 is a characteristic curve diagram showing the relationship between gate channel length and threshold voltage in a MOS transistor, and FIG.
The figure is a cross-sectional view of a MOS transistor with an LDD structure, FIG. 8 is a cross-sectional view showing the element structure of a conventional NAND circuit, and FIG. 9 is an equivalent circuit thereof. 10...P-type semiconductor substrate, 15, 16, 1
8, 19, 22, 23...High concentration N type diffusion region, 20...Low concentration N type diffusion region, 17, 2
1, 25...gate electrode.

Claims (1)

[Scope of Claims] 1. In an insulated gate semiconductor device that includes a plurality of insulated gate transistors and outputs a desired logical value as an output signal from an output terminal in response to an input signal, an insulated gate transistor that is directly connected to the output terminal A part of the drain region of the N-channel transistor is configured with a diffusion region with a relatively low impurity concentration, a source region of this N-channel transistor is configured with a diffusion region with a relatively high impurity concentration, and a low potential is connected to the N-channel transistor. 1. An insulated gate type semiconductor device characterized in that each of the drain region and source region of another N-channel transistor connected therebetween is composed of only diffusion regions having a relatively high impurity concentration. 2. The insulated gate semiconductor device according to claim 1, wherein an N-channel load transistor is inserted between the output terminal and a high potential. 3. The insulated gate semiconductor device according to claim 1, wherein a P-channel transistor whose gate is supplied with an input signal is inserted between the output terminal and the high potential.