JPH06275787A - Cmosfet circuit device - Google Patents

Abstract

PURPOSE:To improve the ESD breakdown strength of an analog switch circuit by separating the p/n channel-type transistor of a switch part and the n/p type channel-type transistor of a control part from each other. CONSTITUTION:The p<+>-type source/drain regions 36 and 38 of the transistor 14 of a switch part are arranged separately from the n<+>-type source/drain region 26 and 28 of the transistor 12 of a control part. Therefore, A latent resistance attributed to a substrate 20 exists between the p<+>-type source/drain region 36 and 38 and the n<+>-type source and drain regions 26 ad 28. Moreover, not only the n<+>-type guard ring 18 of the transistor 14 but also the n<+>-type guard ring 17 exists between the regions 36 and 38 and 26 and 28. Therefore the surge current by plus surge is hindered from forming a path between the region 36 and 38 and the regions 26 and 28, as a result, the ESD breakdown strength of an analog switch circuit can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a CMOSFET circuit device having an improved ESD withstand voltage.

[0002]

2. Description of the Related Art It is known that a semiconductor device is electrostatically destroyed by static electricity charged on a human body or the like. So-called ESD
(Electro static discharge) causes deterioration of the characteristics of the semiconductor device, junction breakdown, oxide film breakdown, and the like. In particular, with the miniaturization of elements, the electrostatic breakdown resistance of the CMOSFET circuit device tends to decrease.

Particularly in the analog switch circuit,
The electric potential of the switch portion composed of the CMOSFET is not fixed but depends on the electric potential of the input signal to the switch portion. Therefore, there are few places connected to the power supply potential VDD and the ground potential VSS for absorbing the surge (the impact of a large current due to static electricity, etc.) coming from the input / output pad, and the surge current is hard to escape. There is. As a result, the surge current that has entered the switch section concentrates on the shortest path in the circuit, which causes the breakdown of the pn junction and the like, which causes a reduction in the ESD breakdown voltage.

[0004]

As described above, the analog switch circuit generally has a drawback that the ESD withstand voltage tends to be lower than that of other CMOS circuits (logic circuits and the like). Accordingly, the present invention provides a CMOSFET circuit device,
In particular, the object is to improve the ESD withstand voltage of the analog switch circuit.

[0005]

A CMOSF according to the present invention
The ET circuit device includes a switch unit having an n-channel type first transistor surrounded by a p-type guard ring and a p-channel type fourth transistor surrounded by an n-type guard ring, and sandwiched between the first and fourth transistors. And a control unit having an n-channel second transistor surrounded by a p-type guard ring and a p-channel third transistor surrounded by an n-type guard ring, the first transistor Are arranged adjacent to the second transistor, and the fourth transistor is arranged adjacent to the third transistor.

[0006]

Since the p / n-channel type transistor of the switch section and the n / p-channel type transistor of the control section are separated from each other, the surge applied to the switch section will surely flow into the guard ring of the transistor. .

[0007]

1 is a diagram showing an embodiment of a CMOSFET circuit device according to the present invention. The circuit device according to the present invention is
As shown in the schematic plan view of FIG. 1A, two circuits, that is, a first analog switch circuit (transistors 11 to 1)
4) and the second analog switch circuit (transistor 11
a to 14a). In FIG. 1A, the gate electrode of each transistor is not shown. Since the two analog switch circuits are substantially equivalent, in the following, the first
The circuits (transistors 11 to 14) will be described. Figure 1
(B) is an enlarged sectional view showing the transistors 11 to 14 of the first circuit.

An n-channel type transistor 11 and a p-channel type transistor 14 located on both sides of the first analog switch circuit form a pair to form a switch section. Also,
The n-channel type transistor 12 and the p-channel type transistor 13 located in the center form a pair to form a control section.

The n-channel type transistor 11 has n + type source / drain regions 22 and 24 formed in a p type well 40 in the n type substrate 10 and a gate electrode 23 disposed on the substrate 10. Have. The transistor 11 is surrounded by a p + type guard ring 15 formed in the p type well 40.

The p-channel transistor 14 is a p + -type source / drain region 3 formed in the n-type substrate 10.
6 and 38, and the gate electrode 37 disposed on the substrate 10. The transistor 14 is surrounded by an n + type guard ring 18 formed in the n type substrate 10.

The n-channel type transistor 12 is formed in an n-type well 40 shared with the transistor 11.
It has + type source / drain regions 26 and 28 and a gate electrode 27 provided on the substrate 10. Transistor 1
2 is surrounded by a p @ + type guard ring 16 formed in a p type well 40.

The p-channel type transistor 13 is a p + type source / drain region 3 formed in an n type substrate 10.
2, 34 and a gate electrode 33 provided on the substrate 10. The transistor 13 is surrounded by an n + type guard ring 17 formed in the n type substrate 10.

Guard ring 1 of transistors 14 and 13
The power supply potential VDD is connected to the transistors 8 and 17 and one source / drain region 34 of the transistor 13. The ground potential VSS is connected to the guard ring 16 of the transistor 12 and one of the source / drain regions 26.

One input / output pad O / I is connected to one source / drain region 22 of the transistor 11 and one source / drain region 36 of the transistor 14. The other source / drain region 2 of the transistor 11
4 and the other source / drain region 3 of the transistor 14
The other input / output pad I / O is connected to 8 and.

If an n-type substrate is used, the positive surge that comes in through the p + type source / drain regions 36, 38 of the p-channel transistor 14 of the switch section is a problem. For example, in FIG. 1B, assume that a positive surge due to static electricity is applied to the input / output pad O / I on the right side of the drawing. This surge current normally forms a path in the forward direction of the pn junction. Therefore, most of the same current flows from the p + type source / drain region 36 to the n + type guard rings 18 and 17 of the transistors 14 and 13,
Finally, it is absorbed by the VDD power supply. Here, the n + type source of the transistor 12 of the control unit which becomes the lowest potential /
Since the drain regions 26 and 28 are isolated from the p + type source / drain region 24, the surge current is generated in the region 2
It does not flow to 6, 28. Therefore, the surge current does not destroy the pn junction between the substrate 10 and the well 40.

In other words, in the device of this embodiment, the p-channel type transistor 14 of the switch section is the n-type of the control section.
It is necessary to be arranged apart from the channel type transistor 12. That is, p of the transistor 14 of the switch section
The + type source / drain regions 36 and 38 are the n + type source / drain regions 2 of the transistor 12 in the control section.
It is arranged away from 6, 28 (which has the lowest potential). Therefore, the p + type source / drain regions 36 and 38 and the n +
The substrate 1 is located between the source / drain regions 26 and 28.
A large resistance of 0 is latent. Area 3
Between transistor 6 and 38 and regions 26 and 28, transistor 1
In addition to the n + type guard ring 18 of No. 4, the n + type guard ring 17 of the transistor 13 is present.
Therefore, the surge current due to the positive surge is
6, 38 and the regions 26, 28 are prevented from forming a path, resulting in the ES of the analog switch circuit.
The D breakdown voltage is improved.

In order to facilitate understanding of the present invention, FIG. 2 shows a case in which the transistors 11 and 14 of the switch section are arranged so that their positions are opposite to those of the device of the embodiment shown in FIG. 1 with respect to the control section. That is, the p-channel transistor 14 of the switch unit is provided adjacent to the n-channel transistor 12 of the control unit, and the n-channel transistor 11 of the switch unit is provided adjacent to the p-channel transistor 13 of the control unit.

FIG. 2A is a schematic plan view corresponding to FIG. 1A, and FIG. 2B shows the transistors 14 and 12,
It is sectional drawing which expands and shows 13. 2, parts corresponding to the parts of the device of the present invention shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Since the n-channel transistor 12 of the control unit is separated from the n-channel transistor 11 of the switch unit,
It is formed in the p-type well 25 provided exclusively.

In the device having such a structure, for example, assume that a positive surge due to static electricity is applied to the input / output pad I / O on the right side in FIG. The surge current is usually pn
In order to form a path in the forward direction of the junction, it is desirable that the same current flow out from the p + type source / drain region 38 to the n + type guard ring 18 or the n type substrate 10. However, here, the transistor 1 of the control section
Since the n + -type source / drain region 26 (having the lowest potential) of 2 is adjacent to the p + -type source / drain region 38, the surge current is as shown by an arrow A in FIG. It concentrates and flows toward the area 38. Since the region 38 and the region 26 are close to each other, the value of the current flowing between them becomes very large, which is p between the substrate 10 and the well 25.
Destroy the n-junction. That is, due to such a phenomenon, the ESD withstand voltage of the analog switch circuit is lowered. According to the apparatus of the embodiment shown in FIG. 1, such a phenomenon can be avoided.

FIG. 3 is a sectional view showing another embodiment of the CMOSFET circuit device according to the present invention. In FIG. 3, portions corresponding to those of the apparatus of the embodiment shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, a p-type substrate 50 is used in which an n-type well 52 is formed. The n-type well 52 is shared by the p-channel type transistor 14 of the switch section and the p-channel type transistor 13 of the control section. The other points are similar to those of the embodiment shown in FIG.

If a p-type substrate is used, the negative surge that comes in through the n + type source / drain regions 22, 24 of the n-channel transistor 11 of the switch part is a problem. In this regard, in the embodiment shown in FIG. 3, the n + type source / drain regions 22 and 24 are formed.
And the p + -type source / drain regions 32 and 34 of the p-channel transistor 13 of the control unit are separated from each other, the negative surge that comes in through the source / drain regions 22 and 24 is 1
It flows into the p + type guard rings 15 and 16 of 1 and 12.
That is, since a large surge current that reaches the n + type source / drain regions 36 and 38 of the transistor 13 does not flow, the pn junction between the substrate 50 and the well 52 is not destroyed, and the analog switch circuit The ESD breakdown voltage is improved.

[0023]

According to the present invention, since the p / n-channel type transistor of the switch section and the n / p-channel type transistor of the control section are separated from each other, the surge applied to the switch section is protected by the transistor guard. It surely flows into the ring, and as a result, the ESD withstand voltage of the analog switch circuit is improved. Further, since the transistors of the same conductive channel type are arranged in the switch section and the control section, it is possible to share the well in the switch section and the control section. Therefore, the manufacturing process is simplified and the breakdown voltage of the device is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a CMOSFET circuit device according to the present invention.

FIG. 2 is a diagram showing an apparatus in which the arrangement of the apparatus shown in FIG. 1 is modified to understand the present invention.

FIG. 3 is a diagram showing another embodiment of the CMOSFET circuit device according to the present invention.

[Explanation of symbols]

11 ... p-channel type transistor of switch part, 12 ...
N-channel transistor of control section, 13 ... p-channel transistor of control section, 14 ... n-channel transistor 12 of switch section.

Claims (1)

[Claims] 1. An n-channel type first transistor surrounded by a p-type guard ring and a p-type transistor surrounded by an n-type guard ring.
A switch unit having a channel-type fourth transistor; and a switch unit sandwiched between the first and fourth transistors,
a control unit having an n-channel type second transistor surrounded by a p-type guard ring and a p-channel type third transistor surrounded by an n-type guard ring, wherein the first transistor serves as the second transistor. A CMOSFET circuit device disposed adjacent to the fourth transistor, wherein the fourth transistor is disposed adjacent to the third transistor.