JP2007535031A - State retention in data processing systems - Google Patents

Abstract

The power consumption can be reduced using power gating, in which case power is removed from the circuit block or part of the circuit block to reduce leakage current. In one embodiment, an improved state retention flip-flop is used that can retain state when power is removed or partially removed from the circuit. In other embodiments, an improved state holding buffer is used that is capable of holding state when power is removed or partially removed from the circuit. State holding flip-flops and buffers can be used to enable state holding while reducing leakage current. Also disclosed are various methods for reducing power and holding state using, for example, state holding flip-flops and buffers. For example, software, hardware, or a combination of software and hardware may be used to enter deep sleep or idle mode while maintaining state.

Description

  The present invention relates generally to data processing systems and, more particularly, to state retention within a data processing system.

  Low power consumption is becoming increasingly important in data processing systems due to, for example, widespread use of mobile and handheld applications. For example, in the case of handheld devices, battery life is a very important parameter. Handheld devices are typically off for a significant amount of time (eg, in idle or deep sleep mode) and consume only leakage power. Therefore, the reduction of leakage current is becoming an increasingly important factor in extending battery life.

  One way to reduce the leakage current of the device is to increase the threshold voltage. However, simply increasing the threshold voltage of the device may produce undesirable results such as sluggish device movement and limited circuit performance.

  Another way to reduce leakage current is to power gate, i.e. disconnect power into a block. However, in doing so, the state of the circuit block is lost. However, in many circuit blocks, state retention is necessary to prevent the loss of important information and to enable proper circuit operation and performance.

Accordingly, there is a need for a circuit and method that can assist in reducing leakage power and extending battery life with improved circuits and methods for state retention, for example, during idle or deep sleep modes.

The present invention is illustrated by way of example and not by way of limitation with the accompanying figures. In the figures, like reference numerals indicate like elements.
Those skilled in the art will recognize that the elements of the figures are illustrated in a simple and clear manner and are not necessarily drawn to scale. For example, some of the elements in the figures may have exaggerated dimensions compared to other elements to help improve understanding of embodiments of the present invention.

  As used herein, the term “bus” refers to a plurality of signals or conductors that can be used to convey one or more of various types of information, such as data, address, control, or status. The conductors described herein are single conductors, multiple conductors, unidirectional conductors, or bidirectional conductors, which are illustrated or described. However, in different embodiments, the conductor implementation may also be different. For example, separate unidirectional conductors may be used rather than bidirectional conductors, and vice versa. Also, a plurality of conductors may be replaced with a single conductor that transmits a large number of signals in series or in a time division multiplex manner. Similarly, a single conductor carrying multiple signals can be separated into a variety of different conductors carrying portions of these signals. Thus, there are many options for conveying the signal.

  The terms “assert” or “set” and “negate” (or “deassert” or “clear”) refer to a signal, a status bit, or similar device, respectively, in its logically true or logically false state. It is used when processing. If the logically true state is logical level 1, the logically false state is logical level zero. Also, if the logically true state is logical level zero, the logically false state is logical level 1. Thus, each signal described herein may be configured as positive or negative logic, where negative logic is indicated by a bar above the signal name or by an asterisk (*) following the signal name. obtain. In the case of a negative logic signal, the signal is active low, where a logically true state corresponds to a logic level of zero. In the case of a positive logic signal, the signal is active high, where the logically true state corresponds to a logic level of 1. Note that any of the signals described herein can be configured as either negative or positive logic signals. Therefore, a signal described as a positive logic signal can be realized as a negative logic signal, and a signal described as a negative logic signal can be realized as a positive logic signal.

  As will be discussed later in this specification, power consumption may be reduced using power gating, in which case power is removed from the circuit block or a portion of the circuit block to reduce leakage current. . In one embodiment, an improved state retention flip-flop is used that can retain state when power is removed or partially removed from the circuit. Other embodiments use an improved state holding buffer that is capable of holding state when power is removed or partially removed from the circuit. As will be described later, the state holding flip-flop and the buffer enable the state holding with the minimum additional circuit while reducing the leakage current. Also described herein are various methods for reducing power and holding state, for example, using state holding flip-flops and buffers. For example, in one embodiment, a hardware method is used to enter deep sleep mode and maintain state, while in other embodiments, a combination of hardware and software is used to enter deep sleep mode. Keep state.

  FIG. 1 illustrates a data processing system 100 according to one embodiment of the present invention. The data processing system 100 includes a voltage regulator 102, a transistor 104, a clock controller 116, a state holding controller 118, a sleep area function circuit 124, and an operation area function circuit 128. The voltage regulator 102 provides continuous VDD (VDDC) 130 and VDD 132, where VDDC 130 and VDD 132 are connected through transistor 104. That is, the first current electrode of the transistor 104 is connected to the VDDC 130, and the second current electrode of the transistor 104 is connected to the VDD 132. The control electrode of transistor 104 is connected to receive a power gate control signal (VDD control 110) from state retention controller 118. In the illustrated embodiment, transistor 104 is a PMOS transistor. The VDDC 130 is provided to the state holding controller 118, the clock controller 116, the sleep area function circuit 124, and the operation area function circuit 128. The VDD 132 is provided to the sleep area function circuit 124. Clock controller 116 receives reference clock refclk 112, provides sleep domain clock sclk 122 to sleep domain functional circuit 124, provides operational domain clock rclk 126 to operational domain functional circuit 128, and status via bi-directional clk control signal 134. Communication with the holding controller 118 is performed. The state holding controller 118 receives the power gate control request (PGreq 114) and provides the power gate control display signal (PG 120) to the sleep region function circuit 124. The data processing system 100 can all be located on the same integrated circuit, or alternatively, the data processing system 100 can be located on any number of integrated circuits, or both on integrated circuit elements and individual circuit elements. Note that it can be implemented. The data processing system 100 may be any type of data processing system such as a microprocessor or a digital signal processor, or may be any type of information processing system. It should also be noted that in the illustrated embodiment of data processing system 100, signals such as VDD control 110, PG 120, and PG req 114 are described as positive logic signals.

  In operation, data processing system 100 includes VDDC 130 (which may also be referred to as a continuous power supply signal) and VDD 132 (which may also be referred to as a gated power supply signal) that provide power to various portions of data processing system 100. ) Is included. In the illustrated embodiment, as is known in the art, VDDC 130 is generated by voltage regulator 102, and therefore VDDC 130 is a power signal that can be regulated. When VDD 132 is connected to VDDC 130 (via transistor 104 if VDD control 110 is at logic level 0), VDD 132 is substantially the same as VDDC 130, both powering multiple portions of data processing system 100. I will provide a. If VDD control 110 is at logic level 1, VDD 132 is disconnected from VDDC 130, and only VDDC 130 provides power to multiple portions of data processing system 100, thus providing power gate control for VDD 132 (ie, VDD 132). To remove power to those parts of the circuit connected to). In other embodiments, depending on VDD control 110, both VDDC 130 and VDD 132 provide power to data processing system 100, or differ such that VDDC 130 rather than VDD 132 provides power to data processing system 100. Note that a circuit may be used to implement the function of transistor 104. For example, other switching elements, gate circuits, or any combination of elements may be used.

  In the illustrated embodiment, the data processing system 100 includes both a sleep domain functional circuit 124 and an operational domain functional circuit 128. The sleep region functional circuit 124 includes a circuit that can remove the clock when the data processing system 100 is in a low power mode such as when in the deep sleep mode or the idle mode. During those times when the clock (eg, SCLK 122) is off, power may also be removed from the circuit site to help reduce leakage current. For example, in the illustrated embodiment, the sleep domain functional circuit receives both VDDC 130 and VDD 132, and in this case, during normal or maximum power operation, VDD control 110 is a state holding controller to connect VDD 132 to VDDC 130. Set to logic level 0 by 118. Thus, during normal or maximum power operation, VDDC 130 and VDD 132 both provide power to sleep region circuit 124. However, during low power mode (eg, with sclk 122 turned off), VDD control 110 can be set to logic level 1 to disconnect VDD 132 from VDDC 130 and gate VDD 132 off. . In this case, only the part of the sleep region functional circuit 124 (for example, the part holding the state information) is supplied with power by the VDDC 130, while the remaining part connected to the VDD 132 is cut off. As described below, sleep domain functional circuit 124 can include improved flip-flops and buffers that can be used in combination with VDDC 130 to maintain state in sleep domain functional circuit 124.

  The operation region function circuit 128 includes a circuit that continuously receives a clock (for example, rclk 126) and power (VDDC 130) because the deep sleep mode cannot be entered. This circuit may include, for example, a real-time clock that needs to be continuously powered, or (by periodically activating the data processing system 100 to check for activity such as calls or messages, for example. Such as deep sleep modules, interrupt buffers (eg, detecting activity such as key presses), and other blocks that provide important functions that should not be monitored or turned off by the data processing system 100, etc. Other circuits may be included. This circuit may thus include non-state holding devices such as non-state holding flip-flops and buffers (which can now operate as normal flip-flops and buffers as is known in the art). In one embodiment, rclk 126 is a continuous clock that does not turn off during the low power mode. In one embodiment, rclk 126 is a slower clock than sclk 122 (in this case, rclk 126 may be a 32 kHz clock, for example, and sclk 122 may be a 13 MHz clock, for example). Thus, unlike sclk 122, which can be turned on or off, rclk 126 is not normally turned off. Since the active domain functional circuit 128 is continuously operating, it is continuously powered and therefore receives only VDDC 130, which is the portion of the sleep domain functional circuit 124 that receives VDD 132. This is because the gate is not controlled.

  Although FIG. 1 shows that there are two separate functional circuit blocks, it should be understood that the data processing system 100 may include any number of sleep domain circuit ranges and operational domain circuit ranges. . For example, in one embodiment, the sleep domain circuit and the operational domain circuit are not physically separate blocks, but instead are integrated with each other and receive sclk 122, rclk 126, VDD 130, and VDDC 132 as needed. It is also noted that the circuitry within sleep domain functional circuit 124 and operational domain functional circuit 128 may include any type of circuit that performs any type of function as required by data processing system 100. I want. Also, in other embodiments, data processing system 100 may include any number and type of power domain circuits (in addition to sleep and operating domain functional circuits). Accordingly, the data processing system 100 can be configured in a variety of different ways for a variety of different applications. The functional circuitry of the data processing system 100 will therefore not be described in more detail herein, except to the extent necessary to describe the operation of the state retention site.

  The clock controller 116 generates sclk 122 and rclk 126 based on refclk 112 as necessary. In one embodiment, refclk 112 is generated by a crystal oscillator that may be located on an integrated circuit that is the same as data processing system 100 or external to data processing system 100. Thus, based on control from the state retention controller 118 (eg, via the clk control signal 134) and control information, if any, from other power management modules (not shown), the clock controller 116 can control the sclk 122. It can be turned off or the sclk 122 and rclk 126 can be modified as needed. Note that the clock controller 116 can receive the VDDC 130 and continuously control the sclk 122 and rclk 126 as needed, even during the low power mode.

  The state retention controller 118 may be used to ensure that state is properly retained when entering a low power mode such as deep sleep mode or idle mode. For example, in the illustrated embodiment, state retention controller 118 receives PGreq 114. This request may be a signal generated from any other circuit in the data processing system 100 that indicates when power gating is required to a power management module (not shown) or state keeping controller 118. . The PGreq 114 may correspond to a value (eg, a bit) stored in a memory that can be controlled by software running on the data processing system 100. As another option, PGreq 114 may receive from a source external to data processing system 100. In response to receiving PGreq 114, state retention controller 118 may provide a clk control signal to clock controller 116 to enter a low power mode in which power is gated to the sleep region functional circuit 124 portion and turned off. 134 indicates that the sclk 122 is to be blocked. In addition, the state holding controller 118 indicates to the sleep region function circuit 124 that power gate control is scheduled to be performed via the PG 120. Accordingly, in one embodiment, the state keeping controller 118 may determine that the sclk 122 will be switched off in response to receiving an acknowledgment from the clock controller 116 that the sclk 122 has been turned off. PG120 is asserted, thus powering off the sleep region functional circuit 124, and setting VDD control 110 to logic level 1 and VDD132 from VDDC130. Can be separated. The operations of the clock controller 116 and the state holding controller 118 will be described in more detail later with reference to the timing diagrams of FIGS. 11 to 12 and the flowchart of FIG.

  FIG. 2 illustrates one embodiment of a state-retention flip-flop 200 (which may also be referred to as a state-retentive flip-flop 200). In the illustrated embodiment, flip-flop 200 is a master-slave flip-flop, which includes a master unit 202 connected to a slave unit 204. The flip-flop 200 includes a switch 208 having a first terminal connected to receive the input D and a second terminal connected to the first terminal of the switch 210 and the input to the inverter 214. The switch 208 has a first control terminal that receives “e” and a second control terminal that receives “eb” (inversion of “e”). Switch 210 has a second terminal connected to the output of inverter 212, a first control terminal for receiving “f”, and a second terminal for receiving “fb” (inversion of “f”). The output of the inverter 214 and the input of the inverter 212 are connected to the first terminal of the switch 216. The first control terminal of the switch 216 receives “g”, and the second control terminal of the switch 216 receives “gb” (inversion of “g”). The second terminal of the switch 216 is connected to the first terminal of the switch 218 and the input of the inverter 222. The first control terminal of the switch 218 receives “h”, and the second control terminal of the switch 218 receives “hb” (inversion of “h”). A second terminal of the switch 218 is connected to the output of the inverter 220. The input of inverter 220 is connected to the output of inverter 222 which provides output Q. Accordingly, the master 202 includes at least one circuit element (eg, inverter 214) and the slave 204 includes at least one circuit element (eg, inverter 222), which are input to the flip-flop 200. And in series with output nodes (eg, corresponding to D and Q, respectively). That is, at least one circuit element of each of the master 202 and the slave 204 is in the data path from the input to the output of the flip-flop 200.

  The flip-flop 200 receives sclk (sclk 122, etc.), PG signal (PG120, etc.), and VDDC (VDDC 130, etc.). In one embodiment, e, eb, f, fb, g, gb, h, And a switch controller 206 that provides hb. In other embodiments, the switch controller 206 provides e, f, g, and h, and eb, fb, gb, and hb provide e, f, g, and g, respectively, via an inverter. Can be obtained respectively. Inverters 212 and 214 receive VDD1, and inverters 222 and 220 receive VDD2. The master unit 202 includes a switch 210 and inverters 212 and 214, and the slave unit 204 includes a switch 218 and inverters 220 and 222.

  Note that a switch may also be referred to as a transmission gate or a pass gate. When the switch is on or closed (ie, the pass gate is enabled), the first and second terminals of the switch are connected to each other, so that the value at one of the terminals is connected to the other of the terminals. Passed. When the switch is off or open (ie, the pass gate is disabled), the first and second terminals of the switch are disconnected from each other, and thus the value at one of the terminals is not passed to the other. In the illustrated embodiment of FIG. 2, the switch is turned on by asserting e, f, g, and h (thus deasserting eb, fb, gb, and hb, respectively), and e , F, g, and h are deasserted (thus asserting eb, fb, gb, and hb, respectively). Thus, in one embodiment, a switch state of a switch means that the switch is on or off (ie, closed or open, respectively), so that the first switch state is that the switch is on. Note that it means being or closed, and the second switch state may mean that the switch is off or open, or vice versa.

  In operation, flip-flop 200 receives input D and provides the value of D as output Q. For example, the operation of flip-flop 200 will first be described with reference to FIGS. 3 and 6, where it is assumed that flip-flop 200 is a positive edge flip-flop (relative to sclk). As illustrated in the table of FIG. 6, when the flip-flop 200 is known to be a positive edge flip-flop, VDD1 (in the master unit 202) is connected to VDD (VDD132 etc.) and (in the slave unit 204) ) VDD2 is connected to VDDC (VDDC130 etc.). Next, in FIG. 3, during normal operation, if PG is deasserted (ie, set to 0), both VDD1 and VDD2 provide power to the inverter because of normal operation Because VDD is connected to VDDC (eg, via transistor 104), so VDD is approximately equal to VDDC. Thus, when PG is deasserted, flip-flop 200 operates as a normal positive edge flip-flop. That is, when sclk is 0, switches 208 and 218 are on and switches 210 and 216 are off, so that the value of D passes through switch 208 via inverter 214 and switches 216 To the first terminal. However, since switch 216 is off, this value is not sent to the input of inverter 222. With switch 218 on, the value at slave 204 stored by the latch formed by inverters 220 and 222 remains at output Q. When sclk is 1, switches 210 and 216 are on and switches 208 and 218 are off, so the value of D is formed by inverters 212 and 214 with switch 210 on. Stored in the master 202 by the latch. The previous value at the output of inverter 214 is transmitted as output Q via inverter 222, so that at this point, the previous value of D appears as output Q.

  However, if flip-flop 200 is power gated (such as in a low power mode or other power management mode), sclk turns off and VDD is disconnected from VDDC, so VDD1 is the inverter of master 202 No longer supplies power to 212 and 214. In order to maintain state, VDD 2 provided by VDDC still provides power to inverters 220 and 222 of slave 204. Thus, in FIG. 3, when PG is asserted (set to 1), switches 208 and 218 are on and switches 210 and 216 are off, thus the state of flip-flop 200 is slave 204. Maintained. In this way, the state is maintained in slave 204 (isolated from master 202 by switch 216), while power is removed from master 202, thus reducing leakage power consumed by flip-flop 200. obtain. That is, during power gate control, the flip-flop 200 consumes less power than during normal operation. Also note that when PG is asserted, sclk is shown as “don't care” because it no longer affects the operation of flip-flop 200. That is, when PG is asserted, the flip-flop 200 operates independently of sclk. Accordingly, the switch controller 206 can be configured in a variety of different ways to implement the functions of the table of FIG. 3, in which case the switch controller 206 is powered by VDDC so as not to power down during the low power mode. Supplied.

  The operation of flip-flop 200 will now be described with reference to FIGS. 4 and 6, where it is assumed that flip-flop 200 is a negative edge triggered flip-flop (relative to sclk). Again, flip-flop 200 receives input D, which is finally provided as output Q. As illustrated in the table of FIG. 6, when the flip-flop 200 is known to be a negative edge flip-flop, VDD1 (in the master unit 202) is connected to VDDC (such as VDDC 130) and (in the slave unit 204) ) VDD2 is connected to VDD (VDD132 etc.). Next, in FIG. 4, during normal operation, if PG is deasserted (ie, set to 0), both VDD1 and VDD2 provide power to the inverter because of normal operation Because VDD is connected to VDDC (eg, via transistor 104), thus VDD is approximately equal to VDDC. Therefore, when PG is deasserted, flip-flop 200 operates as a normal negative edge flip-flop. That is, when sclk is 0, switches 210 and 216 are on, switches 208 and 218 are off, and the previous value of D is formed by inverters 212 and 214 with switch 210 on. Stored in the master 202 by the latch. The value in master 202 is also transmitted via switch 216 at the output of inverter 214 and provided as Q via inverter 222. Thus, the previous value of D is stored in master 202 and provided as output Q. When sclk is 1, switches 210 and 216 are off and switches 208 and 218 are on, thus the value of D is applied to the first terminal of switch 216 via switch 208 and inverter 214. Sent. However, since switch 216 is off, this value is not transmitted to slave 204 through switch 216. Slave 204 continuously stores the previous output value of Q in the latch formed by inverters 220 and 222 with switch 218 on.

  However, if flip-flop 200 is power gated (such as in a low power mode or other power management mode), sclk is turned off and VDD is disconnected from VDDC, so VDD2 is the inverter of slave 204. No longer supplies power to 220 and 222. In order to maintain state, VDD 1 provided by VDDC still provides power to inverters 212 and 214 of master 202. Thus, in FIG. 4, when PG is asserted (set to 1), switches 208 and 218 are off and switches 210 and 216 are on, thus the state of flip-flop 200 is master 202. Maintained. In this way, the state is maintained in the master 202 (isolated from the slave 204 by the switch 216), while power is removed from the slave 204, thus reducing the leakage power consumed by the flip-flop 200. obtain. That is, during power gate control, the flip-flop 200 consumes less power than during normal operation. Note that when PG is asserted, sclk is indicated as “don't care” because it no longer affects the operation of flip-flop 200. That is, when PG is asserted, the flip-flop 200 operates independently of sclk. Accordingly, the switch controller 206 for negative edge flip-flops can be configured in a variety of different ways to implement the functions of the table of FIG. 4, in which case the switch controller 206 is powered down during the low power mode. To be powered by VDDC.

  Thus, as described above, depending on whether the flip-flop is configured as a positive or negative edge flip-flop, the state can be held in the slave or master portion of the flip-flop, respectively. That is, in the case of a positive edge flip-flop, the clock provided to the flip-flop (eg, sclk) remains in the first state when entering the low power mode (where, for example, this first state is May be at logic level zero). In this case, when the clock stays, the slave part of the flip-flop includes a state to be held. Thus, the slave unit (for example, the slave 204) receives VDDC. Similarly, in the case of a negative edge flip-flop, the clock provided to the flip-flop (eg, sclk) remains in the second state when entering the low power mode (where, for example, this second state is , May correspond to logic level 1). In this case, when the clock stays, the master part of the flip-flop includes a state to be held. Thus, the master unit (for example, master 202) receives VDDC.

  In some cases, when the clock is stopped, it is not known what state the flip-flop 200 is in. That is, when the clock (eg, sclk) provided to the flip-flop is stopped, it is not known in which state. In these cases, when sclk stops, it is not known which part (master 202 or slave 204) holds the desired state information. Therefore, the operation of the flip-flop 200 will be described with reference to FIGS. 5 and 6 showing the case where the flip-flop 200 is in an unknown state. For example, in the case of a ripple counter, when the sclk is stopped, some of the flip-flops are unknown in which state. However, it is still desirable to save state information. A ripple counter is the only example of a circuit having a flip-flop in an unknown state. That is, other types of circuits may use flip-flops when the state of the flip-flop is unknown when sclk stops. In these types of cases, both VDD1 and VDD2 are provided by VDDC so that power is not removed from either the slave or master portion of flip-flop 200, as illustrated in the table of FIG. .

  For example, in FIG. 5, during normal operation (when PG is deasserted or set to 0), as described above with reference to FIG. 3, flip-flop 200 operates as a positive edge triggered flip-flop. Assume. However, in other embodiments, the unknown state flip-flop may be a negative edge flip-flop, in which case it operates as a negative edge flip-flop during normal operation, as described above with reference to FIG. Please note that. If PG is asserted (ie, set to 1) and sclk is turned off, switches 210 and 218 are turned on and switches 208 and 216 are turned off, thus holding the state. That is, with switch 210 on, master 202 includes a latch formed by inverters 212 and 214. Similarly, with switch 218 on, slave 204 includes a latch formed by inverters 220 and 222, where slave 204 is isolated from master 202 by turning switch 216 off, Master 202 is also isolated from other inputs by turning switch 208 off. Further, power is not removed from any of inverters 212, 214, 220, and 222. In this way, that state is maintained regardless of which state the flip-flop 200 is in. That is, when sclk is turned off, the current state of both master 202 and slave 204 is saved regardless of whether master 202 or slave 204 holds the state of flip-flop 200 at that time. The state is saved. Accordingly, in these cases, the switch controller 206 may be configured to implement the functions of the table of FIG. 5 using any type of circuit.

  Accordingly, it can be recognized that the state of the state can be maintained and the leakage power can be reduced using the function of the improved state holding flip-flop such as the flip-flop 200. Depending on the type of flip-flop in the design (whether positive edge, negative edge, or whether it is in a known state), VDD and VDDC may be used appropriately. In some cases, VDDC is provided to only one of the master or slave units, and in other cases, VDDC may be provided to both the master and slave units. Further, in the illustrated embodiment, the flip-flop 200 has two series connections that can maintain a state without requiring an additional latch, and can further reduce or suppress power loss. Note that multiple latches (eg, master 202 and slave 204) are included.

  Other embodiments may use switches and power supplies differently as needed. For example, for testing purposes, in one embodiment, a test mode shown to switch controller 206 via, for example, a test mode signal (not shown) may be used. When the test mode signal is asserted, the switch controller turns on switches 208 and 216 and turns off switches 210 and 218, so that input D is directly stored in Q without being stored in any latch. Can be routed to. It should also be noted that in other embodiments, flip-flop 200 may be configured differently. For example, in one embodiment, switch 210 and inverter 212 may be implemented as a tri-state inverter (also referred to as a tri-stable inverter), where, when trying to enable switch 210, the tri-state inverter is: If it operates as an inverter, outputs 1 or 0 based on its input, and attempts to disable switch 210, the output of the tristate inverter is high impedance (corresponding to switch 210 being off) To do). The same modification can be made to inverter 220 and switch 218. Also, other types of circuits or elements may be used to implement switches 208, 210, 216, and 218. That is, in the illustrated embodiment, they are implemented as pass gates having NMOS and PMOS transistors connected together. However, in other embodiments they can be implemented differently.

  Thus, in one embodiment, the state holding flip-flop includes input and output nodes and two latches. The two latches include a master latch and a slave latch, each including circuit elements connected in series with input and output nodes, the first of which is decoupled from the second of the latches. In the power management mode, the flip-flop state is maintained. In other embodiments, the state holding flip-flop includes input and output nodes and two latches. The two latches include a master latch and a slave latch, each including a circuit element connected in series with the input and output nodes, the first of the latches being operated using the first power supply signal. The second of the latches is connected to operate using the second power signal, and the second power signal is a power signal that can be adjusted. In yet another embodiment, the state maintaining flip-flop includes an input node, an output node, a master including a plurality of circuit elements, and a slave including a plurality of circuit elements. In this case, the input node, at least one circuit element of the master, at least one circuit element of the slave, and the output node are connected in series. Also, in this case, at least a first circuit element from at least one of the master and slave is in power management mode when power is disconnected from at least a second circuit element from at least one of the master and slave. Configured to receive power. In yet another embodiment, the circuit includes a data path from the input to the output, a master loop circuit having a first circuit element in the data path and connected to receive data from the input, and a first in the data path. A state holding flip-flop is included that includes a slave loop circuit having two circuit elements and connected to receive data from the first circuit element and provide the data to the output, and state holding control means. The state holding control means includes means for enabling the master loop circuit to hold the state of the flip-flop, means for enabling the slave loop circuit to hold the state of the flip-flop, or the master and slave Means are included for enabling both loop circuits to maintain the state of the flip-flop.

  FIG. 7 shows an example of a state holding buffer 300 according to one embodiment of the present invention. The state holding buffer 300 may be power gated to reduce leakage power while maintaining the current state in response to the PG 120. State holding buffer 300 receives input A (which may also be referred to as buffer data input) and provides output Y (which may also be referred to as buffer data output). State holding buffer 300 includes an inverter 302 having an input for receiving A and an output connected to the input of inverter 304 and the output of inverter 306. The output of inverter 304 provides output Y and is connected to the input of inverter 306. The inverting enable input of inverter 302 is connected to receive PG (eg, PG 120, etc.) and is connected to the input of inverter 308. The output of inverter 308 is connected to the inverting enable input of inverter 306. Inverter 302 receives VDD, and inverters 304, 306, and 308 receive VDDC. Accordingly, the first buffer unit (eg, inverter 302) receives the first power signal (eg, VDD), while the second buffer unit (eg, inverters 304, 306, and 308) receives the second power signal. (For example, VDDC) is received.

  The operation of the state holding buffer 300 will be described with reference to the table of FIG. During normal operation, when PG is deasserted and 1 is received as input A, 1 is provided as output Y. Similarly, if 0 is received as input A, 0 is provided as output Y. That is, in FIG. 7, when PG is deasserted (ie, at logic level 0), inverter 302 is enabled, while inverter 306 is disabled. Thus, input A is provided through inverters 302 and 304 (also referred to as data path inverters) and provides output Y. Also, when PG is deasserted, all inverters 302, 304, 308, and 306 are powered because VDD is connected to VDDC (eg, via transistor 104 of FIG. 1) and is approximately equal to VDDC. Supplied. However, when PG is asserted (ie, set to logic level 1) and power gating is performed, such as in a low power mode, output Y holds its state (and input A is a state holding buffer). (It can be treated as “don't care” because it no longer affects the operation of 300). That is, when PG is asserted, Y remains at this value no matter what Y is. In FIG. 7, when PG is asserted (ie, at logic level 1), inverter 302 is disabled and inverter 306 is enabled. Also, once PG is asserted, VDD can be disconnected from VDDC so that only inverters 304, 306, and 308 remain powered. Thus, inverter 302 no longer receives power, thus reducing leakage power. While PG is asserted, the value at output Y is maintained by a latch formed by inverters 304 and 306. Note also that inverter 308 connected between the inverting enable inputs of inverters 302 and 306 ensures that inverters 302 and 306 are not enabled at the same time, preventing data contention problems at the output of inverter 302. However, in other embodiments, the inverter 308 may not be present, or other circuits may be used to prevent data contention. Therefore, it should be noted that the state of the output Y can be maintained using the state holding buffer 300 during power gating. Also note that the state of output Y need not be known. That is, during power gate control, regardless of whether the output Y is 0 or 1, the output Y is simply fed back to the input of the inverter 304 via the inverter 306, so this state is maintained.

  FIG. 9 shows a state holding buffer 400 according to another embodiment of the present invention. The state holding buffer 400 is similar to the state holding buffer 300, but can be used when the state to be maintained is known. State holding buffer 400 receives input A (which may also be referred to as buffer data input) and provides output Y (which may also be referred to as buffer data output). State holding buffer 400 includes an inverter 402 having an input for receiving A and an output connected to the input of inverter 404 and the output of inverter 406. The output of inverter 404 provides output Y. The input of the inverter 306 receives the state holding input S. The inverting enable input of inverter 402 is connected to receive PG (eg, PG 120, etc.) and is connected to the input of inverter 408. The output of inverter 408 is connected to the inverting enable input of inverter 406. Inverter 402 receives VDD, and inverters 404, 406, and 408 receive VDDC. Thus, the first buffer unit (eg, inverter 402) receives the first power signal (eg, VCC), while the second buffer unit (eg, inverters 404, 406, and 408) receives the second power signal. (For example, VDDC) is received.

  The operation of the state holding buffer 400 will be described with reference to the table of FIG. During normal operation, when PG is deasserted and 1 is received as input A, 1 is provided as output Y. Similarly, if 0 is received as input A, 0 is provided as output Y. That is, in FIG. 9, when PG is deasserted (ie, at logic level 0), inverter 402 is enabled, while inverter 406 is disabled. Thus, input A is provided via inverters 402 and 404 (also referred to as data path inverters) and provides output Y. Also, when PG is deasserted, VDD is connected to VDDC (eg, via transistor 104 of FIG. 1) and is approximately equal to VDDC, so that all inverters 402, 404, 408, and 406 are Powered. Note that the state hold input S is treated as “don't care” when PG is deasserted, because it does not affect the operation of the state hold buffer 400 when PG is not asserted.

  However, for power gating such as in low power mode, when PG is asserted (ie, set to logic level 1), the state is maintained by providing state hold input S as output Y. (A can be treated as “don't care” because it no longer affects the operation of state holding buffer 400). Thus, in this embodiment, S can be set to any value desired at the output of state holding buffer 400 during power gating. For example, when PG is asserted, knowing what the state of holding buffer 400 is, S can be set as such and provided as output Y during power gating. In this manner, the state circuit (eg, inverter 406 etc.) sets the state of the buffer in response to receiving S and the inverted power gate control indication signal (eg, PG). In one embodiment, S is implemented in hardware, such as through a transistor, and provides a logic level 1 or 0 at the input of inverter 406. As another option, S may be a programmable value set by software (corresponding to stored bits etc.) or set by hardware (via programmable fuses etc.).

  Accordingly, in FIG. 9, when PG is asserted (ie, at logic level 1), inverter 402 is disabled and inverter 406 is enabled. Also, once PG is asserted, VDD can be disconnected from VDDC so that only inverters 404, 406, and 408 remain powered. Therefore, inverter 402 no longer receives power, thus reducing leakage power. While PG is asserted, the value at output Y is provided by state hold input S via inverters 406 and 404. Also note that inverter 408 connected between the inverting enable inputs of inverters 402 and 406 ensures that inverters 402 and 406 are not enabled at the same time, thus preventing data contention problems at the output of inverter 402. I want to be. However, in other embodiments, the inverter 408 may not be present, or other circuits may be used to prevent data contention. Therefore, it should be noted that the state holding buffer 400 can be used to maintain the state of the output Y during power gate control using the state holding input S when the state of the output Y is known. .

  FIG. 14 shows a state holding buffer 500 according to another embodiment of the present invention. The state holding buffer 500 can be used when the state to be maintained is known to be a logic level zero, and thus can be maintained using a hardware built-in pull-up transistor. State holding buffer 500 receives input A (which may also be referred to as buffer data input) and provides output Y (which may also be referred to as buffer data output). State holding buffer 500 includes an inverter 502 having an input for receiving A and an output connected to the input of inverter 504. The output of inverter 504 provides output Y. The inverting enable input of inverter 502 is connected to receive PG (eg, PG 120, etc.) and is connected to the input of inverter 508. The state holding buffer 500 includes a first current electrode (also referred to as a first current processing terminal) connected to the input of the inverter 504 and a second current electrode (also referred to as a second current processing terminal) connected to VDDC. And a pull-up transistor 510 having: An output of the inverter 508 is connected to a control electrode (also referred to as a control terminal) of the pull-up transistor 510. The inverter 402 receives VDD, and the inverters 504 and 408 receive VDDC. Accordingly, the first buffer unit (eg, inverter 502) receives the first power supply signal (eg, VCC), while the second buffer unit (eg, inverters 404 and 408) receives the second power supply signal (eg, VCC). VDDC) is received. It should be noted that in the present embodiment, the second current electrode of the transistor 510 is connected to the state holding input S corresponding to VDDC in the present embodiment.

  The operation of the state holding buffer 500 will be described with reference to the table of FIG. During normal operation, when PG is deasserted and 1 is received as input A, 1 is provided as output Y. Similarly, if 0 is received as input A, 0 is provided as output Y. That is, in FIG. 14, when PG is deasserted (i.e., at logic level 0), inverter 502 is enabled and pull-up transistor 510 has a value at its control electrode (at logic level 1). Is off). Thus, input A is provided through inverters 502 and 504 (also referred to as data path inverters) and provides output Y. Also, when PG is deasserted, VDD is connected to VDDC (eg, via transistor 104 in FIG. 1) and is approximately equal to VDDC, so all inverters 502, 504, and 508 are powered. Is done.

  However, the state is maintained by pull-up transistor 510 when PG is asserted (ie, set to logic level 1) for power gating, such as during a low power mode. That is, when PG is asserted, pull-up transistor 510 is on, so the input to inverter 504 is coupled to VDDC, thus pulling it to logic level one. Therefore, the output of inverter 504 is maintained at logic level zero. In this way, the state circuit (eg, including pull-up transistor 510) has a state holding input (eg, VDDC connected to the second current electrode of transistor 510) and an inverted power gate control display signal (eg, PG). In response to receiving, the buffer state is set. Accordingly, in FIG. 14, when PG is asserted (ie, at logic level 1), inverter 502 is disabled and inverter 506 is enabled. Also, once PG is asserted, VDD can be disconnected from VDDC so that only inverters 504 and 508 remain powered. Thus, inverter 502 no longer receives power, thus reducing leakage power.

  FIG. 16 shows a state holding buffer 600 according to another embodiment of the present invention. The state holding buffer 600 can be used when the state to be maintained is known to be a logic level 1 and thus can be maintained using a hardware built-in pull-down transistor. State holding buffer 600 receives input A (which may also be referred to as buffer data input) and provides output Y (which may also be referred to as buffer data output). State holding buffer 600 includes an inverter 602 having an input for receiving A and an output connected to the input of inverter 604. The output of inverter 604 provides output Y. The inverting enable input of inverter 602 is connected to receive PG (eg, PG 120, etc.). The state holding buffer 500 includes a first current electrode (also referred to as a first current processing terminal) connected to the input of the inverter 604 and a second current electrode (second current processing) connected to the ground potential (GND). A pull-down transistor 610 having a terminal). Further, PG (for example, PG 120) is provided to a control electrode (also referred to as a control terminal) of the pull-down transistor 610. The inverter 502 receives VDD, and the inverter 604 receives VDDC. Accordingly, the first buffer unit (eg, inverter 602) receives the first power supply signal (eg, VCC), while the second buffer unit (eg, inverter 604) receives the second power supply signal (eg, VDDC). Receive. It should be noted that in the present embodiment, the second current electrode of the transistor 610 is connected to the state holding input S corresponding to GND in the present embodiment.

  The operation state holding buffer 600 will be described with reference to the table of FIG. During normal operation, when PG is deasserted and 1 is received as input A, 1 is provided as output Y. Similarly, if 0 is received as input A, 0 is provided as output Y. That is, in FIG. 16, when PG is deasserted (that is, logic level 0), the inverter 602 is enabled, and the pull-down transistor 610 indicates that the value at its control electrode is logic level 0. And off). Thus, input A is provided through inverters 602 and 604 (also referred to as data path inverters) and provides output Y. Also, if PG is deasserted, VDD is connected to VDDC (eg, via transistor 104 of FIG. 1) and is approximately equal to VDDC, so all inverters 602, 604, and 608 are powered. Is done.

  However, the state is maintained by pull-down transistor 610 when PG is asserted (ie, set to logic level 1) for power gating such as in a low power mode. That is, when PG is asserted, pull-down transistor 610 is on, so the input to inverter 604 is coupled to GND, thus pulling it to logic level zero. Therefore, the output of inverter 604 is maintained at logic level 1. In this way, the state circuit (eg, including the pull-down transistor 610) receives the state holding input (eg, GND connected to the second current electrode of the transistor 610) and the power gate control display signal (eg, PG). In response to, set the buffer state. Accordingly, in FIG. 16, when PG is asserted (ie, at logic level 1), inverter 602 is disabled and inverter 606 is enabled. Also, once PG is asserted, VDD can be decoupled from VDDC so that only inverter 604 is powered. Therefore, inverter 602 no longer receives power, thus reducing leakage power.

  As can be appreciated by the various examples provided in FIGS. 7-10 and 14-17, any type of state set circuit is capable of receiving the state hold signal S and the power gating control signal at the state hold data input. Accordingly, it can be used to set the state of the buffer. That is, other embodiments may use different types of circuits to provide state retention for the buffer, where different parts of the buffer are different to reduce leakage power during the low power mode. Power signals (eg, VDD and VDDC, etc.) can be received.

  Accordingly, in one embodiment, the buffer includes a first buffer unit connected to receive the first power signal and a second buffer unit connected to receive the second power signal. . The first buffer unit includes a buffer data input, and the second buffer unit includes a buffer data output. In this case, one of the first and second power signals is the first and second power sources. It is configured to be selectively enabled independently of the other of the signals. In the present embodiment, each of the first and second buffer units may include a data path unit connected in series between the buffer data input and the buffer data output, and the first or second buffer unit. One of the sections may include a feedback section that allows buffer state retention during the power saving mode. In another embodiment, the circuit includes a first power signal, a gate circuit connected to receive and gate the first power signal, and to controllably provide the second power signal, and Buffer cells. Each buffer cell has a buffer input, a buffer output, an inverter having an inverter input connected to the buffer input and connected to receive the first power supply, and a latch input and a buffer output connected to the inverter output. Having a latched output. The latch is connected to receive the second power source. In yet another embodiment, a method for maintaining a state of a circuit in a power saving mode of the circuit includes providing a first buffer portion connected to receive a first power signal, One buffer unit includes a buffer input. The method also includes providing a second buffer portion connected to receive the second power signal, the second buffer portion including a buffer output. The method further includes supplying a first power signal to the first buffer unit, supplying a second power signal to the second buffer unit, and disabling the first power signal to the first buffer unit. And storing the buffer state in the second buffer unit while the first power signal is disabled. In yet another embodiment, a method for operating a single bit buffer cell includes providing power to a first portion of the buffer, supplying power to a second portion of the buffer, Disabling power to the first portion of the buffer while being supplied to the second portion of the buffer.

  The operation and signal timing of the state holding controller according to various embodiments of the present invention will be described with reference to FIGS. 11-13. FIG. 13 shows a flow 500 illustrating the operation of the data processing system 100 of FIG. 1 according to one embodiment of the invention. FIG. 11 shows a timing diagram corresponding to one embodiment of hardware implementation, and FIG. 12 shows a timing diagram corresponding to one embodiment of software implementation. (Note that the signals shown in FIGS. 11 and 12 are implemented as positive logic signals, but in other embodiments, any signal may be implemented as a negative logic signal). Therefore, first, the flow of FIG. 13 will be described with reference to the data processing system of FIG.

  In FIG. 13, flow 500 begins at start 501 and then the flow proceeds to block 505 where a power gate (PG) request for a sleep region is received. For example, in FIG. 1, this may correspond to state retention controller 118 receiving PGreq 114. In one embodiment, PGreq 114 may correspond to all sleep region functional circuit 124 such that when a PG request is received via PGreq 114, all sleep region functional circuit 124 is power gated. (Note that in this embodiment, PG requests may be referred to as batch PG requests). However, in other embodiments, the PG request may correspond to a portion of the sleep region functional circuit 124 or to another portion of the sleep region functional circuit elsewhere in the data processing system 100 that may be independently power gated. A corresponding PGreq 114 may be received. (Note that in these embodiments, a PG request may also be referred to as a partial PG request.) For example, each PG request received via PGreq 114 may also have which sleep region is power gated. (In this case, the power-gated sleep region may be part of the sleep region functional circuit 124, for example). Also, in this embodiment having multiple parts that can be independently power gated, each part receives the corresponding sclk 122 from the clock controller 116, receives the corresponding PG 120 from the state holding controller 118, and is derived from the VDDC 130. A corresponding VDD 132 may be received. However, for ease of explanation herein, it is assumed that the request received via PGreq 114 indicates that the entire sleep region functional circuit 124 is power gated. Therefore, sclk 122, PG 120, and VDD 132 are all provided to the sleep region function circuit 124.

  Returning to FIG. 13, after receiving a PG request, the flow proceeds to block 510 where the corresponding sleep domain clock (sclk) is disabled. Accordingly, in FIG. 1, when the state holding controller 118 receives a PG request via the PGreq 114, it communicates with the clock controller 116 via the clk control signal 134, and the clock controller 116 can disable the sclk 122. Therefore, the sclk 122 is disabled with respect to the entire sleep area function circuit 124. (However, it should be noted that in other embodiments, the sclk 122 may be disabled for only a portion of the power-gated sleep region functional circuit 124. In this embodiment, the data may be disabled. The processing system 100 may be configured such that a sleep region clock, such as sclk 122, is provided separately for sites that are independently power gated.) Returning to FIG. 13, flow then proceeds to block 515. Proceed to, where it is confirmed that sclk is disabled. Accordingly, in one embodiment, the clock controller 116 may provide confirmation to the state keeping controller 118 that the sclk 122 has been disabled.

After block 515 of FIG. 13, flow proceeds to block 520 where the current state of the corresponding sleep domain circuit is saved. For example, sleep region functional circuit 124 may include state holding flip-flops and buffers similar to those described with reference to FIGS. 2, 7, 9, 14, and 16. Therefore, the state holding controller 118 can assert PG 120, but in this case, the state is maintained according to PG 120. For example, as described above with reference to flip-flop 200 and buffers 300 and 400 in FIGS. 2, 7, 9, 14, and 16, state holding flip-flops and buffers save state in response to PG 120. (Note that in other embodiments, as described above, PG 120 may only assert to a portion of sleep region functional circuit 124 that is power gated, eg, as indicated by PGreq 114. In form, the data processing system 100 may be configured to provide a separate PG signal, such as PG 120, for the independently power gated site.)
After block 520 of FIG. 13, the flow proceeds to block 525 where the supply voltage may be removed or reduced from the corresponding sleep domain circuit site. In the example of FIG. 1, it is assumed that the PG request via PGreq 114 corresponds to the entire sleep region function circuit 124, but the state holding controller 118 asserts the VDD control 110 (that is, the VDD control 110 is set to the logic level 1). Can be disconnected from VDDC 130, so that circuit portions powered by VDD 132 no longer receive power. For example, as described above with reference to flip-flop 200 and buffers 300 and 400, power is removed from circuit elements powered by VDD (while those powered by VDDC retain state). To continue to be powered). Note that during normal or maximum power operation, the state hold controller 118 may maintain the deasserted state of the VDD control 110 such that VDD 132 is connected to VDDC 130 via transistor 104 and VDD 132 is approximately equal to VDDC 130. . It should be noted that in other embodiments, the data processing system 100 may be configured differently so that VDD 132 is not disconnected from VDDC 132 to remove power, but may instead be reduced. For example, in one embodiment, VDD 132 may not be connected to VDDC 130 via transistor 104, but instead to another voltage regulator (not shown) in data processing system 100 that provides power to VDD 132. Can connect. In this embodiment, the voltage regulator connected to VDD 132 may reduce the voltage supplied by VDD 132 based on a control signal from state holding controller 118 to reduce leakage power.

  After block 525 of FIG. 13, the flow proceeds to block 530 where the supply voltage to the operation domain circuit and the rest of the sleep domain circuit is reduced. For example, in the data processing system of FIG. 1, VDDC 130 may be reduced by voltage regulator 102 so that more power is stored. Accordingly, all of the sleep region functional circuit 124 powered by the VDDC 130 and the operation region functional circuit 128 powered by the VDDC 130 can operate with reduced power during power gate control. However, it should be noted that in other embodiments this is optional. That is, in one embodiment, during power gate control, VDDC 130 remains at the same power level.

  Returning to FIG. 13, the flow then proceeds to decision diamond 535 where it is determined whether additional PG requests are received. If so, then the flow proceeds to block 540 where the additional PG request is processed using the process of blocks 510-530 as described above. The flow then returns to decision diamond 535. However, in decision diamond 535, if no further PG requests are received, flow proceeds to block 545 where a batch or partial PG termination request is received. For example, in the example of FIG. 1, a batch PG termination request may be indicated via PGreq 114 (by deasserting PGreq 114, etc.). In other embodiments having circuit portions that can be independently power gated, partial PG termination requests corresponding to one or more of these portions may be received. For example, they may also be received via PGreq 114 with an indication as to which sites are no longer power gated.

  After block 545, flow proceeds to block 550 where the supply voltage is restored as desired for operation and sleep domain circuitry. For example, state retention controller 118 may deassert VDD control 110 such that VDD 132 can be reconnected to VDDC 130, thereby restoring power to elements powered by VDD 132. Similarly, VDD 132 can return to full power if reduced. Also, if VDDC 130 is reduced, it can return to full power. As another option, data processing system 100 may remain in a low power mode with reduced power if power gating is not desired. In this embodiment, the supply voltages VDDC 130 and VDD 132 cannot be restored (ie, block 550 is optional).

  The flow 500 then proceeds to block 555 where the state of the sleep domain circuit is restored. That is, once the supply voltage is restored as desired, the state can be restored. For example, in the data processing system 100, once the VDD control 110 is deasserted to restore VDD 132 and VDDC 130, the state holding controller 118 changes the state as described above with reference to the flip-flop 200 and the buffers 300 and 400. PG 120 may be deasserted so that it can recover. The flow then proceeds to block 560 where the corresponding sleep region sclk that is about to finish power gating is enabled. Thus, in data processing system 100, once PG 120 is deasserted, state retention controller 118 may indicate to clock controller 116 that sclk 122 can be re-enabled. The flow then proceeds to end 565.

  FIG. 11 shows a timing diagram of exemplary timing of signals according to one embodiment of the present invention. For example, the timing diagram of FIG. 11 may correspond to a hardware implementation that achieves the power gating described with reference to FIG. In response to PGreq 114 being asserted (assuming this is a collective PG request for all sleep region functional circuits 124), in FIG. As shown, a stop clock signal may be asserted (eg, by the state retention controller 118 via the clk control signal 134). In response to the stop clk signal, the clock controller 116 may disable the sclk 122. This can be done as soon as the asserted stop clk signal is received or at some predetermined time thereafter to ensure that the clock is properly disabled. The state keeping controller 118 may assert PG 120 at some time T 0 after sclk 122 is disabled. In one embodiment, state retention controller 118 receives a signal from clock controller 116 via clk control signal 134 indicating that sclk 122 has been disabled, and state retention controller PG 120 in response to this signal. Can be asserted. However, in other embodiments, as indicated by the dotted arrow from the rising edge of stop clk to the time PG 120 is asserted, state retention controller 118 asserts stop clk and after a predetermined amount of time PG 120 Can be asserted. The predetermined amount of time may be configured to ensure that a sufficient amount of time elapses between disabling sclk 122 and asserting PG 120, if desired. In some embodiments, T0 may be 0, while in other embodiments, T0 may be long.

  After PG 120 is asserted, state retention controller 118 asserts VDD control 110 to remove the power supplied by VDD 132. In one embodiment, state retention controller 118 waits for a predetermined amount of time after PG 120 is asserted before VDD control 110 is asserted. The predetermined amount of time may be configured to ensure that all circuit elements are properly communicated before a sufficient amount of time T1 has elapsed and before the supply power is removed or reduced. Alternatively, if the supply power is removed or reduced before the PG 120 assertion is received (as seen in the example flip-flop 200 and buffers 300, 400, 500, and 600 above), the state is saved appropriately. I can't. After T1, VDD control 110 is asserted and after a while (as indicated by the arrow from the rising edge of VDD control 110 to the falling edge of VDD 132), VDD 132 drops to a level of 0V. In other embodiments, VDD 132 may be reduced rather than dropping completely to 0V. Also, in one embodiment, as shown in FIG. 11, VDD 130 is also reduced (as indicated by the arrow from the rising edge of VDD control 110 to the falling edge of VDD 130) in response to the assertion of VDD control 110. obtain. However, in other embodiments, VDDC 130 may be reduced in response to the falling edge of VDD 132, or not at all. At this point, the data processing system 100 is power gated and operates in a low power mode.

  When PGreq 114 is deasserted, the state holding controller 118 deasserts the VDD control 110 that restores the VDD 132 and the VDDC 130. After a predetermined amount of time of VDD control 110 deassertion, the state retention controller 118 asserts PG 120. The predetermined amount of time ensures that a sufficient amount of time T2 has elapsed between the restoration of the supply voltage and the deassertion of PG 120 to ensure that the supply voltage is restored before the state is restored. obtain. After deasserting PG 120, state retention controller 118 deasserts the stop clk signal via clk control signal 134 so that clock controller 116 can re-enable sclk 122. Therefore, after receiving the stop clk signal, the clock controller re-enables the sclk 122 as indicated by the dotted arrow from the falling edge of the stop clk to the rising edge of the sclk 122 in FIG.

  Note that in the embodiment of FIG. 11, PGreq 114 may be generated in a variety of different ways. For example, this may be provided by a power management unit (not shown) or by other circuitry internal or external to the data processing system 100. In one embodiment, PGreq 114 may receive based on bits stored in memory programmable via software running on data processing system 100. As another option, PGreq 114 may itself correspond to software controllable bit (s) of storage circuitry within data processing system 100. The timing diagram of FIG. 12 shows an example where software bit (s) may be used as PGreq 114. Note that software may be used to implement the timing diagram of FIG. 12, in which case the software may be located in memory within data processing system 100 and executed by the processor portion. For example, the software can be executed by circuitry in the operational domain functional circuit 128 and stored in memory located anywhere in the data processing system 100. As another option, the software may be executed by circuitry within the state retention controller 118.

  In the timing diagram of FIG. 12, the PG request may be received, for example, by asserting the PGreq bit (in this example, the PG request is also assumed to be a collective PG request for all sleep region functional circuits 124). . After this bit is asserted, using software, the sclk 122 will be disabled, as indicated by the dotted arrow from asserting the PGreq bit to disabling the sclk 122. Can be shown. In response to disabling sclk 122, the stop clock acknowledgment (stop clk_ack) bit (s) may be asserted to indicate that sclk 122 has been disabled. In response to the stop clk_ack signal, the PG bit (which may be stored in some storage circuit in the data processing system 100) may be asserted to indicate that power gating is to be performed. The state retention controller 118 may then assert the voltage control 110 to remove or reduce VDD 132 and reduce VDDC 130 if desired, as described above with reference to FIG. In other embodiments, the software stored in the data processing system 100 detects when the PG bit is asserted and, accordingly, the VDD (s) also stored in memory. Note that VDD control 110 may be controlled by asserting control 110. At this point, the data processing system 100 is power gated and operates in a low power mode.

  When the PGreq bit is deasserted, VDD control 110 may be deasserted (either by software in state retention controller 118 or by hardware), thereby restoring VDD 132 and VDDC 130. When VDD 132 and VDDC 130 are restored, a voltage regulator acknowledgment (voltage reg_ack) signal may be generated (eg, by voltage regulator 102) to indicate that the voltage has been restored. The software may detect the generation of the voltage regulator ack, deassert the PG bit, and initiate the termination of power gating. In one embodiment, voltage reg_ack is also represented by bit (s) stored in data processing system 100. After deasserting the PG bit, the stop clk_ack signal may be deasserted to indicate “restart clock request” to the clock controller 116. Thus, in one embodiment, the stop clk_ack indicates when the clk 122 has been stopped when asserted, and when deasserted, within the data processing system 100 that acts as a request to re-enable the sclk 122. Bit (s) stored in. The clock controller 116 may then re-enable the sclk 122 and the data processing system 100 may resume normal or full power operation.

  Therefore, it should be noted that the flow of FIG. 13 can be realized by hardware, software, or a combination of hardware and software. Data processing system 100 may thus include state holding circuits such as state holding flip-flops 200 and state holding buffers 300 and 400 that can be power gated to save state information while reducing leakage power. In addition, the data processing system 100 is configured in a variety of different ways to properly control the PG signal, sclk, and supply voltages (eg, VDD and VDDC) provided to the state holding flip-flops and buffers. That is, the flow diagram of FIG. 13 and the timing diagrams of FIGS. 11 and 12 are merely examples of methods that can properly control signals within the data processing system 100 to enable power gating.

  Therefore, in one embodiment, a method for reducing power loss in an information processing system having an operation region circuit and a sleep region circuit includes receiving a power gate control request for reducing power loss in the information processing system; Disabling the sleep domain clock connected to the sleep domain circuit and the current state of the corresponding sleep domain circuit in at least one of the two serially connected latches, for each flip of the sleep domain circuit Saving power and adjusting a supply voltage from at least a portion of the sleep domain circuit corresponding to the power gating control request.

  In one embodiment, the circuit includes a gate circuit for receiving a continuous power signal and generating a gate controllable power signal, an operating region flip-flop connected to receive the continuous power signal, A sleep region state retention flip-flop connected to receive a continuous power signal and a gateable power signal, wherein the sleep region state retention flip-flop is a part of the sleep region state retention flip-flop Keep the existing state while disconnecting power to.

  In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, any software taught herein may include one or more computer hard disks, floppy disks, 3.5 "disks, computer storage tapes, magnetic drums, random access memory (RAM) cells, static random Access memory (SRAM) cell, dynamic random access memory (DRAM) cell, synchronous dynamic random access memory (SDRAM) cell, electrically erasable (EEPROM, EPROM, flash) cell, non-volatile cell, ferroelectric or ferromagnetic memory, It may be implemented on a compact disc (CD), laser disc, optical disc, and any similar computer-readable medium, and the block diagram may include blocks different from those illustrated, The flow diagram can be configured differently, and can be configured differently, with more or less steps, or more There may be steps that may be separated into steps, or steps that may be performed simultaneously, so the specification and figures are to be regarded as illustrative rather than restrictive, and All modifications are intended to be included within the scope of the present invention.

  Benefits, other advantages, and solutions to problems have been described above with reference to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that cause or make any benefit, advantage, or solution a decisive, necessary, or essential feature of all claims Or as an element. As used herein, the terms “comprises”, “comprising” or derivatives thereof are intended to cover non-exclusive inclusions and include a series of elements. A method, article, or device may include not only these elements, but also other elements not explicitly listed, as well as other elements unique to such processes, methods, articles, or devices.

1 is a block diagram of a data processing system according to an embodiment of the present invention. FIG. 2 illustrates in partial block diagram form and partial schematic diagram form a state-keeping flip-flop according to an embodiment of the present invention. FIG. 3 illustrates a table corresponding to the operation of various embodiments of a state holding flip-flop, such as the state holding flip-flop of FIG. 2, in accordance with various embodiments of the invention. FIG. 3 illustrates a table corresponding to the operation of various embodiments of a state holding flip-flop, such as the state holding flip-flop of FIG. 2, in accordance with various embodiments of the invention. FIG. 3 illustrates a table corresponding to the operation of various embodiments of a state holding flip-flop, such as the state holding flip-flop of FIG. 2, in accordance with various embodiments of the invention. FIG. 3 illustrates a table corresponding to the operation of various embodiments of a state holding flip-flop, such as the state holding flip-flop of FIG. 2, in accordance with various embodiments of the invention. FIG. 3 is a schematic diagram illustrating a state holding buffer according to an embodiment of the present invention. The figure which shows the table corresponding to operation | movement of the state holding buffer of FIG. 7 based on one Embodiment of this invention. FIG. 6 shows in schematic diagram form a state holding buffer according to another embodiment of the present invention. The figure which shows the table corresponding to operation | movement of the state holding buffer of FIG. 9 based on one Embodiment of this invention. FIG. 2 shows a timing diagram representing the operation of the data processing system of FIG. 1 in accordance with various embodiments of the invention. FIG. 2 shows a timing diagram representing the operation of the data processing system of FIG. 1 in accordance with various embodiments of the invention. FIG. 2 illustrates in flow diagram form a method for state retention according to an embodiment of the present invention. FIG. 6 shows in schematic diagram form a state holding buffer according to another embodiment of the present invention. The figure which shows the table corresponding to operation | movement of the state holding buffer of FIG. 14 based on one Embodiment of this invention. FIG. 6 shows in schematic diagram form a state holding buffer according to another embodiment of the present invention. The figure which shows the table corresponding to operation | movement of the state holding buffer of FIG. 16 based on one Embodiment of this invention.

Claims (45)

A circuit including a state holding flip-flop,
Input and output nodes;
And two latches, a master latch and a slave latch,
Each latch includes a circuit element connected in series with the input and output nodes, wherein the first of the latches is the flip-flop when power is in a power management mode in which power is disconnected from the second of the latches. A circuit configured to maintain the state of a loop. The circuit of claim 1, wherein the flip-flop further comprises:
A switch controller connected to receive a clock signal and a power gate control indication signal, wherein the power gate control indication signal has a first value, the first set of switch control values depending on the clock signal. And a circuit including the switch controller that generates a second set of switch control values independent of the clock signal when the power gate control indication signal has a second value. 3. The circuit of claim 2, wherein the flip-flop further comprises:
A first switch connected between the input node and the master latch;
And a second switch connected between the master latch and the slave latch, wherein the switch controller is connected to provide a switch control signal to the first and second switches. A circuit according to claim 3,
The master latch includes an interconnected inverter and a third switch. One of the inverter and the third switch is connected to the first switch, and the third switch is controlled by the switch controller. Connected to receive signals,
The slave latch includes an interconnected inverter and a fourth switch, one of the inverters of the slave latch and the fourth switch are connected to the second switch, and each inverter of the slave latch is A circuit connected to the output node, wherein the fourth switch is connected to receive a switch control signal from the switch controller. A circuit according to claim 4,
In response to the clock signal having a first value and the power gate control indication signal having a first value, the switch controller controls the first and fourth switches to a first switch state. The second and third switches are configured to control the second switch state,
The switch controller controls the first and fourth switches to the second state in response to the clock signal having a second value and the power gate control display signal having the first value. And configured to control the second and third switches to the first state,
The switch controller is responsive to the power gate control indication signal having a second value to control the first and third switches to a first state and to switch the third and fourth switches to a first state. A circuit configured to control in two states. The circuit of claim 1, wherein the flip-flop further comprises:
A controller connected to receive a clock signal and a power gate control indication signal, and when the power gate control indication signal has a first value, generates a first set of control values depending on the clock signal And when the power gate control indication signal has a second value, the controller generates a second set of control values independent of the clock signal;
At least one tri-stable inverter in each of the latches, wherein the at least one tri-stable inverter is connected to receive a control signal from the controller. The circuit of claim 1, wherein the flip-flop further comprises:
A clock signal input node for receiving the clock signal;
A power gate control display input node for receiving a power gate control display signal, wherein the flip-flop has a first value dependent on the clock signal when the power gate control display signal has a first value. When the power gate control display signal has a second value, the power gate control display signal operates in a second operation state independent of the clock signal, and the second operation state is the first operation state. A circuit that retains the state of the flip-flop while consuming less power. The circuit according to claim 1, wherein the flip-flop further includes:
A first power supply node connected to receive a continuous power supply signal;
And a second power supply node connected to receive a gated power supply signal. A circuit according to claim 8,
The state holding flip-flop is a positive edge flip-flop;
The slave latch is connected to receive the continuous power signal via the first power node;
The master latch is a circuit connected to receive the gated power signal via the second power node. A circuit according to claim 8,
The state holding flip-flop is a negative edge flip-flop,
The master latch is connected to receive the continuous power signal via the first power node;
The slave latch is a circuit connected to receive the gated power signal through the second power node. The circuit of claim 1, comprising:
The state holding flip-flop is a positive edge flip-flop;
The first of the latches is the slave latch;
A circuit in which the second of the latches is the master latch. The circuit of claim 11, further comprising a negative edge flip-flop, wherein the negative edge flip-flop includes:
Input and output nodes;
Two latches, a master latch and a slave latch, each latch of the negative edge flip-flop including circuit elements connected in series with the input and output nodes of the negative edge flip-flop, The circuit configured to maintain the state of the flip-flop in a power management mode in which power is disconnected from the slave latch of the negative edge flip-flop. The circuit of claim 1, further comprising:
A clock controller connected to receive a reference clock and to provide an operating clock and a sleep clock;
An operation region circuit including a non-state holding flip-flop, wherein the non-state holding flip-flop is connected to receive the operation clock signal;
A sleep region circuit including the state retention flip-flop connected to receive the sleep clock signal;
Circuit containing. The circuit of claim 13, further comprising:
A state keeping controller connected to provide a power gate control indication signal to the sleep region circuit and to provide a power gate control signal to the power gate control switch;
The power gate control switch connected to receive a continuous power signal under control of the power gating signal and to provide a gated power signal to the sleep domain circuit;
Circuit containing. The circuit of claim 1, comprising:
The state holding flip-flop is a negative edge flip-flop,
The first of the latches is the master latch;
A circuit in which the second of the latches is the slave latch. The circuit according to claim 1, wherein the flip-flop further includes:
A switch controller connected to receive the clock signal and the power gate control indication signal;
In response to the clock signal having a first value and the power gate control indication signal having a first value, the switch controller controls the first and fourth switches to a first switch state. The second and third switches are configured to control the second switch state,
The switch controller controls the first and fourth switches to the second state in response to the clock signal having a second value and the power gate control display signal having the first value. And configured to control the second and third switches to the first state,
The switch controller is responsive to the power gate control indication signal having a second value to control the third and fourth switches to the first switch state, and the first and second switches A circuit configured to control the second state to the second state. A state-holding flip-flop,
Input and output nodes;
Two latches including a master latch and a slave latch, each latch including a circuit element connected in series with the input and output nodes, wherein the first of the latches is a first power signal. The second of the latches is connected to operate using a second power signal, and the second power signal is a flip-flop that is a power signal that can be adjusted and controlled. P. A state holding flip-flop according to claim 17,
The first of the latches is a flip-flop configured to maintain the state of the flip-flop in a power management mode in which the second power signal is disconnected from the second of the latches. A state holding flip-flop according to claim 17,
The first of the latches is configured to hold the state of the flip-flop during a power management mode in which the second power supply signal is reduced relative to the second of the latches. flip flop. 18. The apparatus of claim 17, wherein the flip-flop is a positive edge flip-flop, the first is the slave, and the second is the master. 18. The apparatus of claim 17, wherein the flip-flop is a negative edge flip-flop, the first is the master, and the second is the slave. A method for reducing power loss in an information processing system having an operation region circuit and a sleep region circuit,
Receiving a power gating control request for reducing power loss in the information processing system;
Disabling a sleep domain clock connected to the sleep domain circuit;
Saving the current state of the corresponding sleep domain circuit in at least one of two serially connected latches in each flip-flop of the sleep domain circuit;
Adjusting a supply voltage from at least a portion of a sleep domain circuit corresponding to the power gate control request;
Include methods. 23. The method of claim 22, wherein the power gating request is a partial gating request, and the step of receiving the gating request identifies a particular sleep domain circuit of a plurality of sleep domain circuits. A method that includes a step to do. 23. The method of claim 22, wherein the power gate control request is a collective gate control request that requests the start of a power saving state for all sleep region circuits in the information processing system. 23. The method of claim 22, wherein the step of disabling the sleep region clock includes disabling the sleep clock prior to adjusting the supply voltage of the sleep region circuit. A method that includes the step of confirming. 23. The method of claim 22, wherein adjusting the supply voltage of the sleep domain circuit includes at least one of the following steps:
Disconnecting power from the sleep domain circuit, or
Reducing power to the sleep domain circuit;
Include methods. 23. The method of claim 22, further comprising:
Receiving an additional power gating request; and
In response to receiving the additional power gate control request, repeating a disable state, a confirmation step, and a save step; and
Include methods. 24. The method of claim 22, further comprising reducing a supply voltage to the operating region circuit and any sleep region circuit that is still operating. 23. The method of claim 22, further comprising:
Receiving a bulk or partial power gate control termination request;
Restoring the supply voltage to the operating region and sleep region circuit;
Restoring the state of the sleep region circuit;
Enabling the sleep region clock; and
Include methods. 23. The method of claim 22, wherein restoring the state of the sleep domain circuit comprises restoring a higher power level to the sleep domain circuit, and enabling the sleep domain circuit. And operating based on the sleep clock. 23. The method of claim 22, wherein the step of saving the current state of a corresponding sleep domain circuit includes:
Saving the current state in the master latch of each flip-flop in which the received clock signal remains in the first state;
Saving the current state in the slave latch of each flip-flop where the received clock signal remains in the second state;
Include methods. 32. The method of claim 31, wherein the first state is logic zero and the second state is logic one. A state-holding flip-flop,
An input node;
An output node;
A master including a plurality of circuit elements;
A slave including a plurality of circuit elements, and
The input node, at least one circuit element of the master, at least one circuit element of the slave, and the output node are connected in series,
At least a first circuit element from at least one of the master and the slave has power in a power management mode in which power is disconnected from at least a second circuit element from at least one of the master and the slave. A flip-flop configured to receive power. A circuit,
A gate circuit for receiving a continuous power supply signal and generating a gateable power supply signal;
An operating region flip-flop connected to receive the continuous power signal;
A sleep region state retention flip-flop connected to receive the continuous power signal and the gate controllable power signal, wherein the sleep region state retention flip-flop is a portion of the sleep region state retention flip-flop A circuit that maintains the existing state while disconnecting power to the device. A circuit including a state holding flip-flop, wherein the state holding flip-flop includes:
A data path from input to output;
A master loop circuit having a first circuit element in the data path and connected to receive data from the input;
A slave loop circuit having a second circuit element in the data path and connected to receive data from the first circuit element and to provide data to the output;
State holding control means,
Means for enabling the master loop circuit to maintain the state of the flip-flop;
Means for enabling the slave loop circuit to maintain the state of the flip-flop;
Means for holding both the master and slave loop circuits in an enabled state and holding the state of the flip-flop, and the state holding control means including one of a group consisting of:
Circuit containing. 36. The circuit of claim 35, wherein the state holding flip-flop is a positive edge triggered flip-flop, and the state holding control means includes the means for enabling the slave loop circuit. Circuit. 37. The circuit of claim 36, wherein the state holding flip-flop further comprises:
A master loop switch of the master loop circuit;
A slave loop switch of the slave loop circuit;
An inter-loop switch connected between the master loop and the slave loop,
The state holding control means includes a control signal for closing the slave loop switch and opening the master loop switch and the inter-loop switch in the power saving mode. 36. The circuit according to claim 35, wherein the state holding flip-flop is a negative edge triggered flip-flop, and the state holding control means includes the means for enabling the master loop circuit. Circuit included. 40. The circuit of claim 38, wherein the state holding flip-flop further comprises:
A master loop switch of the master loop circuit;
A slave loop switch of the slave loop circuit;
An inter-loop switch connected between the master loop and the slave loop,
The state holding control means includes a control circuit for closing the master loop switch and opening the slave loop switch and the inter-loop switch in the power saving mode. 36. The circuit according to claim 35, wherein the state holding flip-flop is an edge-triggered flip-flop, and the state holding control means is for enabling both the master and the slave loop circuit. A circuit including the means. 41. The circuit of claim 40, wherein the state holding flip-flop further comprises:
An input switch connected between the input of the state maintaining flip-flop and the master loop;
A master loop switch of the master loop circuit;
An inter-loop switch connected between the master loop and the slave loop;
A slave loop switch of the slave loop circuit,
The state holding control means includes a control circuit for opening the input switch and the inter-loop switch and closing the master and slave loop switches in the power saving mode. 42. The circuit of claim 41, wherein the state holding flip-flop further comprises:
An input switch connected between the input of the state maintaining flip-flop and the master loop;
A master loop switch of the master loop circuit;
An inter-loop switch connected between the master loop and the slave loop;
A slave loop switch of the slave loop circuit;
An input for receiving a clock signal;
Control means for operating the master switch and the inter-loop switch in a first switch state in response to the clock signal having a first value, and further in an operation mode other than the power saving mode, The control means for operating the inter-loop switch and the slave loop switch in response to the clock signal having a second value;
Circuit containing. 36. The circuit of claim 35, wherein the state retention flip-flop is a first state retention type, the circuit further comprising:
A circuit including the second type of state holding flip-flop, the second type of state holding flip-flop including an enabling means different from the enabling means of the first type of state holding flip-flop. 44. The circuit of claim 43, further comprising:
A third type of state holding flip-flop, the third type of state holding flip-flop including an enabling means different from the enabling means of the state holding flip-flops of the first and second types. circuit. 45. The circuit of claim 44, wherein
The first type includes a positive edge triggered flip-flop that includes the means for enabling the slave loop circuit to maintain the state of the flip-flop,
The second type includes a negative edge triggered flip-flop including the means for enabling the master loop circuit and maintaining the state of the flip-flop,
The third type circuit includes an edge-triggered flip-flop including the means for enabling both the master and the slave loop circuit to hold the state of the flip-flop.

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