JP2006222952A - Multi-threshold cmos system, and method for controlling respective blocks - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MTCMOS system and method for controlling respective blocks. <P>SOLUTION: The MTCMOS system and method individually controls the state of the respective blocks. Each blocks includes a logic circuit, having a logic transistor and a control transistor connected in between a power line connected to one of ground voltage and supply voltage and the logic circuit. The control transistor has threshold higher than that of the logic transistor. The blocks are controlled by generating an individual blcok on/off (BLOCK_ON/OFF) signal for each block, generating an individual control signal, in response to the individual block on/off (BLOCK_ON/OFF) signal, supplying the individual control signal to the control transistor and controlling voltage supply to the logic circuit within each block, based on the individual control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an MTCMOS (Multi-Threshold Complementary Metal-Oxide-Silicon), and more particularly to an MTCMOS system and a control method for each block.

  As semiconductor devices are highly integrated, demands for low power consumption have increased. One way to reduce power consumption in an integrated circuit is to reduce the supply voltage. However, reducing the supply voltage reduces the speed of the transistors in the integrated circuit. Thereby, the threshold voltage (Vth) of the transistor decreases. However, when the threshold voltage is decreased, the leakage current of the transistor is increased, and the power consumption is increased when the semiconductor device is in a standby mode. This is particularly important for devices with a high ratio of standby mode to active mode (standby activity ratio), i.e. mobile and portable devices where leakage current is the dominant factor in overall battery life.

  One way to solve this problem is to use MTCMOS, which uses all transistors with high and low threshold voltages. Specifically, MTCMOS systems use a low threshold voltage to place the gate at high operating speeds and leak in standby mode using a high threshold voltage to form a virtual gate at low operating speeds. Suppresses current. That is, a low threshold voltage transistor is used for logic operations, and a high threshold voltage transistor is used to provide a power supply voltage and / or a ground voltage.

  In the active mode, the high threshold voltage transistor is turned on to provide the power supply voltage to the logic gate, and the low threshold voltage transistor operates at high speed. In standby mode, the high threshold voltage transistor is turned off to turn off the low threshold voltage transistor, reducing or eliminating leakage current through the low threshold voltage transistor.

  FIG. 1 is a block diagram illustrating a conventional MTCMOS system 100. The MTCMOS system 100 includes a power manager 10, an MTCMOS controller 20, and an MTCMOS design area 30. The MTCMOS design area 30 is composed of a plurality of blocks. Each block includes a flip-flop (F / F, 32), a logic block 34, a MOS switch 36, and a functional block 38. MOS switch 36 has a higher threshold voltage than logic block 34. The flip-flop 32 and the logic block 34 are connected between a power supply voltage (VDD) and a virtual ground (VGND). The MOS switch 36 is connected between a ground voltage (GND) and a virtual ground (VGND).

  In the active mode, the MOS switch 36 is turned on to provide a power supply voltage and a ground voltage to the logic block 34. In the standby mode, the MOS switch 36 is turned off to block the supply of the power supply voltage (VDD) and / or ground voltage (GND) to the logic block 34, thereby reducing the leakage current of the logic block 34 and reducing the power consumption of the system. Let

  When the system enters the standby mode, the power manager 10 transmits a stop signal (STOP) to the MTCMOS controller 20 and the MTCMOS design area 30, respectively, and does not transmit a clock signal. In response to the stop signal (STOP), the MTCMOS controller 20 outputs a signal (SC) for controlling the MOS switch 36 and an inversion control signal (SCB) for controlling the flip-flop 32. When the power supply voltage (VDD) is cut off, the virtual ground voltage (VGND) level becomes a floating state. In order to prevent loss of data stored in the logic block 34, data is stored in the flip-flop 32 in response to the inversion control signal (SCB) before turning off the MOS switch 36 in response to the control signal (SC). To do. In many systems, for example, in mobile systems, only some functions are typically activated and the remaining functions remain deactivated. However, the conventional MTCMOS system enters the standby mode only when the entire system is not operating. Thus, conventional MTCMOS systems cannot control individual blocks when only certain blocks need to be activated, and cannot reduce power consumption.

  Accordingly, an object of the present invention is to provide an MTCMOS system and method capable of controlling a plurality of functional blocks.

  It is another object of the present invention to provide an MTCMOS system and method that can reduce power consumption when only certain functions are performed.

  Still another object of the present invention is to provide a circuit for preventing a floating state generated between blocks.

  At least one of the features and advantages of the present invention is to provide a method for controlling a plurality of blocks. Each block includes a logic circuit including a logic transistor and a control transistor connected between a power line connected to a power source and the logic circuit, and the control transistor has a higher threshold voltage than the logic transistor. . The method of controlling a block includes generating individual block on / off signals for each block, individually generating control signals in response to individual block on / off signals, and individual control signals for control transistors. And controlling the voltage provided to the logic circuit in each block corresponding to the individual control signal.

The control method further includes buffering the output of the logic circuit when each block is in an ON state and controlling buffering corresponding to the inverted individual control signal. The control method includes delaying an individual control signal that is inverted compared to the individual control signal when the block is turned on and inverted compared to the individual control signal when the block is turned off. The method may further include delaying the individual control signal.
Before outputting the individual control signal, the control method sends a request signal to the corresponding predetermined block in response to the individual block on / off signal and the corresponding block is ready to receive the individual control signal. Sending a response signal from the corresponding block when it is. The control method may further include generating a block selection signal according to the response signal and controlling the individual control signal generation according to the block selection signal.

  The step of supplying individual control signals corresponds to a wake-up event.

  The control method may further include preventing leakage current from the block from affecting other blocks when the predetermined block is in an off state. The control method may further include providing an output of the logic circuit of the block to the bus holder when the block is in an off state. The step of providing the output of the logic block is controlled by an inverted individual control signal.

  At least one of the features and advantages of the present invention is to provide a system composed of a plurality of blocks. Each block is a logic transistor, and a power line and a logic circuit connected to one of a ground and a power source. And a logic circuit including a control transistor coupled between the first and second transistors. The system outputs a separate block on / off signal (BLOCK_ON / OFF) for each block and receives a separate block on / off signal for each block and adjusts a voltage supplied to the logic circuit. A control circuit for outputting individual control signals to the control transistors in the block is included.

  Each block may include a buffer disposed in parallel with the logic circuit, and the control circuit further outputs an individual control signal inverted to the buffer. The system includes a first delay for delaying an individual control signal that is inverted compared to an individual control signal when the block is about to be turned on, and an individual control that is inverted when the block is about to be turned off. A second delay unit that delays the individual control signal compared to the signal may be further included.

  The control circuit may further output a request signal to a corresponding predetermined block in response to an individual block on / off signal before outputting the individual control signal, and each block may output an individual control signal. Send response signal when ready to receive. The control circuit sends a request signal to a corresponding block when receiving an individual block on / off signal from the power manager, and outputs a block selection signal when receiving a response signal from the corresponding block and a block selection And a state controller that outputs the individual control signal when receiving a signal.

  After outputting the individual control signal, the control circuit outputs the individual control signal to the power manager in response to the wakeup event and the wakeup signal.

  The system can include a floating prevention circuit associated with a given block. The floating prevention circuit receives the individual control signal inverted from the control circuit and the output of the logic circuit of a predetermined block corresponding thereto, and outputs the output of the logic circuit according to the inverted individual control signal ( tri-state buffer) and a bus holder that receives the output of the tri-state buffer. The system can include a pair of anti-floating circuits between adjacent blocks.

  At least one or more features and advantages according to the present invention are to provide a system for protecting the first block and the second block. In this case, each block includes a logic circuit having an on / off state controlled individually, the system is located between the first block and the second block, and the system is a logic circuit of the first block. A first tri-state buffer for receiving a first output of the first block and a first inverted control signal corresponding to the first block and outputting a first output in response to the first inverted control signal; A second tri-state buffer for receiving a second output of the logic circuit and a second inverted control signal corresponding to the second block and outputting a second output in response to the second inverted control signal; A second bus holder may be included for receiving the output of the two tri-state buffer.

  Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a block diagram illustrating an MTCMOS system 200 according to one embodiment of the present invention. The MTCMOS system 200 includes a power manager 220, an MTCMOS controller block 250 having a block controller 240 and a state controller 260, and an MTCMOS design area 210 having a plurality of blocks 210-i.

  As shown in FIG. 3, each block 210-i includes a flip-flop 211, a logic circuit 215, a MOS switch 217, and a functional block 219. MOS switch 217 has a higher threshold voltage than logic circuit 215. The flip-flop 211 and the logic circuit 215 are connected between a power supply voltage (VDD) and a virtual ground voltage (VGND). The MOS switch 217 is connected between the ground voltage (GND) and the virtual ground voltage (VGND).

  In response to the wake-up event (WAKE_UP_EVENT), the state controller 260 generates a control signal (SC) and an inverted control signal (SCB) according to the number of blocks to be controlled and the wake-up signal (WAKE_UP). . In the specific example shown in FIG. 2, each block (210-i) is controlled individually. Therefore, the number of control signals (SC) and inverted control signals (SCB) is the same as the number of blocks n.

  The power manager 220 generates a stop signal (STOP), a plurality of clock signals (CLK1-n) output to the state controller 260, and an individual block on / off signal (BLOCKi_ON / OFF) output to the block controller 240. The wake-up signal (WAKE_UP) is received from the state controller 260. The block controller 240 sends a request signal (X_reqi) to the corresponding block in response to the block on / off signal. The corresponding predetermined block 210-i sends a response signal (X-acki) to the block controller once the predetermined block 210-i finishes the current operation. The block controller 240 sends a block selection signal (MT_SELi) to the state controller 260 in response to the response signal (X_ack) received from the block. The state controller 260 supplies or cuts off the power supply voltage to the specific block 210-i based on a control signal corresponding to the block selection signal (MT_SELi).

  In order to deactivate the specific block 210-i, the power manager 220 outputs a stop signal (STOP) to the state controller 260, and the state controller 260 responds to the block selection signal (MT_SELi) from the block controller 240. Then, the control signal (SCi) and the inverted control signal (SCBi) are sent to the corresponding predetermined block 210-i. The MOS switch 217 is turned off in response to the control signal (SCi), the virtual ground voltage (VGND) is in a floating state, and the data stored in the logic circuit 215 is lost. Accordingly, the data is stored in the flip-flop 211 in response to the inversion control signal (SCBi) before the MOS switch 217 is turned off. That is, the inversion control signal (SCBi) changes to logic low before the control signal SCi changes to logic high.

  In order to activate the specific block 210-i, the state controller 260 outputs a wakeup signal to the power manager 220, and responds to the block selection signal (MT_SELi) with the control signal (SCi) and the inverted control signal (SCBi). Send to. Accordingly, the MTCMOS system 200 can reduce power consumption even when only some functions are utilized.

  FIG. 4 shows a specific embodiment of the block controller 240. As shown in FIG. 4, the block controller 240 includes a plurality of block selection signal generators 241. Each block selection signal generator 241 includes a first AND gate 242 and a second AND gate 244. The first AND gate 242 performs an AND operation on the enable signal (EN) and the block on / off signal (BLOCK_ON / OFF). The second AND gate 244 performs an AND operation on the response signal (X_acki) and the block on / off signal (BLOCKi_ON / OFF). The AND gate 242 outputs a request signal (X_reqi) to the corresponding block when the corresponding block is to be activated.

  As shown in FIG. 5, in order to inactivate a predetermined block, the block on / off signal (BLOCi_ON / OFF) becomes logic high, the request signal (X_reqi) becomes logic high, and the predetermined block becomes After the time (TD1) for completing the operation currently being performed, the response signal (X_acchi) becomes logic high, and the block selection signal (MT_SELi) becomes logic high in response to the response signal (X-acchi). In order to turn off the MOS switch 217, the control signal (SCi) becomes logic high. In order to activate a predetermined block, first, a block on / off signal (BLOCKi_ON / OFF) becomes a logic low, a request signal (X_reqi), a response signal (X_acki), and a block selection signal (X MT_SELi) sequentially becomes logic low, and after a predetermined time (TD2) elapses after the block on / off signal (BLOCKi_ON / OFF) becomes logic low, the control signal (SCi) becomes logic low.

  A specific embodiment of the state controller 260 is shown in FIG. The state controller 260 includes a plurality of AND gates 261, 263, 265, 267, 281-1,. . . , 281-n, 285-1,. . . 285-n, a NAND gate 269, a plurality of delay circuits 271 to 274, and an inverter 276.

  The stop signal (STOP) is input from the power manager 220 to the state controller 260. The first AND gate 261 receives a stop signal and a stop signal having a first delayed output. The stop signal having the first delay output is also output to the second delay circuit 272. The second AND gate 263 receives a stop signal having a first delayed output and a stop signal having a second delayed output.

  A signal instructing a wake-up event (WE) is input to the state controller 260 from the outside. The inverter 276 receives the wakeup event signal (WE) and outputs the inverted signal (IWE) to the third delay circuit 273. An inverted wakeup event signal (IWE) having a third delay output is output to the fourth delay circuit 274. The third AND gate 265 receives an inverted wakeup event signal (IWE) having a third delay and an inverted wakeup event signal (IWE) having a fourth delayed output.

  The fourth AND gate 267 receives the inverted wakeup signal (IWE) having the third delay and the output of the first AND gate 261. The output of the fourth AND gate 267 is an inversion control signal (SCB). NAND gate 269 receives the wakeup event signal (WE) and the output of AND gate 263. The output of the NAND gate 269 is a control signal (SC).

  The AND gates 281-1 to 281-n receive the block selection signal (MT_SELi) for each block and the control signal (SC) for determining the inversion control signal (SCi) for each block, which are the outputs of the block controller 250, respectively. To do.

  As shown in FIG. 7, for example, if the first block 210-1 attempts to enter the standby mode, the wakeup event signal (WE) is low and the stop signal (STOP) is high at time T1. The inversion control signal (SCB1) goes high at T2, and the control signal (SC1) goes low at T3. For example, if the first block 210-1 is activated, the wakeup event signal (WE) goes high at T5, the control signal (SC1) goes high at T6, and the inverted control signal (SCB1) goes low at T7. become. The wakeup event signal (WE) and stop signal (STOP) all go low at T8.

  Therefore, for example, if the first block 210-1 is to be deactivated, the first delay circuit 271 and the second delay circuit 272 are switched between the state change with respect to the inversion control signal (SCB1) and the control signal (SC1). There is a predetermined time delay (TD3) used, and the data of the logic circuit 215-1 is stored in the flip-flop 211-1 before the MOS switch 217 is turned off. For example, when the first block 210-1 is to be activated, a predetermined time delay (TD4) exists between the state changes for the control signal (SC1) and the inverted control signal (SCB1), and the MOS switch 217 is turned on. The data stored in the flip-flop 211-1 is re-stored in the logic circuit 215-1.

  A pair of anti-floating circuits are provided between the blocks. As shown in FIG. 8, the first floating prevention circuit 830 includes a tri-state buffer 810 and a bus holder 820. The second floating prevention circuit 840 may include a tri-state buffer 822 and a bus holder 812. In the first floating prevention circuit 830, the bus holder 820 stores the previous data from the first block 210-1, and the tri-state buffer 810 receives the first block 210-1 and the second block 210-2 according to an inversion control signal (SCB1). To regulate the current flow between. In the second floating prevention circuit 840, the bus holder 822 stores the previous data from the second block 210-2, and the tri-state buffer 822 receives the first block 210-1 and the second block 210- according to the inversion control signal (SCB2). 2 to adjust the current flow between.

  Accordingly, each tri-state buffer receives the inverted individual control signal from the controller circuit and the output of the logic circuit corresponding to the predetermined block, and outputs the output of the logic circuit to the corresponding bus holder by the inverted individual control signal. Output. When the first block 210-1 is in the standby mode and the second block 210-2 is in the active mode, the tri-state buffer 810 is in a high impedance state and the current path from the first block 210-1 to the second block 210-2. The data is stored in the bus holder 820, and the leakage current due to the floating virtual ground voltage (VGND) of the first block 210-1 is prevented.

  An MTCMOS system 900 according to another embodiment of the present invention is shown in FIG. The MTCOMS system 900 does not use the block controller 240 and the state controller 250 for the block selection signal (MT_SEL), but generates control signals (SC, SCB) in response to the response signals (X_ack) received from the corresponding blocks. The MTCMOS controller circuit 950 is substituted. In particular, the MTCMOS controller 950 sends a request signal (X_req) to a specific block in response to a block on / off signal (BLOCK_ON / OFF) from the power manager 220. When the corresponding block finishes the current operation, it sends a response signal (X_ack) to the MTCMOS controller circuit. Unlike the case where the MTCMOS controller circuit responds to the block selection signal (MT_SEL) in the embodiment described above, the control signal (SC) and the inverted control signal (SCB) are sent to each block in response to the response signal (X_ack). send. Otherwise, the operation of the MTCMOS controller circuit is the same as that of the above-described embodiment.

The MTCMOS co-system according to the present invention can reduce power consumption by controlling each block separately. As used so far, the word block can contain more than one functional block. Although embodiments of the present invention have been described in connection with a hardware implementation, the processes of the present invention can be implemented in software, i.e., a structure having a machine accessible medium.

  The present invention has been described in detail with reference to the embodiments. However, the present invention is not limited to this, and any person having ordinary knowledge in the technical field to which the present invention belongs can be used without departing from the spirit and spirit of the present invention. The present invention can be modified or changed.

It is a block diagram which shows the conventional MTCMOS system. 1 is a block diagram illustrating an MTCMOS system according to an embodiment of the present invention. FIG. 3 is a detailed block diagram of one block included in the MTCMOS design region of FIG. 2 according to an embodiment of the present invention. FIG. 3 is a conceptual diagram of the block controller of FIG. 2 according to an embodiment of the present invention. FIG. 5 is a timing diagram of the block controller of FIG. 4 according to one embodiment of the present invention. FIG. 3 is a conceptual diagram of the MTCMOS controller of FIG. 2 according to an embodiment of the present invention. FIG. 7 is a timing diagram of the MTCMOS controller of FIG. 6 according to one embodiment of the present invention. FIG. 3 is a block diagram illustrating a function for preventing floating between blocks according to an exemplary embodiment of the present invention. FIG. 6 is a block diagram of an MTCMOS system according to another embodiment of the present invention.

Explanation of symbols

200 MTCMOS system 210-i block 211 flip-flop 215 logic circuit 217 MOS switch 217
219 Function block 220 Power manager 240 Block controller 241 Block selection signal generator 242 First AND gate 244 Second AND gate 250 MTCMOS controller block 260 State controller 276 Inverter VDD Power supply voltage VGND Virtual ground voltage

Claims (20)

In a method for controlling a plurality of blocks,
Each block includes a logic circuit having a logic transistor, and a control transistor connected between a power line connected to one of a ground voltage and a supply voltage and the logic circuit, and the control transistor is the logic transistor. Has an even higher threshold voltage,
Generating a separate block on / off signal for each block;
Generating an individual control signal in response to the individual block on / off signal;
Supplying the individual control signals to the control transistors in each block;
Adjusting a voltage supplied to the logic circuit in each block in response to the individual control signal;
A method for controlling a plurality of blocks. For each block, buffering the output of the logic circuit when the block is in an on state;
2. The method of controlling a plurality of blocks of claim 1, further comprising the step of controlling buffering with an inverted individual control signal. Delaying an individual control signal inverted relative to the individual control signal when the block is about to be turned on;
Delaying the individual control signal relative to the inverted individual control signal when the block is about to be turned off;
The method of controlling a plurality of blocks according to claim 1, further comprising: Sending a request signal to a predetermined block corresponding to the individual block on / off signal;
The plurality of claim 1, further comprising: sending a response signal from the corresponding block when ready to receive the individual control signal before outputting the individual control signal. How to control a block. Generating a block selection signal according to the response signal;
5. The method of controlling a plurality of blocks according to claim 4, further comprising: controlling generation of the individual control signal based on the block selection signal.   The method of claim 1, wherein providing the individual control signal is responsive to a wake up event.   The method of claim 1, further comprising preventing the block from affecting other blocks when the block is in an off state.   The method of claim 1, further comprising providing an output of the logic circuit to a bus holder when the block is in an off state.   9. The method of controlling a plurality of blocks according to claim 8, further comprising the step of controlling the provision of the output of the logic circuit according to an inverted individual control signal. Each block includes a logic circuit having a logic transistor, and a control transistor connected between a power line connected to one of a ground voltage and a supply voltage and the logic circuit, and the control transistor is the logic transistor. A plurality of blocks having even higher threshold voltages;
A power manager to output individual block on / off signals for each block;
A control circuit that individually receives a block on / off signal for each block and outputs a control signal individually to the control transistor in the block to control voltage supply to the logic circuit;
A system characterized by including.   11. The system of claim 10, wherein each block further includes a buffer in parallel with the logic circuit, and the control circuit further outputs an individual control signal inverted to the buffer. A first delay unit for delaying the inverted individual control signal compared to the individual control signal when the block is to be turned on;
12. The system of claim 11, further comprising a second delay unit for delaying an individual control signal relative to the inverted individual control signal when the block is about to be turned off. .   The control circuit further outputs a request signal to a corresponding block according to the individual block on / off signal before outputting the individual control signal, and each block is prepared to receive the individual control signal. 11. The system of claim 10, wherein a response signal is sent when a response is made. The control circuit is
A block controller for receiving the individual block on / off signal from the power manager, sending the request signal to the corresponding block, receiving a response signal from the corresponding block, and outputting a block selection signal;
The system according to claim 13, further comprising: a state controller that receives the block selection signal and outputs the individual control signal based on the block selection signal.   The control circuit outputs the individual control signal in response to a wakeup event, and further outputs a wakeup signal to the power manager in response to the wakeup event after the output of the individual control signal. The system according to claim 10.   The system of claim 10, further comprising a floating prevention circuit associated with the block. The floating prevention circuit is
A tri-state buffer that receives an individual control signal inverted from the control circuit and an output of the logic circuit of a corresponding block, and outputs an output of the logic circuit according to the inverted individual control signal;
The system of claim 16, further comprising: a bus holder that receives the output of the tri-state buffer.   The system of claim 10, further comprising a pair of anti-floating circuits between adjacent blocks. Each floating prevention circuit
A tri-state buffer that receives an individual control signal inverted from the control circuit and an output of the logic circuit of a corresponding block, and outputs an output of the logic circuit according to the inverted individual control signal;
19. The system of claim 18, further comprising a bus holder that receives the output of the tri-state buffer. A system for protecting a first block and a second block, each block including a logic circuit and having an individually controlled on / off state, wherein the system includes a first block and a second block. In a system located between, the system comprises:
A first tri-state buffer for receiving a first output of the logic circuit of the first block and a first inversion control signal for the first block and outputting the first output in response to the first inversion control signal When,
A first bus holder for receiving the output of the first tri-state buffer;
A second tri-state buffer for receiving a second output of the logic circuit of the second block and a second inversion control signal for the second block and outputting the second output in response to the second inversion control signal When,
A second bus holder for receiving the output of the second tri-state buffer;
A system characterized by including.

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