CN103269213A

CN103269213A - Clockless buffer trigger

Info

Publication number: CN103269213A
Application number: CN201310126011XA
Authority: CN
Inventors: 杜映红
Original assignee: PTSSYSTEM ENGINEERING Co Ltd
Current assignee: Wuxi Optimum Technology Co., Ltd.
Priority date: 2013-04-11
Filing date: 2013-04-11
Publication date: 2013-08-28

Abstract

The invention relates to a clockless buffer trigger, which consists of a logic switch and a logic gate, wherein the clock input end of the trigger is connected with a clock signal by the buffer on the outer part of the trigger, and a plurality of triggers with the similar structure share one outer buffer. According to the clockless buffer trigger disclosed by the invention, the clock buffer in the traditional trigger is omitted, one buffer gate is omitted, the area of the trigger is reduced, and the power consumption of the buffer gate is saved, so that the branches of an SOC (system on a chip) clock tree can be reduced when the SOC is designed so as to achieve a purposes of reducing the power consumption of the SOC clock tree and bringing convenience in wiring.

Description

No clock buffer trigger

Technical field

The present invention relates to a kind of trigger, especially a kind of trigger of inner no buffer.

Background technology

Trigger is logical block the most basic in the digital integrated circuit, and it mainly plays the sequencing control effect, and any one needs the circuit of sequencing control all to be unable to do without the use trigger.Because it is the therefore trigger that carries out the logic state preservation under clock control one or more input end of clock must be arranged.Can use thousands of triggers for an integrated circuit with suitable integrated level, often need a huge clock tree (CLOCK TREE) and drive these triggers.This clock tree and trigger clock internal buffer circuit often will consume about power consumption of about 1/3 of whole integrated circuit.Figure one has provided a typical flip-flop circuit figure.A typical trigger has 4 inverters (Inverter) I1～I4, and 4 logic switch clki and 1 clock buffer B and 1 inverter I0 form.Buffer B can be that giving of positive can be anti-phase.

The purpose that adds a buffer at input end of clock is the waveform (P1 among the figure to trigger clock internal signal, P2 and P3) carry out shaping to reduce extraneous parasitic components (R among the figure and C) to the influence of clock internal, eliminate the noise jamming on the internal clocking waveform.

But, with present integrated circuit (IC) design and manufacture level, as long as when the layout design of chip, accurately make the noise cancellation of making good use of design software and the design of optimizing the clock tree, can guarantee that clock tree signal when being input to the input end of clock of trigger of chip has been cleaner.So buffer B has been not essential.If taken down buffer, each trigger just can be saved a buffered gate so.The power consumption that this area that not only can reduce trigger also can be saved a buffered gate.A chip tends to use thousands of triggers, and the area of saving so and power consumption are very considerable.

Summary of the invention

The technical problem to be solved in the present invention is: propose a kind of no clock buffer flip-flop, it can not influence the situation decline low-power consumption of performance of integrated circuits.

The technical solution adopted in the present invention is: a kind of no clock buffer trigger, described trigger be only by logic switch and gate, and gate is by inverter, compositions such as NAND gate and/or NOR gate, and the input end of clock of trigger does not have buffer; But when a plurality of no time slack clocks are shared towards the trigger of device; The no clock buffer trigger that a plurality of structures are identical shares an external buffer.

For the ease of using, a plurality of trigger of the present invention shares an external buffer and constitutes a module, like this user directly calling module use the present invention, perhaps also can be designed to that a professional component is put into the chip design component library to this structure so that call during chip design.

The invention has the beneficial effects as follows: removed conventional trigger device clock internal buffer, saved a buffered gate, not only reduced the power consumption that the area of trigger has also been saved buffered gate, from the branch that reduces SOC clock tree and then reach the power consumption that reduces the clock tree and the purpose of wiring easily.

Description of drawings

The present invention is further described below in conjunction with drawings and Examples.

Fig. 1 is the circuit diagram of typical trigger in the prior art;

Fig. 2 is circuit diagram of the present invention.

Embodiment

The present invention is further detailed explanation with preferred embodiment by reference to the accompanying drawings now.These accompanying drawings are the schematic diagram of simplification, basic structure of the present invention only is described in a schematic way, so it only show the formation relevant with the present invention.

As shown in Figure 1, a typical trigger has 4 inverters (Inverter) I1～I4, and 4 logic switch clki and 1 clock buffer B and 1 inverter I0 form.Buffer B can be positive, also can be anti-phase, and what provide among Fig. 1 is the positive buffer.The purpose that adds buffer is to make clock signal carry out the shaping of waveform to reduce extraneous parasitic components to the influence of its clock internal before entering trigger.Waveform P1, P2 and P3 provide clock waveform shaping signal.

And shown in Figure 2 be a kind of no clock buffer trigger of the present invention, its trigger itself does not have clock buffer, clock buffer is placed on the outside of trigger.And a plurality of conditionally complete identical triggering devices can share outside same clock buffer.In this case, from the branch that reduces SOC clock tree and then reach the power consumption that reduces the clock tree and the purpose of wiring easily.And the circuit of figure two both can be when chip layout had designed be put trigger and buffering together and is formed a submodule and call then.Also can specialized designs become special client's professional component to put into the chip design component library in order to call during chip design.

Just the specific embodiment of the present invention of describing in the above specification, various not illustrating is construed as limiting flesh and blood of the present invention, the person of an ordinary skill in the technical field after having read specification can to before described embodiment make an amendment or be out of shape, and do not deviate from essence of an invention and scope.

Claims

1. no clock buffer trigger, it is characterized in that: described trigger only is made up of logic switch and gate, and the input end of clock of trigger does not have buffer.

2. no clock buffer trigger as claimed in claim 1 is characterized in that: adopt outside buffer to connect clock signal when a plurality of no clock buffer flip-flops are used in combination, described a plurality of triggers share an external buffer.

3. no clock buffer trigger as claimed in claim 2 is characterized in that: module of the shared external clock buffer formation of described a plurality of triggers.

4. no clock buffer trigger as claimed in claim 2, it is characterized in that: the structure of described a plurality of triggers is identical.

5. no clock buffer trigger as claimed in claim 1, it is characterized in that: described gate comprises inverter, NAND gate and/or NOR gate.