CN112034317A - Oscillation partial discharge voltage locking circuit, partial discharge test system and working method - Google Patents
Oscillation partial discharge voltage locking circuit, partial discharge test system and working method Download PDFInfo
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- CN112034317A CN112034317A CN202010897912.9A CN202010897912A CN112034317A CN 112034317 A CN112034317 A CN 112034317A CN 202010897912 A CN202010897912 A CN 202010897912A CN 112034317 A CN112034317 A CN 112034317A
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- 230000010355 oscillation Effects 0.000 title claims abstract description 81
- 238000012360 testing method Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000011017 operating method Methods 0.000 claims description 2
- 238000005259 measurement Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 description 4
- 230000003534 oscillatory effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/1272—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of cable, line or wire insulation, e.g. using partial discharge measurements
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
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- General Physics & Mathematics (AREA)
- Testing Relating To Insulation (AREA)
Abstract
The invention belongs to the technical field of power equipment measurement, and provides an oscillation partial discharge voltage locking circuit, a partial discharge test system and a working method. The oscillation partial discharge voltage locking circuit comprises a voltage comparator, a first NOR logic gate and a second NOR logic gate. The overvoltage state that appears is locked in the process of increasing the voltage by adopting the voltage comparator and the NOR logic gate circuit, so that testers are reminded, the situation that the oscillation wave partial discharge test equipment is damaged by the increased voltage is avoided, and potential safety hazards are brought to the oscillation wave partial discharge test equipment and the testers.
Description
Technical Field
The invention belongs to the technical field of power equipment measurement, and particularly relates to an oscillation partial discharge voltage locking circuit, a partial discharge test system and a working method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The excellent insulation performance is the basic condition for normal operation of high-voltage equipment and even a power grid system, and insulation degradation or insulation capacity failure is one of the main reasons for faults of the high-voltage electrical equipment and the power grid system. The most sensitive and effective means have been known in the industry to detect the partial discharge characteristics and reflect the dielectric state of the medium.
In the existing oscillatory wave partial discharge test system, a capacitor is charged by adopting direct current high voltage, and a series oscillation loop is formed by using a reactor and the capacitor at the moment of direct current discharge, so that an alternating current damping oscillatory wave is generated on a tested object, and the insulation state of the tested object in an oscillatory state is measured.
The inventor finds that during the process of boosting the direct current high voltage, the voltage overvoltage is caused by the fault of the direct current boosting module or the voltage sampling output circuit. When the overvoltage signal is not locked, the overvoltage voltage can damage the oscillation wave partial discharge test equipment, and potential safety hazards are brought to the oscillation wave partial discharge test equipment and test personnel.
Disclosure of Invention
In order to solve the above problems, a first aspect of the present invention provides an oscillation local discharge voltage locking circuit, which uses a voltage comparator and a nor logic gate circuit to lock an overvoltage state during a voltage boosting process, so as to conveniently remind a tester and prevent the oscillation wave local discharge test equipment from being damaged by the voltage boosting overvoltage.
In order to achieve the purpose, the invention adopts the following technical scheme:
an oscillation partial discharge voltage locking circuit comprises a voltage comparator, a first NOR logic gate and a second NOR logic gate;
two input ends of the voltage comparator are respectively connected with the oscillation partial discharge voltage signal and the reference voltage signal; the output end of the voltage comparator is connected with the first input end of the first NOR logic gate;
the output end of the first NOR logic gate is connected with the first input end of the second NOR logic gate; the second input end of the second NOR logic gate is grounded; and the second input end of the first NOR logic gate is connected with the output end of the second NOR logic gate and is used as the output end of the oscillation partial discharge voltage locking circuit.
In order to solve the above problems, a second aspect of the present invention provides a working method of an oscillation local discharge voltage locking circuit, which can lock an overvoltage state to conveniently remind a tester, and avoid the oscillation wave local discharge test device from being damaged by a boost overvoltage, thereby bringing potential safety hazards to the oscillation wave local discharge test device and the tester.
An operating method of an oscillating partial discharge voltage locking circuit comprises the following steps:
comparing the oscillation partial discharge voltage signal with a reference voltage signal by using a voltage comparator:
when the oscillation partial discharge voltage signal is less than or equal to the reference voltage, the oscillation partial discharge voltage locking circuit is in a default state, a low level is output, and the test voltage is judged to be normal;
when the oscillation partial discharge voltage signal is greater than the reference voltage, the oscillation partial discharge voltage locking circuit fixedly outputs a high level at the moment, and the overvoltage of the test voltage is judged.
In order to solve the above problems, a third aspect of the present invention provides a partial discharge test system, which includes an oscillation partial discharge voltage locking circuit capable of locking an overvoltage state, so as to conveniently remind a tester, and prevent the oscillation wave partial discharge test device from being damaged by a boost overvoltage.
A partial discharge test system comprises the oscillation partial discharge voltage locking circuit.
The invention has the beneficial effects that:
the oscillation partial discharge voltage locking circuit adopts the voltage comparator and the NOR logic gate circuit to lock the overvoltage state in the voltage increasing process, and in the actual test process, when the input voltage is always kept lower than the set reference voltage value in the test voltage continuous output process, the oscillation partial discharge voltage locking circuit judges that the test voltage is normal; even if the instantaneous input voltage is higher than the set reference voltage value in the continuous output process of the test voltage, the oscillation partial discharge voltage locking circuit can always lock the voltage to judge the overvoltage of the test voltage, so that testers are reminded to check the overvoltage phenomenon of the oscillation wave partial discharge test equipment, and the purpose of protecting the oscillation wave partial discharge test equipment and the testers is achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
Fig. 1 is a schematic diagram of an oscillating partial discharge voltage locking circuit according to an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Referring to fig. 1, the oscillating partial discharge voltage locking circuit of the present embodiment includes a voltage comparator, a first nor logic gate, and a second nor logic gate. In fig. 1, the first nor gate is a nor gate a, and the second nor gate is a nor gate B.
The specific connection relationship of the oscillation partial discharge voltage locking circuit of the present embodiment is as follows:
two input ends of the voltage comparator are respectively connected with the oscillation partial discharge voltage signal and the reference voltage signal. The oscillation partial discharge voltage signal is an input voltage and is connected with an In terminal.
The output end of the voltage comparator is connected with the input end 1 of the NOR logic gate A;
the output end 3 of the NOR logic gate A is connected with the input end 5 of the NOR logic gate B; the input end 6 of the NOR logic gate B is grounded, so that the low level can be kept stable;
an input end 2 of the NOR logic gate A is connected with an output end 4 of the NOR logic gate B, and the output end 4 of the NOR logic gate B is used as an output end Out of the oscillating partial discharge voltage locking circuit.
In this embodiment, the initial logic of input 2 of nor gate a is 0. Therefore, the purpose of locking the overvoltage voltage of the oscillation partial discharge can be achieved by more accurately ensuring the whole oscillation partial discharge voltage locking circuit.
In specific implementation, the range of the magnitude value of the oscillation partial discharge voltage signal is 0-5V. The oscillation partial discharge voltage signal is output by a voltage division circuit, and the voltage division circuit is connected with one input end accessed by the voltage comparator.
Correspondingly, the value of the reference voltage signal is less than 5V. The reference voltage signal is stored by a memory, and the memory is connected with the other input end accessed by the voltage comparator.
It should be noted that, in other embodiments, the range of the magnitude value of the oscillating partial discharge voltage signal may also be set to be other ranges, and the reference voltage setting fixed value is smaller than the maximum value of the range of the magnitude value of the oscillating partial discharge voltage signal, which can be set by a person skilled in the art according to specific operating conditions, and will not be described in detail herein.
In another embodiment, the output terminal of the nor logic gate B is also connected to an alarm. Wherein, the alarm can be realized by adopting a buzzer.
When the test voltage is continuously output, even if the instantaneous input voltage is higher than the set reference voltage value, the oscillation partial discharge voltage locking circuit can always lock the voltage and judge that the test voltage is overvoltage. The alarm can remind the tester to check the overvoltage phenomenon of the oscillation wave partial discharge test equipment, so that the oscillation wave partial discharge test equipment and the tester are protected.
It is understood that in other embodiments, the alarm may be implemented by using a light emitting diode, etc., and those skilled in the art may set the alarm according to specific working conditions, which will not be described in detail herein.
The working principle of the oscillation partial discharge voltage locking circuit of the embodiment is as follows:
comparing the oscillation partial discharge voltage signal with a reference voltage signal by using a voltage comparator:
when the oscillation partial discharge voltage signal is less than or equal to the reference voltage, the oscillation partial discharge voltage locking circuit is in a default state, a low level is output, and the test voltage is judged to be normal;
when the oscillation partial discharge voltage signal is greater than the reference voltage, the oscillation partial discharge voltage locking circuit fixedly outputs a high level at the moment, and the overvoltage of the test voltage is judged.
In the process of continuously inputting the oscillation partial discharge test voltage, when the situation that the instantaneous oscillation partial discharge voltage is greater than the reference voltage and the subsequent oscillation partial discharge voltage is less than or equal to the reference voltage occurs, the oscillation partial discharge voltage locking circuit continuously and fixedly outputs a high level and locks a voltage overvoltage signal.
The following description will be given by taking an example that the amplitude value range of the oscillation partial discharge voltage signal is 0-5V, and the value of the reference voltage signal is less than 5V:
firstly, comparing an oscillation partial discharge voltage signal with a reference voltage through a voltage comparator:
when the oscillation partial discharge voltage signal is less than or equal to the reference voltage, the logic of the output end of the voltage comparator is 0, and the logic of the input end 1 of the nor logic gate a is also 0.
Since the input terminal 2 of the nor logic gate a initially has a logic 0, the output terminal 3 of the nor logic gate a outputs a logic 1, i.e. the input terminal 5 of the nor logic gate B inputs a logic 1.
And then the input end 6 of the NOR gate B is combined to input logic 0, and the output end 4 of the NOR gate B outputs logic 0. At the moment, the oscillation partial discharge voltage locking circuit is in a default state, a low level of 0V is output, and the test voltage is judged to be normal. When the output end of the oscillation partial discharge voltage locking circuit is connected with a buzzer, the buzzer does not give an alarm.
When the oscillating partial discharge voltage signal is greater than the reference voltage, the logic of the output end of the voltage comparator is 1, that is, the input end 1 of the nor logic gate a inputs logic 1.
Since the input terminal 2 of the nor logic gate a initially has a logic 0, the output terminal 3 of the nor logic gate a outputs a logic 0, i.e. the input terminal 5 of the nor logic gate B inputs a logic 0.
And then the input end 6 of the NOR gate B is combined to input logic 0, and the output end 4 of the NOR gate B outputs logic 1. At the moment, the oscillation partial discharge voltage locking circuit fixedly outputs 5V voltage, and the overvoltage of the test voltage is judged. When the output end of the oscillation partial discharge voltage locking circuit is connected with a buzzer, the buzzer gives an alarm.
In the process of continuously inputting the test voltage, when the instant oscillation partial discharge voltage signal is larger than the reference voltage and the subsequent oscillation partial discharge voltage signal is smaller than or equal to the reference voltage, the output end 4 of the NOR logic gate B outputs logic 1, and the input end 2 of the NOR logic gate A inputs logic 1.
In combination with the output of the voltage comparator being logic 0, i.e. input 1 of nor gate a inputs logic 0, output 3 of nor gate a outputs logic 0, and input 5 of nor gate B inputs logic 0.
Since the input terminal 6 of the NOR gate B inputs logic 0, the output terminal 4 of the NOR gate B outputs logic 1. At the moment, the oscillation partial discharge voltage locking circuit continuously and fixedly outputs 5V voltage, and the voltage overvoltage signal is locked. When the output end of the oscillation partial discharge voltage locking circuit is connected with a buzzer, the buzzer continuously alarms and does not release the alarm state.
In the oscillation partial discharge voltage locking circuit, a voltage comparator and a NOR logic gate circuit are adopted to lock an overvoltage state in a voltage increasing process, and in an actual test process, when an input voltage is always kept lower than a set reference voltage value in a test voltage continuous output process, the oscillation partial discharge voltage locking circuit judges that the test voltage is normal; even if the instantaneous input voltage is higher than the set reference voltage value in the continuous output process of the test voltage, the oscillation partial discharge voltage locking circuit can always lock the voltage to judge the overvoltage of the test voltage, so that testers are reminded to check the overvoltage phenomenon of the oscillation wave partial discharge test equipment, and the purpose of protecting the oscillation wave partial discharge test equipment and the testers is achieved.
In another embodiment, a partial discharge test system is further provided, which includes the oscillation partial discharge voltage locking circuit described above.
The oscillating partial discharge voltage locking circuit is specifically shown in fig. 1, and will not be described here.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An oscillation partial discharge voltage locking circuit is characterized by comprising a voltage comparator, a first NOR logic gate and a second NOR logic gate;
two input ends of the voltage comparator are respectively connected with the oscillation partial discharge voltage signal and the reference voltage signal; the output end of the voltage comparator is connected with the first input end of the first NOR logic gate;
the output end of the first NOR logic gate is connected with the first input end of the second NOR logic gate; the second input end of the second NOR logic gate is grounded; and the second input end of the first NOR logic gate is connected with the output end of the second NOR logic gate and is used as the output end of the oscillation partial discharge voltage locking circuit.
2. The oscillating partial discharge voltage locking circuit of claim 1, wherein the initial logic of the second input of the first nor logic gate is 0.
3. The oscillating partial discharge voltage locking circuit according to claim 1, wherein the oscillating partial discharge voltage signal has a magnitude in a range of 0 to 5V.
4. The oscillating partial discharge voltage locking circuit of claim 3, wherein the reference voltage signal has a value of less than 5V.
5. The oscillating partial discharge voltage locking circuit of claim 1, wherein the oscillating partial discharge voltage signal is output by a voltage divider circuit coupled to an input to which the voltage comparator is coupled.
6. The oscillating partial discharge voltage locking circuit of claim 1, wherein the reference voltage signal is stored by a memory coupled to another input terminal to which the voltage comparator is coupled.
7. The oscillating partial discharge voltage lock circuit of claim 1, wherein the output of the second nor logic gate is further coupled to an alarm.
8. A method of operating an oscillating partial discharge voltage lock circuit according to any of claims 1 to 7, comprising:
comparing the oscillation partial discharge voltage signal with a reference voltage signal by using a voltage comparator:
when the oscillation partial discharge voltage signal is less than or equal to the reference voltage, the oscillation partial discharge voltage locking circuit is in a default state, a low level is output, and the test voltage is judged to be normal;
when the oscillation partial discharge voltage signal is greater than the reference voltage, the oscillation partial discharge voltage locking circuit fixedly outputs a high level at the moment, and the overvoltage of the test voltage is judged.
9. The operating method of the oscillation partial discharge voltage locking circuit according to claim 8, wherein in the process of the continuous input of the oscillation partial discharge test voltage, when the instantaneous oscillation partial discharge voltage is larger than the reference voltage and the subsequent oscillation partial discharge voltage is smaller than or equal to the reference voltage, the oscillation partial discharge voltage locking circuit continuously and fixedly outputs a high level to lock the voltage overvoltage signal.
10. A partial discharge test system comprising an oscillating partial discharge voltage locking circuit according to any one of claims 1 to 7.
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| CN202010897912.9A CN112034317B (en) | 2020-08-31 | 2020-08-31 | Oscillating partial discharge voltage locking circuit, partial discharge test system and working method |
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| CN112034317B (en) | 2023-11-28 |
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