CN104955226A - Combined protective optical excitation gate driving system based on logic protection amplifying circuit - Google Patents
Combined protective optical excitation gate driving system based on logic protection amplifying circuit Download PDFInfo
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- CN104955226A CN104955226A CN201510316959.0A CN201510316959A CN104955226A CN 104955226 A CN104955226 A CN 104955226A CN 201510316959 A CN201510316959 A CN 201510316959A CN 104955226 A CN104955226 A CN 104955226A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a combined protective optical excitation gate driving system based on a logic protection amplifying circuit. The system mainly comprises a driver chip M, a self-locking optical excitation circuit, a driving circuit and an in-phase alternating signal amplification circuit, wherein the driving circuit is connected with the driver chip M, and the in-phase alternating signal amplification circuit is serially connected between the driver chip M and the self-locking optical excitation circuit. The in-phase alternating signal amplification circuit comprises a power amplifier P1, a resistor R4 and the like; one end of the resistor R4 is connected with a VCC (virtual channel connection) pin of the driver chip M, and the other end of the resistor R4 is connected with an anode input end of the power amplifier P1; the logic protection amplifying circuit is serially connected between the power amplifier P1 and an INP (impulse noise protection) pin of the driver chip M; a combined protection circuit is arranged on the driver chip M. The system has the advantages that circuit power supply can be quickly cut off when operating temperatures of input currents or circuits are overhigh, the circuit is protected from damages caused by current impact or long-term high-temperature operation, and accordingly service life of the circuit is greatly improved; in addition, related functions of the driver chip M can be automatically excited according to external light conditions, and extra starting devices are not needed, so that power consumption is low.
Description
Technical field
The present invention relates to a kind of LED drive circuit, specifically refer to the complex protection type optical excitation raster data model system of a kind of logic-based protection amplifying circuit.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Summary of the invention
The object of the invention is to the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit; a kind of reasonable in design is provided; can effectively reduce energy consumption and current noise, obviously shorten the complex protection type optical excitation raster data model system of a kind of logic-based protection amplifying circuit of start-up time.
Object of the present invention is achieved through the following technical solutions:
The complex protection type optical excitation raster data model system of logic-based protection amplifying circuit, primarily of driving chip M, self-locking optical excitation circuit, the drive circuit be connected with this driving chip M, and be serially connected in homophase AC signal amplifying circuit between driving chip M and self-locking energizing circuit and form; Described homophase AC signal amplifying circuit is by power amplifier P1, the resistance R4 that one end is connected with the VCC pin of driving chip M, the other end is connected with the electrode input end of power amplifier P1, the resistance R5 that one end is connected with the negative input of power amplifier P1, the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the electrode input end of power amplifier P1, the polar capacitor C5 of negative pole external power supply forms.Meanwhile, between power amplifier P1 and the INP pin of driving chip M, be also serially connected with virtual protection amplifying circuit, driving chip M is provided with compound protective circuit, described virtual protection amplifying circuit is primarily of power amplifier P2, power amplifier P3, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC5 after resistance R9, one end is connected with the negative input of NAND gate IC4, the resistance R6 that the other end is connected with the electrode input end of power amplifier P2, be serially connected in the resistance R7 between the negative input of power amplifier P2 and output, one end is connected with the output of NAND gate IC4, the resistance R8 that the other end is connected with the negative input of power amplifier P3, be serially connected in the polar capacitor C7 between the electrode input end of power amplifier P3 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C8 that voltage stabilizing didoe D2 is connected with the output of power amplifier P2 after resistance R10, P pole is connected with the output of power amplifier P3, N pole is in turn through diode D3 that resistance R12 is connected with the tie point of resistance R10 with voltage stabilizing didoe D2 after resistance R11, and N pole is connected with the negative pole of electric capacity C8, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R12 with diode D3 forms, the electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P2, the electrode input end of the output NAND gate IC5 of power amplifier P3 is connected, and its electrode input end is then connected with the output of power amplifier P2, the positive pole of described polar capacitor C6 is connected with the output of power amplifier P1, and resistance R12 is then connected with the INP pin of driving chip M with the tie point of resistance R11.
Described compound protective circuit is by incoming line, time-base integrated circuit Q101, triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, one end is connected with the emitter of triode VT101, the resistance R101 that the other end is connected with the collector electrode of triode VT103, one end is connected with the base stage of triode VT101, the other end is connected with the emitter of triode VT104, the slide rheostat RP101 that sliding end is connected with the base stage of triode VT103, N pole is connected with the collector electrode of triode VT101, the diode D101 that P pole is connected with the base stage of triode VT102, the relay K 101 in parallel with diode D101, one end is connected with the P pole of diode D101, the resistance R103 that the other end is connected with the base stage of triode VT105, P pole is connected with the collector electrode of triode VT101 after resistance R102, the diode D103 that N pole is connected with the Discharge pin of time-base integrated circuit Q101, one end is connected with the N pole of diode D103, the resistance R104 that the other end is connected with the collector electrode of triode VT105, P pole is connected with the N pole of diode D103, the diode D102 that N pole is connected with the GND pin of time-base integrated circuit Q101, one end is connected with the P pole of diode D103, the other end is connected with the N pole of diode D102, the slide rheostat RP102 that sliding end is connected with the Control voltage pin of time-base integrated circuit Q101, P pole ground connection, the diode D104 that N pole is connected with the P pole of diode D103, minus earth, the electric capacity C101 that positive pole is connected with Thresshold pin with the Trigger pin of time-base integrated circuit Q101 simultaneously, the thermistor RT101 in parallel with electric capacity C101, and one end is connected with the N pole of diode D104, the slide rheostat RP103 that the other end is connected with the positive pole of electric capacity C101 after resistance R105 forms, wherein, the collector electrode of triode VT101 is connected with input circuit, the base stage of triode VT101 is connected with the emitter of triode VT103 with the emitter of triode VT102 simultaneously, the collector electrode of triode VT101 is also connected with the collector electrode of triode VT102, the emitter of triode VT101 is also connected with the collector electrode of triode VT104, the grounded emitter of triode VT104, the base stage of triode VT104 is connected with the collector electrode of triode VT105, the grounded emitter of triode VT105, the GND pin ground connection of time-base integrated circuit Q101, the N pole of diode D104 is connected with Reset pin with the Vcc pin of time-base integrated circuit Q101 simultaneously, the normally closed electric shock switch S 101 of described relay K 101 is arranged on incoming line, the output of incoming line is connected with the Vcc pin of driving chip M.
Further, described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, one end is connected with the electrode input end of power amplifier P1, the photocell CDS of other end ground connection after potentiometer R2, the resistance R1 that one end is connected with the electrode input end of power amplifier P1, the negative input of other end AND OR NOT gate IC2 is connected, and the electric capacity C1 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected, and the output of the output of NOR gate IC3 then power amplifier P1 is connected; The output of the other end of described resistance R5 then AND OR NOT gate IC2 is connected.
Described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C3 and electric capacity C4 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use, described driving chip M is LTC4440A integrated chip.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention can excite the correlation function of driving chip M automatically according to outside illumination condition, and without the need to increasing extra starting drive, therefore its power consumption is lower.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present invention, therefore its start-up time is extremely short.
(3) the present invention effectively can avoid external electromagnetic interference, can reduce current noise significantly.
(4) be provided with homophase AC signal amplifying circuit in the present invention, therefore can guarantee that the intensity of pulse signal can not decay, thus guarantee stable performance.
(5) the present invention adopts compound protective circuit; the power supply of circuit can be cut off rapidly when the operating temperature of input current or circuit is too high; avoid circuit be subject to the impact of electric current or at high temperature run the damage caused for a long time, substantially increase the useful life of circuit.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is virtual protection amplification circuit structure schematic diagram of the present invention.
Fig. 3 is the circuit diagram of compound protective circuit of the present invention.
Description of reference numerals:
10, compound protective circuit; 20, virtual protection amplifying circuit.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1; the present invention is primarily of driving chip M; self-locking optical excitation circuit; the drive circuit be connected with driving chip M; be arranged on the homophase AC signal amplifying circuit between driving chip M and self-locking energizing circuit; be serially connected in the virtual protection amplifying circuit 20 between driving chip M and homophase AC signal amplifying circuit, and the compound protective circuit 10 arranged on driving chip M forms.
The pulse signal that described homophase AC signal amplifying circuit is used for self-locking energizing circuit lock produces amplifies, to avoid signal attenuation.It is by power amplifier P1, and resistance R4, resistance R5 and polar capacitor C5 form.During connection, one end of resistance R4 is connected with the VCC pin of driving chip M, and its other end is connected with the electrode input end of power amplifier P1; One end of resistance R5 is connected with the negative input of power amplifier P1, and its other end is then connected with self-locking optical excitation circuit; The positive pole of polar capacitor C5 is then connected with the electrode input end of power amplifier P1, its negative pole external power supply.
For guaranteeing that power amplifier P1 can normally work, the supply voltage that the negative pole of this polar capacitor C5 is external needs to be between 6 ~ 12V.Meanwhile, for guaranteeing result of use, the high-frequency N-channel MOS FET grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
Wherein, described self-locking optical excitation circuit is then by NOR gate IC1, and NOR gate IC2, NOR gate IC3, photocell CDS, resistance R1, potentiometer R2 and electric capacity C1 form.During connection, one end of photocell CDS is connected with the electrode input end of power amplifier P1, and its other end is ground connection after potentiometer R2.One end of resistance R1 is connected with the electrode input end of power amplifier P1, and the negative input of its other end AND OR NOT gate IC2 is connected; The electrode input end of the positive pole AND OR NOT gate IC3 of electric capacity C1 is connected, and the output of its negative pole then AND OR NOT gate IC3 is connected.
The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected.The negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected, and the output of the output of NOR gate IC3 then power amplifier P1 is connected.
The output of the other end of described resistance R5 then AND OR NOT gate IC2 is connected, and the pulse signal that namely output of NOR gate IC2 exports can be input to the negative input of power amplifier P1 after resistance R5.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C2, resistance R3, electric capacity C3, electric capacity C4 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C2 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.For guaranteeing the normal operation of driving chip M, its VCC holds the voltage needing external+12V.
Resistance R3 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C3 and electric capacity C4 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q1 also needs the direct voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1.Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present invention.According to the situation of reality, user can only select any one or several port of these four outputs to use.
The structure of virtual protection amplifying circuit 20 as shown in Figure 2, it is primarily of power amplifier P2, power amplifier P3, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC5 after resistance R9, one end is connected with the negative input of NAND gate IC4, the resistance R6 that the other end is connected with the electrode input end of power amplifier P2, be serially connected in the resistance R7 between the negative input of power amplifier P2 and output, one end is connected with the output of NAND gate IC4, the resistance R8 that the other end is connected with the negative input of power amplifier P3, be serially connected in the polar capacitor C7 between the electrode input end of power amplifier P3 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C8 that voltage stabilizing didoe D2 is connected with the output of power amplifier P2 after resistance R10, P pole is connected with the output of power amplifier P3, N pole is in turn through diode D3 that resistance R12 is connected with the tie point of resistance R10 with voltage stabilizing didoe D2 after resistance R11, and N pole is connected with the negative pole of electric capacity C8, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R12 with diode D3 forms.
The electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P2; The electrode input end of the output NAND gate IC5 of power amplifier P3 is connected, and its electrode input end is then connected with the output of power amplifier P2.During connection, the positive pole of described polar capacitor C6 is connected with the output of power amplifier P1, and resistance R12 is then connected with the INP pin of driving chip M with the tie point of resistance R11.
As shown in Figure 3, described compound protective circuit 10 by incoming line, time-base integrated circuit Q101, triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, resistance R101, resistance R102, resistance R103, resistance R104, resistance R105, relay K 101, diode D101, diode D102, diode D103, diode D104, electric capacity C101;
During connection, one end of resistance R101 is connected with the emitter of triode VT101, the other end is connected with the collector electrode of triode VT103, one end of slide rheostat RP101 is connected with the base stage of triode VT101, the other end is connected with the emitter of triode VT104, sliding end is connected with the base stage of triode VT103, the N pole of diode D101 is connected with the collector electrode of triode VT101, P pole is connected with the base stage of triode VT102, relay K 101 is in parallel with diode D101, one end of resistance R103 is connected with the P pole of diode D101, the other end is connected with the base stage of triode VT105, the P pole of diode D103 is connected with the collector electrode of triode VT101 after resistance R102, N pole is connected with the Discharge pin of time-base integrated circuit Q101, one end of resistance R104 is connected with the N pole of diode D103, the other end is connected with the collector electrode of triode VT105, the P pole of diode D102 is connected with the N pole of diode D103, N pole is connected with the GND pin of time-base integrated circuit Q101, one end of slide rheostat RP102 is connected with the P pole of diode D103, the other end is connected with the N pole of diode D102, sliding end is connected with the Control voltage pin of time-base integrated circuit Q101, the P pole ground connection of diode D104, N pole is connected with the P pole of diode D103, the minus earth of electric capacity C101, positive pole is connected with Thresshold pin with the Trigger pin of time-base integrated circuit Q101 simultaneously, thermistor RT101 is in parallel with electric capacity C101, one end of slide rheostat RP103 is connected with the N pole of diode D104, the other end is connected with the positive pole of electric capacity C101 after resistance R105, wherein, the collector electrode of triode VT101 is connected with incoming line, the base stage of triode VT101 is connected with the emitter of triode VT103 with the emitter of triode VT102 simultaneously, the collector electrode of triode VT101 is also connected with the collector electrode of triode VT102, the emitter of triode VT101 is also connected with the collector electrode of triode VT104, the grounded emitter of triode VT104, the base stage of triode VT104 is connected with the collector electrode of triode VT105, the grounded emitter of triode VT105, the GND pin ground connection of time-base integrated circuit Q101, the N pole of diode D104 is connected with Reset pin with the Vcc pin of time-base integrated circuit Q101 simultaneously, the normally closed electric shock switch S 101 of described relay K 101 is arranged on incoming line, the output of incoming line is connected with the Vcc pin of driving chip M.When the electric current of input or the overall operation temperature of circuit exceed preset value, relay K 101 obtains the electric normally-closed contact switch S 101 that makes and disconnects, thus completes the power-off of whole circuit.
As mentioned above, just the present invention can well be realized.
Claims (4)
1. the complex protection type optical excitation raster data model system of logic-based protection amplifying circuit, primarily of driving chip M, self-locking optical excitation circuit, the drive circuit be connected with this driving chip M, and be serially connected in homophase AC signal amplifying circuit between driving chip M and self-locking energizing circuit and form, described homophase AC signal amplifying circuit is by power amplifier P1, one end is connected with the VCC pin of driving chip M, the resistance R4 that the other end is connected with the electrode input end of power amplifier P1, one end is connected with the negative input of power amplifier P1, the resistance R5 that the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the electrode input end of power amplifier P1, the polar capacitor C5 of negative pole external power supply forms, it is characterized in that, virtual protection amplifying circuit (20) is also serially connected with between power amplifier P1 and the INP pin of driving chip M, driving chip M is provided with compound protective circuit (10), described virtual protection amplifying circuit (20) is primarily of power amplifier P2, power amplifier P3, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC5 after resistance R9, one end is connected with the negative input of NAND gate IC4, the resistance R6 that the other end is connected with the electrode input end of power amplifier P2, be serially connected in the resistance R7 between the negative input of power amplifier P2 and output, one end is connected with the output of NAND gate IC4, the resistance R8 that the other end is connected with the negative input of power amplifier P3, be serially connected in the polar capacitor C7 between the electrode input end of power amplifier P3 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C8 that voltage stabilizing didoe D2 is connected with the output of power amplifier P2 after resistance R10, P pole is connected with the output of power amplifier P3, N pole is in turn through diode D3 that resistance R12 is connected with the tie point of resistance R10 with voltage stabilizing didoe D2 after resistance R11, and N pole is connected with the negative pole of electric capacity C8, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R12 with diode D3 forms, the electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P2, the electrode input end of the output NAND gate IC5 of power amplifier P3 is connected, and its electrode input end is then connected with the output of power amplifier P2, the positive pole of described polar capacitor C6 is connected with the output of power amplifier P1, and resistance R12 is then connected with the INP pin of driving chip M with the tie point of resistance R11,
Described compound protective circuit (10) is by incoming line, time-base integrated circuit Q101, triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, one end is connected with the emitter of triode VT101, the resistance R101 that the other end is connected with the collector electrode of triode VT103, one end is connected with the base stage of triode VT101, the other end is connected with the emitter of triode VT104, the slide rheostat RP101 that sliding end is connected with the base stage of triode VT103, N pole is connected with the collector electrode of triode VT101, the diode D101 that P pole is connected with the base stage of triode VT102, the relay K 101 in parallel with diode D101, one end is connected with the P pole of diode D101, the resistance R103 that the other end is connected with the base stage of triode VT105, P pole is connected with the collector electrode of triode VT101 after resistance R102, the diode D103 that N pole is connected with the Discharge pin of time-base integrated circuit Q101, one end is connected with the N pole of diode D103, the resistance R104 that the other end is connected with the collector electrode of triode VT105, P pole is connected with the N pole of diode D103, the diode D102 that N pole is connected with the GND pin of time-base integrated circuit Q101, one end is connected with the P pole of diode D103, the other end is connected with the N pole of diode D102, the slide rheostat RP102 that sliding end is connected with the Control voltage pin of time-base integrated circuit Q101, P pole ground connection, the diode D104 that N pole is connected with the P pole of diode D103, minus earth, the electric capacity C101 that positive pole is connected with Thresshold pin with the Trigger pin of time-base integrated circuit Q101 simultaneously, the thermistor RT101 in parallel with electric capacity C101, and one end is connected with the N pole of diode D104, the slide rheostat RP103 that the other end is connected with the positive pole of electric capacity C101 after resistance R105 forms, wherein, the collector electrode of triode VT101 is connected with input circuit, the base stage of triode VT101 is connected with the emitter of triode VT103 with the emitter of triode VT102 simultaneously, the collector electrode of triode VT101 is also connected with the collector electrode of triode VT102, the emitter of triode VT101 is also connected with the collector electrode of triode VT104, the grounded emitter of triode VT104, the base stage of triode VT104 is connected with the collector electrode of triode VT105, the grounded emitter of triode VT105, the GND pin ground connection of time-base integrated circuit Q101, the N pole of diode D104 is connected with Reset pin with the Vcc pin of time-base integrated circuit Q101 simultaneously, the normally closed electric shock switch S 101 of described relay K 101 is arranged on incoming line, the output of incoming line is connected with the Vcc pin of driving chip M.
2. the complex protection type optical excitation raster data model system of logic-based protection amplifying circuit according to claim 1, it is characterized in that, described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, one end is connected with the electrode input end of power amplifier P1, the photocell CDS of other end ground connection after potentiometer R2, one end is connected with the electrode input end of power amplifier P1, the resistance R1 that the negative input of other end AND OR NOT gate IC2 is connected, and the electric capacity C1 be serially connected between the electrode input end of NOR gate IC3 and output forms, the electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected, the negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected, and the output of the output of NOR gate IC3 then power amplifier P1 is connected, the output of the other end of described resistance R5 then AND OR NOT gate IC2 is connected.
3. the complex protection type optical excitation raster data model system of logic-based protection amplifying circuit according to claim 2, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C3 and electric capacity C4 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
4. the complex protection type optical excitation raster data model system of logic-based protection amplifying circuit according to claim 3, it is characterized in that, described driving chip M is LTC4440A integrated chip.
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| CN201510316959.0A CN104955226A (en) | 2014-11-27 | 2015-06-10 | Combined protective optical excitation gate driving system based on logic protection amplifying circuit |
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| CN201410699796.4A CN104411054A (en) | 2014-11-27 | 2014-11-27 | Same-phase alternating-current signal amplification type optical excitation gate drive system based on logic protection amplification circuit |
| CN2014106997964 | 2014-11-27 | ||
| CN201510316959.0A CN104955226A (en) | 2014-11-27 | 2015-06-10 | Combined protective optical excitation gate driving system based on logic protection amplifying circuit |
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| CN201510316959.0A Pending CN104955226A (en) | 2014-11-27 | 2015-06-10 | Combined protective optical excitation gate driving system based on logic protection amplifying circuit |
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| CN112034317A (en) * | 2020-08-31 | 2020-12-04 | 国网山东省电力公司电力科学研究院 | Oscillation partial discharge voltage locking circuit, partial discharge test system and working method |
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| CN104442563A (en) * | 2014-11-27 | 2015-03-25 | 成都措普科技有限公司 | Automobile safety-type double-power amplification lamp alarm system |
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2014
- 2014-11-27 CN CN201410699796.4A patent/CN104411054A/en active Pending
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2015
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112034317A (en) * | 2020-08-31 | 2020-12-04 | 国网山东省电力公司电力科学研究院 | Oscillation partial discharge voltage locking circuit, partial discharge test system and working method |
| CN112034317B (en) * | 2020-08-31 | 2023-11-28 | 国网山东省电力公司电力科学研究院 | Oscillating partial discharge voltage locking circuit, partial discharge test system and working method |
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| CN104411054A (en) | 2015-03-11 |
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