CN104869723A - Hybrid energy-saving grid drive system based on gate drive - Google Patents
Hybrid energy-saving grid drive system based on gate drive Download PDFInfo
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- CN104869723A CN104869723A CN201510307125.3A CN201510307125A CN104869723A CN 104869723 A CN104869723 A CN 104869723A CN 201510307125 A CN201510307125 A CN 201510307125A CN 104869723 A CN104869723 A CN 104869723A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention discloses a hybrid energy-saving grid drive system based on gate drive, and the system consists of a drive chip M, a drive circuit connected with the drive chip M, an in-phase AC signal amplification circuit connected with the drive chip M, a self-locking optical excitation circuit connected with the in-phase AC signal amplification circuit, a bootstrapping circuit connected with the self-locking optical excitation circuit, a power amplification circuit disposed between the self-locking optical excitation circuit and the drive chip M, and a logic amplification circuit of a light-beam excitation type, wherein the logic amplification circuit of a light-beam excitation type is connected with the bootstrapping circuit, the self-locking optical excitation circuit and the power amplification circuit. The system is characterized in that a gate drive circuit is connected in series between the logic amplification circuit of a light-beam excitation type and the drive circuit; the system can automatically excites the relative functions of the drive chip M according to the conditions of external illumination, does not need an additional starting device, and is lower in power consumption; meanwhile, through the effect of the gate drive circuit, the system enables the starting time to be one fourth of the starting time of a conventional grid drive circuit.
Description
Technical field
The present invention relates to a kind of LED drive circuit, specifically refer to the energy-conservation raster data model system of mixed type based on gate-drive.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But the widely used gate driver circuit of current people, due to the irrationality of its project organization, result in the existence of current gate driver circuit and drives effect bad, the defects such as start-up time is longer.
Summary of the invention
The object of the invention is to overcome gate driver circuit existence at present drives effect bad, and the defect that start-up time is longer, provides a kind of energy-conservation raster data model of the mixed type based on gate-drive system of reasonable in design.
Object of the present invention is achieved through the following technical solutions: the energy-conservation raster data model system of the mixed type based on gate-drive, it comprises driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, be arranged on the power amplification circuit between self-locking optical excitation circuit and driving chip M, respectively with boostrap circuit, the beam excitation formula logic amplifying circuit that self-locking optical excitation circuit is connected with power amplification circuit, in order to reach object of the present invention, the present invention is also serially connected with gate drive circuit between beam excitation formula logic amplifying circuit and drive circuit.
Further, described gate drive circuit is by triode Q5, triode Q6, field effect transistor MOS1, unidirectional thyristor D6, negative pole is connected with the base stage of triode Q6, the electric capacity C16 that positive pole is then connected with beam excitation formula logic amplifying circuit, the resistance R24 be in parallel with electric capacity C16, one end is connected with the positive pole of electric capacity C16, the resistance R23 of ground connection while the other end is then connected with the emitter of triode Q6, one end is connected with the collector electrode of triode Q5, the resistance R22 that the other end is then connected with the positive pole of electric capacity C16, be serially connected in the resistance R25 between the collector electrode of triode Q5 and base stage, N pole is connected with the collector electrode of triode Q6, the diode D5 that P pole is then connected with the grid of field effect transistor MOS1 after resistance R26, positive pole is connected with the emitter of triode Q6, the electric capacity C17 that negative pole is then connected with the grid of field effect transistor MOS1 after resistance R27, positive pole is connected with the negative pole of electric capacity C17, the electric capacity C18 that negative pole is then connected with the P pole of unidirectional thyristor D6, and positive pole is connected with the control pole of unidirectional thyristor D6, the electric capacity C19 that negative pole is then connected with drive circuit forms, the base stage of described triode Q5 is connected with the collector electrode of triode Q6, its emitter is then connected with the P pole of diode D5, grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D6.
Described beam excitation formula logic amplifying circuit is by power amplifier P4, NAND gate IC4, NAND gate IC5, NAND gate IC6, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5, the electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with power amplification circuit, and its negative input is then connected with the positive pole of electric capacity C16, the output of power amplifier P4 is then connected with self-locking optical excitation circuit, and its in-phase end is connected with boostrap circuit.
Described power amplification circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and end of oppisite phase and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and in-phase end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the in-phase end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the end of oppisite phase of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the end of oppisite phase of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the end of oppisite phase of described power amplifier P1 is connected with the in-phase end of power amplifier P2, and its in-phase end is connected with self-locking optical excitation circuit, the end of oppisite phase of power amplifier P2 is connected with the output of NAND gate IC6, the output of power amplifier P3 is then connected with the TD pin of driving chip M.
Described homophase AC signal amplifying circuit is by power amplifier P, one end is connected with the VCC pin of driving chip M, the resistance R7 that the other end is connected with the in-phase end of power amplifier P, one end is connected with the end of oppisite phase of power amplifier P, the resistance R6 that the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the in-phase end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M and self-locking optical excitation circuit respectively, its in-phase end is also connected with self-locking optical excitation circuit.
Described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, the photocell CDS that one end is connected with the in-phase end of power amplifier P, the other end is connected with the output of power amplifier P4 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described NOR gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the in-phase end of power amplifier P1, the output of NOR gate IC3 is then connected with the output of power amplifier P; The output of described NOR gate IC2 is also connected with the end of oppisite phase of power amplifier P after resistance R6.
Described boostrap circuit is by field effect transistor MOS, the resistance R4 that one end is connected with the source electrode of field effect transistor MOS, the other end is connected with the in-phase end of power amplifier P4, the polar capacitor C1 that negative pole is connected with the grid of field effect transistor MOS, positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, the polar capacitor C2 that positive pole is connected with the positive pole of polar capacitor C1, the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms; The drain electrode of described field effect transistor MOS is connected with the tie point of resistance R7 with photocell CDS.
Described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode forms through electric capacity C6 ground connection and transistor Q1 that emitter is connected with the negative pole of electric capacity C19 after electric capacity C7 in turn; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, and its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and its collector electrode then connects+6V voltage, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
In order to ensure result of use, described driving chip M is preferably LTC4440A integrated chip to realize.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention can excite the correlation function of driving chip M automatically according to outside illumination condition, and without the need to increasing extra starting drive, therefore its power consumption is lower.
(2) the present invention is by the effect of gate drive circuit, and make to be only its start-up time 1/4 of conventional gate drive circuit start-up time, its start-up time is extremely short.
(3) the present invention adopts boostrap circuit to provide control signal for self-locking optical excitation circuit and driving chip, therefore has very high input impedance, can guarantee the stable performance of whole circuit
(4) the present invention effectively can avoid external electromagnetic interference, can reduce current noise significantly.
(5) be provided with homophase AC signal amplifying circuit in the present invention, therefore can guarantee that the intensity of pulse signal can not decay, thus guarantee stable performance.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is power amplification circuit structural representation of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention includes driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, be arranged on the power amplification circuit between self-locking optical excitation circuit and driving chip M, respectively with boostrap circuit, the beam excitation formula logic amplifying circuit that self-locking optical excitation circuit is connected with power amplification circuit, in order to reach object of the present invention, the present invention is also serially connected with gate drive circuit between beam excitation formula logic amplifying circuit and drive circuit.
For guaranteeing result of use, the high-frequency N-channel MOS FET grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
The structure of described power amplification circuit as shown in Figure 2, namely it is by power amplifier P1, power amplifier P2, power amplifier P3, triode Q2, triode Q3, triode Q4, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and end of oppisite phase, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and in-phase end, and resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, electric capacity C10, electric capacity C11, electric capacity C12 and diode D2 form.
Wherein, described one-level RC filtered electrical routing resistance R9 and electric capacity C8 is formed in parallel, namely between resistance R9 and the electric capacity C8 end of oppisite phase that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R10 and electric capacity C9, namely between resistance R10 and the electric capacity C9 in-phase end that is all serially connected in power amplifier P2 and output.Meanwhile, the end of oppisite phase of power amplifier P1 is also connected with the in-phase end of power amplifier P2.
The base stage of triode Q2 is connected with the output of power amplifier P1, and its collector electrode is connected with the in-phase end of power amplifier P3 after resistance R11, and its emitter is then connected with the base stage of triode Q3; The collector electrode of triode Q3 is connected with the end of oppisite phase of power amplifier P3 after resistance R12, meanwhile, and the collector electrode also external+10V voltage of this triode Q3.
The base stage of triode Q4 is connected with the output of power amplifier P2 after resistance R13, and its collector electrode is then connected with the base stage of triode Q3 after resistance R16.Electric capacity C11 is then in parallel with resistance R13, and for guaranteeing effect, this electric capacity C11 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C11 is connected with the base stage of triode Q4, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C10 is connected with the end of oppisite phase of power amplifier P3, and its negative pole is then connected with the emitter of triode Q3.Meanwhile, the negative pole of this electric capacity C10 and the equal ground connection of emitter of triode Q3.
One end of resistance R14 is connected with the base stage of triode Q4, the voltage of the external-4V of its other end; And one end of resistance R15 is connected with the emitter of triode Q4, the voltage of its other end then external equally-4V.Electric capacity C12 is then in parallel with resistance R15.Equally, described electric capacity C10 and electric capacity C12 also all adopts electrochemical capacitor to realize.
The N pole of described diode D2 is connected with the collector electrode of triode Q2, and its P pole is at the voltage of external-4V.Simultaneously, the output of this power amplifier P3 will be connected with the TD pin of driving chip M, the in-phase end of power amplifier P1 then needs to be connected with self-locking optical excitation circuit, and the end of oppisite phase of power amplifier P2 then needs to be connected with beam excitation formula logic amplifying circuit.
For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C8 and electric capacity C9 all preferentially adopts patch capacitor to realize.And the resistance of resistance R9, resistance R10 is 10K Ω, the resistance of resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16 is 20K Ω.
Described homophase AC signal amplifying circuit is by power amplifier P, and resistance R7, resistance R6 and polar capacitor C4 form.During connection, one end of resistance R7 is connected with the VCC pin of driving chip M, and its other end is connected with the in-phase end of power amplifier P; And one end of resistance R6 is connected with the end of oppisite phase of power amplifier P, its other end is connected with self-locking optical excitation circuit.The positive pole of polar capacitor C4 is connected with the in-phase end of power amplifier P, its negative pole external power supply Vin.The output of described power amplifier P is connected with the INP pin of driving chip M and self-locking optical excitation circuit respectively, its in-phase end is also connected with self-locking optical excitation circuit, for guaranteeing that power amplifier P can normally work, the magnitude of voltage of this external power supply Vin needs to be 6 ~ 12V.
Described beam excitation formula logic amplifying circuit is by power amplifier P4, NAND gate IC4, NAND gate IC5, NAND gate IC6, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms.
For guaranteeing effect, during connection, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5; The electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with the end of oppisite phase of power amplifier P2, and its negative input is then connected with gate drive circuit.The output of described power amplifier P4 is also connected with self-locking optical excitation circuit.
Self-locking optical excitation circuit is by NOR gate IC1, and NOR gate IC2, NOR gate IC3, photocell CDS, potentiometer R5 and electric capacity C3 form.During connection, one end of photocell CDS is connected with the in-phase end of power amplifier P, and its other end is connected with the output of power amplifier P4 after potentiometer R5.This photocell CDS is once sense outside illumination, then its limit self-excitation can produce electric energy, for driving chip M.
Described electric capacity C3 is serially connected between the electrode input end of NOR gate IC3 and output, and namely the positive pole of electric capacity C3 wants the electrode input end of AND OR NOT gate IC3 to be connected, and the output of its negative pole then AND OR NOT gate IC3 is connected.
Meanwhile, the electrode input end of NOR gate IC1 will be connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected.The output of described NOR gate IC2 then needs the negative pole of AND OR NOT gate IC3 simultaneously to enter end to be connected with the in-phase end of power amplifier P1, and the output of the output of NOR gate IC3 then power amplifier P is connected.
The output of the other end AND OR NOT gate IC2 of described resistance R6 is connected, and namely the output of NOR gate IC2 is connected with the end of oppisite phase of power amplifier P after resistance R6.Meanwhile, the negative input of this NOR gate IC2 will be connected with boostrap circuit.
Described boostrap circuit is made up of field effect transistor MOS, resistance R1, resistance R2, resistance R3, resistance R4 and polar capacitor C1 and polar capacitor C2.During connection, one end of resistance R4 is connected with the source electrode of field effect transistor MOS, the other end is connected with the in-phase end of power amplifier P4; The negative pole of polar capacitor C1 is connected with the grid of field effect transistor MOS, and its positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1; Resistance R2 and polar capacitor C1 is in parallel, and the positive pole of polar capacitor C2 is connected with the positive pole of polar capacitor C1, and the negative pole of its negative pole AND OR NOT gate IC2 enters end and is connected.
One end of resistance R3 is connected with the positive pole of polar capacitor C2, its other end ground connection.Meanwhile, the drain electrode needs of this field effect transistor MOS are connected with the tie point of resistance R7 with photocell CDS, to guarantee that photocell CDS can provide operating voltage for field effect transistor MOS.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C5, resistance R8, electric capacity C6, electric capacity C7 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C5 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.For guaranteeing the normal operation of driving chip M, its VCC holds the voltage needing external+12V.
Resistance R8 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, and its emitter is connected with the negative pole of electric capacity C19.Meanwhile, the collector electrode of this transistor Q1 also needs the direct voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, and its non-same polarity is then connected with the emitter of transistor Q1.Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present invention.According to the situation of reality, user can only select any one or several port of these four outputs to use.
Gate drive circuit is then emphasis of the present invention, and it is by triode Q5, triode Q6, field effect transistor MOS1, unidirectional thyristor D6, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, diode D5, electric capacity C16, electric capacity C17, electric capacity C18 and electric capacity C19 form.
During connection, the negative pole of electric capacity C16 is connected with the base stage of triode Q6, its positive pole is then connected with the negative input of NAND gate IC6.Resistance R24 then needs to be in parallel with electric capacity C16, thus forms a reshaper.Ground connection while one end of resistance R23 is connected with the positive pole of electric capacity C16, its other end is then connected with the emitter of triode Q6, one end of resistance R22 is connected with the collector electrode of triode Q5, its other end is then connected with the positive pole of electric capacity C16.
Simultaneously, between the collector electrode that this resistance R25 is serially connected in triode Q5 and base stage, the N pole of diode D5 is connected with the collector electrode of triode Q6, its P pole is then connected with the grid of field effect transistor MOS1 after resistance R26, the positive pole of electric capacity C17 is connected with the emitter of triode Q6, its negative pole is then connected with the grid of field effect transistor MOS1 after resistance R27, the positive pole of electric capacity C18 is connected with the negative pole of electric capacity C17, its negative pole is then connected with the P pole of unidirectional thyristor D6, the positive pole of electric capacity C19 is connected with the control pole of unidirectional thyristor D6, its negative pole is then connected with the emitter of transistor Q1.The base stage of described triode Q5 is connected with the collector electrode of triode Q6, its emitter is then connected with the P pole of diode D5.Grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D6.
When signal enters into by triode Q5 after reshaper shaping, the amplifier that triode Q6 and diode D5 is formed amplifies.This triode Q6 preferentially adopts NPN type triode, and triode Q5 then preferentially adopts PNP type triode, so then can provide enough gate currents, better to trigger field effect transistor MOS1.Meanwhile, in order to eliminate the oscillatory occurences that may occur, the electric capacity C17 in this gate drive circuit, electric capacity C18 and resistance R27 then form a damping filter, and it is for oscillation-damped phenomenon.
As mentioned above, just the present invention can well be realized.
Claims (8)
1. based on the energy-conservation raster data model system of mixed type of gate-drive, it is by driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, be arranged on the power amplification circuit between self-locking optical excitation circuit and driving chip M, and the beam excitation formula logic amplifying circuit be connected with power amplification circuit with boostrap circuit, self-locking optical excitation circuit respectively forms, it is characterized in that, between beam excitation formula logic amplifying circuit and drive circuit, be also serially connected with gate drive circuit, described gate drive circuit is by triode Q5, triode Q6, field effect transistor MOS1, unidirectional thyristor D6, negative pole is connected with the base stage of triode Q6, the electric capacity C16 that positive pole is then connected with beam excitation formula logic amplifying circuit, the resistance R24 be in parallel with electric capacity C16, one end is connected with the positive pole of electric capacity C16, the resistance R23 of ground connection while the other end is then connected with the emitter of triode Q6, one end is connected with the collector electrode of triode Q5, the resistance R22 that the other end is then connected with the positive pole of electric capacity C16, be serially connected in the resistance R25 between the collector electrode of triode Q5 and base stage, N pole is connected with the collector electrode of triode Q6, the diode D5 that P pole is then connected with the grid of field effect transistor MOS1 after resistance R26, positive pole is connected with the emitter of triode Q6, the electric capacity C17 that negative pole is then connected with the grid of field effect transistor MOS1 after resistance R27, positive pole is connected with the negative pole of electric capacity C17, the electric capacity C18 that negative pole is then connected with the P pole of unidirectional thyristor D6, and positive pole is connected with the control pole of unidirectional thyristor D6, the electric capacity C19 that negative pole is then connected with drive circuit forms, the base stage of described triode Q5 is connected with the collector electrode of triode Q6, its emitter is then connected with the P pole of diode D5, grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D6.
2. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 1, it is characterized in that, described beam excitation formula logic amplifying circuit is by power amplifier P4, NAND gate IC4, NAND gate IC5, NAND gate IC6, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5, the electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with power amplification circuit, and its negative input is then connected with the positive pole of electric capacity C16, the output of power amplifier P4 is then connected with self-locking optical excitation circuit, and its in-phase end is connected with boostrap circuit.
3. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 2, it is characterized in that, described power amplification circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and end of oppisite phase and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and in-phase end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the in-phase end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the end of oppisite phase of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the end of oppisite phase of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the end of oppisite phase of described power amplifier P1 is connected with the in-phase end of power amplifier P2, and its in-phase end is connected with self-locking optical excitation circuit, the end of oppisite phase of power amplifier P2 is connected with the output of NAND gate IC6, the output of power amplifier P3 is then connected with the TD pin of driving chip M.
4. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 3, it is characterized in that, described homophase AC signal amplifying circuit is by power amplifier P, one end is connected with the VCC pin of driving chip M, the resistance R7 that the other end is connected with the in-phase end of power amplifier P, one end is connected with the end of oppisite phase of power amplifier P, the resistance R6 that the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the in-phase end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M and self-locking optical excitation circuit respectively, its in-phase end is also connected with self-locking optical excitation circuit.
5. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 4, it is characterized in that, described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, the photocell CDS that one end is connected with the in-phase end of power amplifier P, the other end is connected with the output of power amplifier P4 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described NOR gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the in-phase end of power amplifier P1, the output of NOR gate IC3 is then connected with the output of power amplifier P; The output of described NOR gate IC2 is also connected with the end of oppisite phase of power amplifier P after resistance R6.
6. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 5, it is characterized in that, described boostrap circuit is by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R4 that the other end is connected with the in-phase end of power amplifier P4, negative pole is connected with the grid of field effect transistor MOS, the polar capacitor C1 that positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, positive pole is connected with the positive pole of polar capacitor C1, the polar capacitor C2 that the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms, the drain electrode of described field effect transistor MOS is connected with the tie point of resistance R7 with photocell CDS.
7. the energy-conservation raster data model system of the mixed type based on gate-drive according to claim 6, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, and the transistor Q1 that emitter is connected with the negative pole of electric capacity C19 forms, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, and its non-same polarity is then connected with the emitter of transistor Q1, meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and its collector electrode then connects+6V voltage, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
8. the energy-conservation raster data model of the mixed type based on the gate-drive system according to any one of claim 1 ~ 7, it is characterized in that, described driving chip M is LTC4440A integrated chip.
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| CN201510307125.3A CN104869723A (en) | 2014-11-25 | 2015-06-06 | Hybrid energy-saving grid drive system based on gate drive |
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