CN204335030U - A kind of virtual protection amplifying type self-locking optical excitation raster data model system - Google Patents
A kind of virtual protection amplifying type self-locking optical excitation raster data model system Download PDFInfo
- Publication number
- CN204335030U CN204335030U CN201420726367.7U CN201420726367U CN204335030U CN 204335030 U CN204335030 U CN 204335030U CN 201420726367 U CN201420726367 U CN 201420726367U CN 204335030 U CN204335030 U CN 204335030U
- Authority
- CN
- China
- Prior art keywords
- gate
- driving chip
- output
- resistance
- power amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The utility model discloses a kind of virtual protection amplifying type self-locking optical excitation raster data model system, primarily of driving chip M, the drive circuit be connected with this driving chip M, and the self-locking optical excitation circuit be connected with this driving chip M forms; Described self-locking optical excitation circuit is by NOR gate IC1; NOR gate IC2; NOR gate IC3; one end is connected with the VCC pin of driving chip M, the photocell CDS of other end ground connection after potentiometer R2; the compositions such as the resistance R1 that one end is connected with the VCC pin of driving chip M, the negative input of other end AND OR NOT gate IC2 is connected; it is characterized in that, between the output and the INP pin of driving chip M of NOR gate IC3, be serially connected with virtual protection amplifying circuit.The utility model can excite the correlation function of driving chip M automatically according to outside illumination condition, without the need to increasing extra starting drive, therefore its power consumption is lower.
Description
Technical field
The utility model relates to a kind of LED drive circuit, specifically refers to a kind of virtual protection amplifying type self-locking optical excitation raster data model system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Utility model content
The purpose of this utility model is the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit; a kind of reasonable in design is provided; can effectively reduce energy consumption and current noise, obviously shorten a kind of virtual protection amplifying type self-locking optical excitation raster data model system of start-up time.
The purpose of this utility model is achieved through the following technical solutions: a kind of virtual protection amplifying type self-locking optical excitation raster data model system, primarily of driving chip M, the drive circuit be connected with this driving chip M, and the self-locking optical excitation circuit be connected with this driving chip M forms; Described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, one end is connected with the VCC pin of driving chip M, the photocell CDS of other end ground connection after potentiometer R2, the resistance R1 that one end is connected with the VCC pin of driving chip M, the negative input of other end AND OR NOT gate IC2 is connected, and the electric capacity C1 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected.Meanwhile, between the output and the INP pin of driving chip M of NOR gate IC3, virtual protection amplifying circuit is serially connected with, this virtual protection amplifying circuit is primarily of power amplifier P1, power amplifier P2, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C5 that positive pole is connected with the negative input of NAND gate IC5 after resistance R7, one end is connected with the negative input of NAND gate IC4, the resistance R4 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R5 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC4, the resistance R6 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C6 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D2 is connected with the output of power amplifier P1 after resistance R8, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D3 that resistance R10 is connected with the tie point of resistance R8 with voltage stabilizing didoe D2 after resistance R9, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R10 with diode D3 forms, the electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P1, the electrode input end of the output NAND gate IC5 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1, the output of the positive pole AND OR NOT gate IC3 of described polar capacitor C5 is connected, and resistance R10 is then connected with the INP pin of driving chip M with the tie point of resistance R9.
Described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C3 and electric capacity C4 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use, described driving chip M is LTC4440A integrated chip.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model can excite the correlation function of driving chip M automatically according to outside illumination condition, and without the need to increasing extra starting drive, therefore its power consumption is lower.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present utility model, therefore its start-up time is extremely short.
(3) the utility model effectively can avoid external electromagnetic interference, can reduce current noise significantly.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is virtual protection amplification circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1; the utility model is primarily of driving chip M; the drive circuit be connected with this driving chip M, the self-locking optical excitation circuit be connected with driving chip M, and the virtual protection amplifying circuit be serially connected between driving chip M and self-locking optical excitation circuit forms.
As described in Figure 1, this self-locking optical excitation circuit is made up of photocell CDS, NOR gate IC1, NOR gate IC2, NOR gate IC3, resistance R1, potentiometer R2 and electric capacity C1.Wherein, photocell CDS is used for producing electric energy under illumination condition, and its one end is connected with the VCC pin of driving chip M, and its other end is ground connection after potentiometer R2 then.
Meanwhile, one end of resistance R1 is also connected with the VCC pin of driving chip M, and the negative input of its other end then AND OR NOT gate IC2 is connected.Electric capacity C1 is serially connected between the electrode input end of NOR gate IC3 and output, and for guaranteeing that NOR gate IC3 can normally run, the positive pole of this electric capacity C1 needs the electrode input end of AND OR NOT gate IC3 to be connected, and the output of its negative pole then AND OR NOT gate IC3 connects.
The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, the output of its negative input AND OR NOT gate IC2 is connected, the electrode input end of its output then AND OR NOT gate IC2 is connected, and namely forms one between this NOR gate IC1 and NOR gate IC2 and intersects gate circuit.The negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C2, resistance R3, electric capacity C3, electric capacity C4 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C2 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.
Resistance R3 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C3 and electric capacity C4 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q1 also needs the direct voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1.Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present utility model.According to the situation of reality, user can only select any one or several port of these four outputs to use.
The structure of described virtual protection amplifying circuit as shown in Figure 2, it is primarily of power amplifier P1, power amplifier P2, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C5 that positive pole is connected with the negative input of NAND gate IC5 after resistance R7, one end is connected with the negative input of NAND gate IC4, the resistance R4 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R5 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC4, the resistance R6 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C6 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D2 is connected with the output of power amplifier P1 after resistance R8, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D3 that resistance R10 is connected with the tie point of resistance R8 with voltage stabilizing didoe D2 after resistance R9, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R10 with diode D3 forms.
Meanwhile, the electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P1; The electrode input end of the output NAND gate IC5 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1.
During connection, the output of the positive pole AND OR NOT gate IC3 of described polar capacitor C5 is connected, and resistance R10 is then connected with the INP pin of driving chip M with the tie point of resistance R9.
For guaranteeing result of use, the high-frequency N channel mosfet grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
As mentioned above, just the utility model can well be realized.
Claims (3)
1. a virtual protection amplifying type self-locking optical excitation raster data model system, primarily of driving chip M, the drive circuit be connected with this driving chip M, and the self-locking optical excitation circuit be connected with this driving chip M forms, described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, one end is connected with the VCC pin of driving chip M, the photocell CDS of other end ground connection after potentiometer R2, the resistance R1 that one end is connected with the VCC pin of driving chip M, the negative input of other end AND OR NOT gate IC2 is connected, and the electric capacity C1 be serially connected between the electrode input end of NOR gate IC3 and output forms, the electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R2 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected, the negative input of the output AND OR NOT gate IC3 of described NOR gate IC2 is connected, and it is characterized in that, between the output and the INP pin of driving chip M of NOR gate IC3, be serially connected with virtual protection amplifying circuit, this virtual protection amplifying circuit is primarily of power amplifier P1, power amplifier P2, NAND gate IC4, NAND gate IC5, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C5 that positive pole is connected with the negative input of NAND gate IC5 after resistance R7, one end is connected with the negative input of NAND gate IC4, the resistance R4 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R5 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC4, the resistance R6 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C6 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC5, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D2 is connected with the output of power amplifier P1 after resistance R8, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D3 that resistance R10 is connected with the tie point of resistance R8 with voltage stabilizing didoe D2 after resistance R9, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D4 that P pole is connected with the tie point of resistance R10 with diode D3 forms, the electrode input end of described NAND gate IC4 is connected with the negative input of power amplifier P1, the electrode input end of the output NAND gate IC5 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1, the output of the positive pole AND OR NOT gate IC3 of described polar capacitor C5 is connected, and resistance R10 is then connected with the INP pin of driving chip M with the tie point of resistance R9.
2. a kind of virtual protection amplifying type self-locking optical excitation raster data model system according to claim 1, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C3 and electric capacity C4 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
3. a kind of virtual protection amplifying type self-locking optical excitation raster data model system according to claim 1 and 2, it is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420726367.7U CN204335030U (en) | 2014-11-27 | 2014-11-27 | A kind of virtual protection amplifying type self-locking optical excitation raster data model system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420726367.7U CN204335030U (en) | 2014-11-27 | 2014-11-27 | A kind of virtual protection amplifying type self-locking optical excitation raster data model system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204335030U true CN204335030U (en) | 2015-05-13 |
Family
ID=53171334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420726367.7U Expired - Fee Related CN204335030U (en) | 2014-11-27 | 2014-11-27 | A kind of virtual protection amplifying type self-locking optical excitation raster data model system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204335030U (en) |
-
2014
- 2014-11-27 CN CN201420726367.7U patent/CN204335030U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204316789U (en) | A kind of self-locking optical excitation raster data model system based on power amplification | |
| CN204335030U (en) | A kind of virtual protection amplifying type self-locking optical excitation raster data model system | |
| CN104411054A (en) | Same-phase alternating-current signal amplification type optical excitation gate drive system based on logic protection amplification circuit | |
| CN104411047A (en) | Energy-saving power-amplifying-type grid driving system | |
| CN104470105A (en) | Logic protection amplifying grid drive system based on bootstrap circuit | |
| CN104869723A (en) | Hybrid energy-saving grid drive system based on gate drive | |
| CN104470103A (en) | Logic protection amplification type self-locking optical excitation grid drive system | |
| CN204316809U (en) | The homophase AC signal amplifying type optical excitation raster data model system of logic-based protection amplifying circuit | |
| CN204335053U (en) | A kind of mixed type raster data model system | |
| CN204316782U (en) | A kind of mixed type raster data model system | |
| CN104485804A (en) | Novel logic protection emitter coupling type gate driving system | |
| CN104470088A (en) | Grid drive system for LED lamp protection system | |
| CN204335006U (en) | A kind of self-locking optical excitation gate driver circuit | |
| CN104470116A (en) | Mixed type grid driving system | |
| CN204316804U (en) | A kind of novel grid drive system | |
| CN204335046U (en) | A kind of mixed type raster data model system of logic-based protection manifold type amplifying circuit | |
| CN104540267A (en) | LED lamp protection system based on logic protection emitter-coupled amplifying circuit | |
| CN204335045U (en) | A kind of homophase AC signal amplifying type raster data model system of logic-based protection emitter-base bandgap grading manifold type | |
| CN204335005U (en) | A kind of homophase AC signal amplifying type optical excitation gate driver circuit | |
| CN204335037U (en) | A kind of virtual protection amplifying type raster data model system based on boostrap circuit | |
| CN104411063A (en) | Hybrid gate drive system based on logic protection coupled amplifying circuit | |
| CN104470122A (en) | In-phase alternating-current signal amplifying type gate drive system based on logic protection emitter-coupled type | |
| CN204305404U (en) | Based on the raster data model system of beam excitation formula switch power amplifying circuit | |
| CN204316774U (en) | A kind of novel blue light LED raster data model system | |
| CN204335051U (en) | A kind of raster data model system based on beam excitation and virtual protection formula |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150513 Termination date: 20151127 |