CN204316774U - A kind of novel blue light LED raster data model system - Google Patents
A kind of novel blue light LED raster data model system Download PDFInfo
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- CN204316774U CN204316774U CN201420715891.4U CN201420715891U CN204316774U CN 204316774 U CN204316774 U CN 204316774U CN 201420715891 U CN201420715891 U CN 201420715891U CN 204316774 U CN204316774 U CN 204316774U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The utility model discloses a kind of novel blue light LED raster data model system, primarily of transformer T, driving chip M, be serially connected with the switched current source between the VCC pin of driving chip M and INP pin, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, and the transistor Q4 of grounded emitter forms.The utility model not only has the function of short-circuit protection, overvoltage protection and open-circuit-protection, and its power consumption is lower, is only 1/4 of conventional gate drive circuit start-up time its start-up time.
Description
Technical field
The utility model relates to a kind of LED drive circuit, specifically refers to a kind of novel blue light LED raster data model system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Utility model content
The purpose of this utility model is the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit, a kind of reasonable in design is provided, can effectively reduce energy consumption and current noise, obviously shorten a kind of novel blue light LED raster data model system of start-up time.
The purpose of this utility model is achieved through the following technical solutions: a kind of novel blue light LED raster data model system, primarily of transformer T, driving chip M, be serially connected with the switched current source between the VCC pin of driving chip M and INP pin, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, and the transistor Q4 of grounded emitter forms, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4, meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
Meanwhile, the utility model is also also serially connected with beam excitation formula logic amplifying circuit between the TD pin of driving chip M and the emitter of transistor Q4, described beam excitation formula logic amplifying circuit is primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R8 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R8, the polar capacitor C8 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R11 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the end of oppisite phase of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2, and the electrode input end of NAND gate IC3 is connected with the output of power amplifier P, the in-phase end of power amplifier P is then connected with the TD pin of driving chip M, and the output of NAND gate IC3 is then connected with the emitter of transistor Q4.
Described switched current source is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms, the base stage of described transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively, the VCC pin of described driving chip M is connected with the positive pole of polar capacitor C2, and the INP pin of driving chip M is then connected with the negative pole of polar capacitor C2.
For guaranteeing result of use, described driving chip M is LTC4440A integrated chip.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model not only has the function of short-circuit protection, overvoltage protection and open-circuit-protection, and its power consumption is lower, is only 1/4 of conventional gate drive circuit start-up time its start-up time.
(2) the utility model is provided with the switched current source carried, and therefore effectively can avoid external electromagnetic interference, meanwhile, can reduce current noise significantly.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model is by transistor Q4, transformer T, driving chip M, switched current source, diode D1, electric capacity C3, resistance R7, electric capacity C4, electric capacity C5, and beam excitation formula logic amplifying circuit composition.During connection, switched current source needs to be serially connected with between the VCC pin of driving chip M and INP pin, and diode D1 is serially connected with between the VCC pin of driving chip M and BOOST pin, electric capacity C3 is serially connected with between the BOOST pin of driving chip M and TG pin, and resistance R7 is then serially connected with between the TG pin of driving chip M and TS pin.
The base stage of described transistor Q4 is connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q4 also needs the driving voltage of external+6V, to guarantee that transistor Q4 can normally run.
Wherein, described beam excitation formula logic amplifying circuit is primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R8 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R8, the polar capacitor C8 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R11 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of NAND gate IC2 forms.
Meanwhile, the electrode input end of this NAND gate IC1 is connected with the end of oppisite phase of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2, and the electrode input end of NAND gate IC3 is connected with the output of power amplifier P; The in-phase end of power amplifier P is then connected with the TD pin of driving chip M, and the output of NAND gate IC3 is then connected with the emitter of transistor Q4.
The Same Name of Ends of the primary coil of transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4.Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M.
The secondary coil of transformer T is provided with tap Y1 and tap Y2, namely by this tap Y1 and tap Y2, the utility model is formed with 4 outputs, the i.e. Same Name of Ends of secondary coil on the secondary coil of transformer T, the non-same polarity of Y1 tap, Y2 tap and secondary coil.
Switched current source is used for providing working power to driving chip M, it is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms.
Meanwhile, the base stage of this transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively; The VCC pin of described driving chip M is connected with the positive pole of polar capacitor C2, and the INP pin of driving chip M is then connected with the negative pole of polar capacitor C2.
Described RC filter circuit is then formed in parallel by resistance R3 and electric capacity C1, and namely after resistance R3 and electric capacity C1 parallel connection, an one common port is connected with the emitter of transistor Q1, its another common port is then connected with the negative pole of DC power supply S.
For guaranteeing result of use, the high-frequency N channel mosfet grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, i.e. LTC4440A integrated chip.This driving chip can with the input voltage work up to 80V, up to can continuous operation during 100V transient state.
As mentioned above, just the utility model can well be realized.
Claims (3)
1. a novel blue light LED raster data model system, primarily of transformer T, driving chip M, be serially connected with the switched current source between the VCC pin of driving chip M and INP pin, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, and the transistor Q4 of grounded emitter forms, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4, simultaneously, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, the secondary coil of described transformer T is provided with tap Y1 and tap Y2, it is characterized in that, is also serially connected with beam excitation formula logic amplifying circuit between the TD pin and the emitter of transistor Q4 of driving chip M, described beam excitation formula logic amplifying circuit is primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R8 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R8, the polar capacitor C8 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R11 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the end of oppisite phase of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2, and the electrode input end of NAND gate IC3 is connected with the output of power amplifier P, the in-phase end of power amplifier P is then connected with the TD pin of driving chip M, and the output of NAND gate IC3 is then connected with the emitter of transistor Q4.
2. a kind of novel blue light LED raster data model system according to claim 1, it is characterized in that, described switched current source is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms, the base stage of described transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively, the VCC pin of described driving chip M is connected with the positive pole of polar capacitor C2, and the INP pin of driving chip M is then connected with the negative pole of polar capacitor C2.
3. a kind of novel blue light LED raster data model system according to claim 1 and 2, it is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420715891.4U CN204316774U (en) | 2014-11-25 | 2014-11-25 | A kind of novel blue light LED raster data model system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420715891.4U CN204316774U (en) | 2014-11-25 | 2014-11-25 | A kind of novel blue light LED raster data model system |
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| Publication Number | Publication Date |
|---|---|
| CN204316774U true CN204316774U (en) | 2015-05-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420715891.4U Expired - Fee Related CN204316774U (en) | 2014-11-25 | 2014-11-25 | A kind of novel blue light LED raster data model system |
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| Country | Link |
|---|---|
| CN (1) | CN204316774U (en) |
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2014
- 2014-11-25 CN CN201420715891.4U patent/CN204316774U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20151125 |