CN204316312U - A kind of raster data model system based on switch power amplifying circuit - Google Patents
A kind of raster data model system based on switch power amplifying circuit Download PDFInfo
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- CN204316312U CN204316312U CN201420707207.8U CN201420707207U CN204316312U CN 204316312 U CN204316312 U CN 204316312U CN 201420707207 U CN201420707207 U CN 201420707207U CN 204316312 U CN204316312 U CN 204316312U
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- transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The utility model discloses a kind of raster data model system based on switch power amplifying circuit, it is characterized in that, primarily of switched current source, transformer T, driving chip M, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, be serially connected with the switch power amplifying circuit between switched current source and driving chip M, and base stage and the structural feature such as the TG pin of driving chip M is connected.The utility model not only has the function of short-circuit protection, overvoltage protection and open-circuit-protection, and its power consumption is lower, is only 1/4 of conventional gate drive circuit start-up time its start-up time.Meanwhile, the utility model is provided with switch power amplifying circuit, therefore can guarantee that the power signal in input queued switches chip M can not produce decay, and then guarantees overall stable performance.
Description
Technical field
The utility model relates to a kind of LED drive circuit, specifically refers to a kind of raster data model system based on switch power amplifying circuit.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Utility model content
The purpose of this utility model is the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit, a kind of reasonable in design is provided, can effectively reduce energy consumption and current noise, obviously shorten a kind of raster data model system based on switch power amplifying circuit of start-up time.
The purpose of this utility model is achieved through the following technical solutions: a kind of raster data model system based on switch power amplifying circuit, primarily of switched current source, transformer T, driving chip M, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, be serially connected with the switch power amplifying circuit between switched current source and driving chip M, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, and the transistor Q4 of grounded emitter forms, described switch power amplifying circuit is then by power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and negative input and electric capacity C6, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C7, base stage is connected with the output of power amplifier P1, the triode Q5 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q5, the triode Q6 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R14, the triode Q7 that collector electrode is connected with the base stage of triode Q6 after resistance R13, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q6 and the electric capacity C8 of ground connection, the electric capacity C9 be in parallel with resistance R14, one end is connected with the base stage of triode Q7, the resistance R15 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q7, the resistance R16 of the external-4V voltage of the other end, the electric capacity C10 be in parallel with resistance R16, and N pole is connected with the collector electrode of triode Q5, the diode D2 of the extremely external-4V voltage of P forms, the negative input of described power amplifier P1 is connected with the electrode input end of power amplifier P2, the output of power amplifier P3 is connected with the VCC pin of driving chip M, the collector electrode of triode Q7 is connected with the INP pin of driving chip M, and the electrode input end of power amplifier P1 is then all connected with switched current source with the negative input of power amplifier P2.
The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4; Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
Described switched current source is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms, the base stage of described transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively, the positive pole of described polar capacitor C2 is connected with the electrode input end of power amplifier P1, and its negative pole is then connected with the negative input of power amplifier P2.
For guaranteeing result of use, described driving chip M preferentially adopts LTC4440A integrated chip to realize.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model not only has the function of short-circuit protection, overvoltage protection and open-circuit-protection, and its power consumption is lower, is only 1/4 of conventional gate drive circuit start-up time its start-up time.
(2) the utility model is provided with the switched current source carried, and therefore effectively can avoid external electromagnetic interference, meanwhile, can reduce current noise significantly.
(3) the utility model is provided with switch power amplifying circuit, therefore can guarantee that the power signal in input queued switches chip M can not produce decay, and then guarantees overall stable performance.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model is by transistor Q4, transformer T, driving chip M, switched current source, diode D1, electric capacity C3, resistance R7, electric capacity C4, electric capacity C5, and switch power amplifying circuit composition.During connection, the output of switched current source needs to be connected with the input of switch power amplifying circuit, and the output of switch power amplifying circuit then needs to be connected with driving chip M.Described diode D1 is serially connected with between the VCC pin of driving chip M and BOOST pin, to guarantee that its foreign current can not cause damage to driving chip M when transformer T damages.Electric capacity C3 is serially connected with between the BOOST pin of driving chip M and TG pin, and resistance R7 is then serially connected with between the TG pin of driving chip M and TS pin.
The base stage of described transistor Q4 is connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q4 also needs the driving voltage of external+6V, to guarantee that transistor Q4 can normally run.
Wherein, the Same Name of Ends of the primary coil of transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4.Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M.
The secondary coil of transformer T is provided with tap Y1 and tap Y2, namely by this tap Y1 and tap Y2, the utility model is formed with 4 outputs, the i.e. Same Name of Ends of secondary coil on the secondary coil of transformer T, the non-same polarity of Y1 tap, Y2 tap and secondary coil.
Described switch power amplifying circuit, primarily of power amplifier P1, power amplifier P2, power amplifier P3, triode Q5, triode Q6, triode Q7, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and negative input, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and electrode input end, and resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, electric capacity C8, electric capacity C9, electric capacity C10 and diode D2 form.
Wherein, described one-level RC filtered electrical routing resistance R9 and electric capacity C6 is formed in parallel, namely between resistance R9 and the electric capacity C6 negative input that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R10 and electric capacity C7, namely between resistance R10 and the electric capacity C7 electrode input end that is all serially connected in power amplifier P2 and output.Meanwhile, the negative input of power amplifier P1 is also connected with the electrode input end of power amplifier P2.
The base stage of triode Q5 is connected with the output of power amplifier P1, and its collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, and its emitter is then connected with the base stage of triode Q6; The collector electrode of triode Q6 is connected with the negative input of power amplifier P3 after resistance R12, meanwhile, and the collector electrode also external+10V voltage of this triode Q6.
The base stage of triode Q7 is connected with the output of power amplifier P2 after resistance R14, and its collector electrode is then connected with the base stage of triode Q6 after resistance R13.Electric capacity C9 is then in parallel with resistance R14, and for guaranteeing effect, this electric capacity C9 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C9 is connected with the base stage of triode Q7, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C8 is connected with the negative input of power amplifier P3, and its negative pole is then connected with the emitter of triode Q6.Meanwhile, the negative pole of this electric capacity C8 and the equal ground connection of emitter of triode Q6.
One end of resistance R15 is connected with the base stage of triode Q7, the voltage of the external-4V of its other end; And one end of resistance R16 is connected with the emitter of triode Q7, the voltage of its other end then external equally-4V.Electric capacity C10 is then in parallel with resistance R16.Equally, described electric capacity C10 and electric capacity C8 also all adopts electrochemical capacitor to realize.
The N pole of described diode D2 is connected with the collector electrode of triode Q5, and its P pole is at the voltage of external-4V.For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C6 and electric capacity C7 all preferentially adopts patch capacitor to realize.
Described switched current source is used for providing working power to switch power amplifying circuit and driving chip M, it is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms.
Meanwhile, the base stage of this transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively.The positive pole of described polar capacitor C2 will be connected with the electrode input end of power amplifier P1, and the negative pole of polar capacitor C2 then will be connected with the negative input of power amplifier P2.
Described RC filter circuit is then formed in parallel by resistance R3 and electric capacity C1, and namely after resistance R3 and electric capacity C1 parallel connection, an one common port is connected with the emitter of transistor Q1, its another common port is then connected with the negative pole of DC power supply S.
For guaranteeing result of use, the high-frequency N-channel MOS FET grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, i.e. LTC4440A integrated chip.This driving chip can with the input voltage work up to 80V, up to can continuous operation during 100V transient state.
As mentioned above, just the utility model can well be realized.
Claims (4)
1. the raster data model system based on switch power amplifying circuit, it is characterized in that, primarily of switched current source, transformer T, driving chip M, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C3 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R7 between the TG pin of driving chip M and TS pin, be serially connected with the switch power amplifying circuit between switched current source and driving chip M, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C4 and electric capacity C5 in turn, and the transistor Q4 of grounded emitter forms, described switch power amplifying circuit is then by power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and negative input and electric capacity C6, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C7, base stage is connected with the output of power amplifier P1, the triode Q5 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q5, the triode Q6 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R14, the triode Q7 that collector electrode is connected with the base stage of triode Q6 after resistance R13, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q6 and the electric capacity C8 of ground connection, the electric capacity C9 be in parallel with resistance R14, one end is connected with the base stage of triode Q7, the resistance R15 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q7, the resistance R16 of the external-4V voltage of the other end, the electric capacity C10 be in parallel with resistance R16, and N pole is connected with the collector electrode of triode Q5, the diode D2 of the extremely external-4V voltage of P forms, the negative input of described power amplifier P1 is connected with the electrode input end of power amplifier P2, the output of power amplifier P3 is connected with the VCC pin of driving chip M, the collector electrode of triode Q7 is connected with the INP pin of driving chip M, and the electrode input end of power amplifier P1 is then all connected with switched current source with the negative input of power amplifier P2.
2. a kind of raster data model system based on switch power amplifying circuit according to claim 1, it is characterized in that, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C5 with electric capacity C4, ground connection after its non-same polarity is then connected with the emitter of transistor Q4; Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
3. a kind of raster data model system based on switch power amplifying circuit according to claim 2, it is characterized in that, described switched current source is by transistor Q1, transistor Q2, transistor Q3, DC power supply S, be serially connected in the resistance R1 between the collector electrode of transistor Q1 and the collector electrode of transistor Q2, be serially connected in the RC filter circuit between the emitter of transistor Q1 and the negative pole of DC power supply S, be serially connected in the resistance R2 between the base stage of transistor Q1 and the negative pole of DC power supply S, the resistance R5 in parallel with DC power supply S-phase, be serially connected in the resistance R6 between the emitter of transistor Q3 and the negative pole of DC power supply S, be serially connected in the resistance R4 between the collector electrode of transistor Q3 and the collector electrode of transistor Q2, and positive pole is connected with the collector electrode of transistor Q2, the polar capacitor C2 that negative pole is connected with the negative pole of DC power supply S forms, the base stage of described transistor Q2 is also connected with the collector electrode of transistor Q1, and the base stage of transistor Q3 is then connected with the positive pole of DC power supply S with the emitter of transistor Q2 respectively, the positive pole of described polar capacitor C2 is connected with the electrode input end of power amplifier P1, and its negative pole is then connected with the negative input of power amplifier P2.
4. a kind of raster data model system based on switch power amplifying circuit according to any one of claims 1 to 3, it is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420707207.8U CN204316312U (en) | 2014-11-22 | 2014-11-22 | A kind of raster data model system based on switch power amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420707207.8U CN204316312U (en) | 2014-11-22 | 2014-11-22 | A kind of raster data model system based on switch power amplifying circuit |
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| Publication Number | Publication Date |
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| CN204316312U true CN204316312U (en) | 2015-05-06 |
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| CN201420707207.8U Expired - Fee Related CN204316312U (en) | 2014-11-22 | 2014-11-22 | A kind of raster data model system based on switch power amplifying circuit |
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2014
- 2014-11-22 CN CN201420707207.8U patent/CN204316312U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: YANG WENWEI Free format text: FORMER OWNER: CHENGDU ZHILIDA TECHNOLOGY CO., LTD. Effective date: 20150519 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Yang Wenwei Inventor before: Xiao Youhua Inventor before: Du Qin |
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| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 610000 CHENGDU, SICHUAN PROVINCE TO: 200233 XUHUI, SHANGHAI Free format text: CORRECT: INVENTOR; FROM: XIAO YOUHUA DU QIN TO: YANG WENWEI |
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| TR01 | Transfer of patent right |
Effective date of registration: 20150519 Address after: 200233, room 31, No. 9, Lane 101, Guilin West Street, Shanghai, Xuhui District Patentee after: Yang Wenwei Address before: 610000 Sichuan city of Chengdu province high tech Zone Guixi Industrial Park Patentee before: Chengdu Zhilida Technology Co., Ltd. |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160822 Address after: 200233 room 420H, building, No. 509, Xuhui District, Shanghai, Caobao Road Patentee after: SHANGHAI JIAQI NETWORK SCIENCE & TECHNOLOGY CO., LTD. Address before: 200233, room 31, No. 9, Lane 101, Guilin West Street, Shanghai, Xuhui District Patentee before: Yang Wenwei |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20191122 |
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| CF01 | Termination of patent right due to non-payment of annual fee |