CN204316791U - A kind of power amplification formula raster data model system - Google Patents
A kind of power amplification formula raster data model system Download PDFInfo
- Publication number
- CN204316791U CN204316791U CN201420708144.8U CN201420708144U CN204316791U CN 204316791 U CN204316791 U CN 204316791U CN 201420708144 U CN201420708144 U CN 201420708144U CN 204316791 U CN204316791 U CN 204316791U
- Authority
- CN
- China
- Prior art keywords
- resistance
- power amplifier
- electric capacity
- driving chip
- triode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The utility model discloses a kind of power amplification formula raster data model system, primarily of driving chip M, and the drive circuit to be connected with driving chip M forms, it is characterized in that, this system is also provided with the switch power amplifying circuit be connected with driving chip M, and the boostrap circuit be connected with this switch power amplifying circuit; Described switch power amplifying circuit is by power amplifier P1, and power amplifier P2, power amplifier P3, be serially connected in the composition such as resistance R6 and electric capacity C3 between the output of power amplifier P1 and negative input.The utility model overall structure is very simple, and it makes and very easy to use.Meanwhile, be only 1/4 of conventional gate drive circuit start-up time start-up time of the present utility model, its start-up time is extremely short.
Description
Technical field
The utility model relates to a kind of LED drive circuit, specifically refers to a kind of power amplification formula raster data model system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Utility model content
The purpose of this utility model is the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit, a kind of reasonable in design is provided, can effectively reduce energy consumption and current noise, obviously shorten a kind of power amplification formula raster data model system of start-up time.
The purpose of this utility model is achieved through the following technical solutions: a kind of power amplification formula raster data model system, primarily of driving chip M, and the drive circuit to be connected with driving chip M forms, simultaneously, this system is also provided with the switch power amplifying circuit be connected with driving chip M, and the boostrap circuit be connected with this switch power amplifying circuit.
Described switch power amplifying circuit is by power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R6 between the output of power amplifier P1 and negative input and electric capacity C3, be serially connected in the resistance R7 between the output of power amplifier P2 and electrode input end and electric capacity C4, base stage is connected with the output of power amplifier P1, the triode Q1 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, base stage is connected with the emitter of triode Q1, the triode Q2 that collector electrode is connected with the negative input of power amplifier P3 after resistance R8, base stage is connected with the output of power amplifier P2 after resistance R9, the triode Q3 that collector electrode is connected with the base stage of triode Q2 after resistance R12, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q2 and the electric capacity C5 of ground connection, the electric capacity C6 be in parallel with resistance R9, one end is connected with the base stage of triode Q3, the resistance R10 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q3, the resistance R11 of the external-4V voltage of the other end, the electric capacity C7 be in parallel with resistance R11, N pole is connected with the collector electrode of triode Q1, the diode D1 of the extremely external-4V voltage of P, and positive pole is connected with the INP pin of driving chip M, negative pole after being connected with the emitter of triode Q2 again the polar capacitor C8 of ground connection form, the output of described power amplifier P3 is then connected with the VCC pin of driving chip M.
Described boostrap circuit is then by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R5 of other end ground connection, the polar capacitor C1 that negative pole is connected with the grid of field effect transistor MOS, positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, the polar capacitor C2 that positive pole is connected with the positive pole of polar capacitor C1, negative pole is connected with the source electrode of field effect transistor MOS, and one end is connected with the positive pole of polar capacitor C2, the resistance R4 of other end ground connection forms; The drain electrode of described field effect transistor MOS is connected with the electrode input end of power amplifier P1, and this drain electrode also simultaneously external+12V voltage, the source electrode of field effect transistor MOS is then connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively, the negative input then ground connection of power amplifier P2.
Further, described drive circuit is by transformer T, be serially connected with the diode D2 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C9 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R13 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C10 and electric capacity C11 the transistor Q4 of ground connection and emitter also ground connection form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C11 with electric capacity C10, and its non-same polarity is then connected with the emitter of transistor Q4; Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use of the present utility model, described driving chip M is LTC4440A integrated chip.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model overall structure is very simple, and it makes and very easy to use.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present utility model, its start-up time is extremely short.
(3) the utility model adopts boostrap circuit and switch power amplifying circuit to provide control signal for driving chip, therefore has very high input impedance, can guarantee the stable performance of whole circuit.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model primarily of driving chip M, the drive circuit be connected with driving chip M, the switch power amplifying circuit be connected with driving chip M, and the boostrap circuit be connected with switch power amplifying circuit forms.For guaranteeing result of use of the present utility model, the high-frequency N-channel MOS FET grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
Described switch power amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, triode Q1, triode Q2, triode Q3, polar capacitor C8, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and negative input, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and electrode input end, and resistance R3, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, electric capacity C5, electric capacity C6, electric capacity C7 and diode D1 form.
Wherein, described one-level RC filtered electrical routing resistance R6 and electric capacity C3 is formed in parallel, namely between resistance R6 and the electric capacity C3 negative input that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R7 and electric capacity C4, namely between resistance R7 and the electric capacity C4 electrode input end that is all serially connected in power amplifier P2 and output.Meanwhile, the negative input of this power amplifier P1 is also connected with the electrode input end of power amplifier P2.
The base stage of triode Q1 is connected with the output of power amplifier P1, and its collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, and its emitter is then connected with the base stage of triode Q2; The collector electrode of triode Q2 is connected with the negative input of power amplifier P3 after resistance R8, meanwhile, and the collector electrode also external+10V voltage of this triode Q2.
The base stage of triode Q3 is connected with the output of power amplifier P2 after resistance R9, and its collector electrode is then connected with the base stage of triode Q2 after resistance R12.Electric capacity C6 is then in parallel with resistance R9, and for guaranteeing effect, this electric capacity C6 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C6 is connected with the base stage of triode Q3, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C5 is connected with the negative input of power amplifier P3, and its negative pole is then connected with the emitter of triode Q2.Meanwhile, the negative pole of this electric capacity C5 and the equal ground connection of emitter of triode Q2.
The positive pole of polar capacitor C8 is connected with the INP pin of driving chip M, and negative pole is connected with the emitter of triode Q2 with the negative pole of electric capacity C5 respectively.
One end of resistance R10 is connected with the base stage of triode Q3, the voltage of the external-4V of its other end; And one end of resistance R11 is connected with the emitter of triode Q3, the voltage of its other end then external equally-4V.Electric capacity C7 is then in parallel with resistance R11.Equally, described electric capacity C5 and electric capacity C7 also all adopts electrochemical capacitor to realize.
The N pole of described diode D1 is connected with the collector electrode of triode Q1, and its P pole is at the voltage of external-4V.
For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C3 and electric capacity C4 all preferentially adopts patch capacitor to realize.
Described boostrap circuit is made up of field effect transistor MOS, polar capacitor C1, polar capacitor C2, resistance R1, resistance R2, resistance R4 and resistance R5.During connection, one end of resistance R5 is connected with the source electrode of field effect transistor MOS, its other end ground connection; The negative pole of polar capacitor C1 is connected with the grid of field effect transistor MOS, and its positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, and resistance R2 is then in parallel with polar capacitor C1.
The positive pole of described polar capacitor C2 is connected with the positive pole of polar capacitor C1, and its negative pole is connected with the source electrode of field effect transistor MOS.And one end of resistance R4 is connected with the positive pole of polar capacitor C2, its other end ground connection.
The drain electrode needs of described field effect transistor MOS are connected with the electrode input end of power amplifier P1, its source electrode then needs to be connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively, the negative input then ground connection of power amplifier P2.
For guaranteeing the normal work of field effect transistor MOS and switch power amplifying circuit, therefore the drain electrode of this field effect transistor MOS needs the voltage of external+12V.
Described drive circuit is then made up of transformer T, diode D2, electric capacity C9, resistance R13, electric capacity C10, electric capacity C11 and transistor Q4.During connection, the P pole of diode D2 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C9 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.
Resistance R13 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q4 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C10 and electric capacity C11 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q4 also needs the direct voltage of external+6V, to guarantee that transistor Q4 has enough bias voltages to drive himself conducting.
For guaranteeing result of use, described electric capacity C9, electric capacity C10 and electric capacity C11 all adopt patch capacitor to realize.Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.
The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C11 with electric capacity C10, ground connection after its non-same polarity is then connected with the emitter of transistor Q4.Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present utility model.According to the situation of reality, user can only select any one or several port of these four outputs to use.
As mentioned above, just the utility model can well be realized.
Claims (3)
1. a power amplification formula raster data model system, primarily of driving chip M, and the drive circuit to be connected with driving chip M forms, it is characterized in that, this system is also provided with the switch power amplifying circuit be connected with driving chip M, and the boostrap circuit be connected with this switch power amplifying circuit, described switch power amplifying circuit is by power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R6 between the output of power amplifier P1 and negative input and electric capacity C3, be serially connected in the resistance R7 between the output of power amplifier P2 and electrode input end and electric capacity C4, base stage is connected with the output of power amplifier P1, the triode Q1 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, base stage is connected with the emitter of triode Q1, the triode Q2 that collector electrode is connected with the negative input of power amplifier P3 after resistance R8, base stage is connected with the output of power amplifier P2 after resistance R9, the triode Q3 that collector electrode is connected with the base stage of triode Q2 after resistance R12, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q2 and the electric capacity C5 of ground connection, the electric capacity C6 be in parallel with resistance R9, one end is connected with the base stage of triode Q3, the resistance R10 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q3, the resistance R11 of the external-4V voltage of the other end, the electric capacity C7 be in parallel with resistance R11, N pole is connected with the collector electrode of triode Q1, the diode D1 of the extremely external-4V voltage of P, and positive pole is connected with the INP pin of driving chip M, negative pole after being connected with the emitter of triode Q2 again the polar capacitor C8 of ground connection form, the output of described power amplifier P3 is then connected with the VCC pin of driving chip M,
Described boostrap circuit is then by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R5 of other end ground connection, the polar capacitor C1 that negative pole is connected with the grid of field effect transistor MOS, positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, the polar capacitor C2 that positive pole is connected with the positive pole of polar capacitor C1, negative pole is connected with the source electrode of field effect transistor MOS, and one end is connected with the positive pole of polar capacitor C2, the resistance R4 of other end ground connection forms; The drain electrode of described field effect transistor MOS is connected with the electrode input end of power amplifier P1, and this drain electrode also simultaneously external+12V voltage, the source electrode of field effect transistor MOS is then connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively, the negative input then ground connection of power amplifier P2.
2. a kind of power amplification formula raster data model system according to claim 1, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D2 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C9 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R13 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C10 and electric capacity C11 the transistor Q4 of ground connection and emitter also ground connection form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C11 with electric capacity C10, and its non-same polarity is then connected with the emitter of transistor Q4; Meanwhile, the emitter of transistor Q4 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
3. a kind of power amplification formula raster data model system according to claim 2, it is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420708144.8U CN204316791U (en) | 2014-11-22 | 2014-11-22 | A kind of power amplification formula raster data model system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420708144.8U CN204316791U (en) | 2014-11-22 | 2014-11-22 | A kind of power amplification formula raster data model system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204316791U true CN204316791U (en) | 2015-05-06 |
Family
ID=53139085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420708144.8U Expired - Fee Related CN204316791U (en) | 2014-11-22 | 2014-11-22 | A kind of power amplification formula raster data model system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204316791U (en) |
-
2014
- 2014-11-22 CN CN201420708144.8U patent/CN204316791U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104869722A (en) | Grid drive system of light beam excitation type based on gate drive | |
| CN104486868A (en) | Power amplification type grid electrode driving system | |
| CN104411047A (en) | Energy-saving power-amplifying-type grid driving system | |
| CN104485804A (en) | Novel logic protection emitter coupling type gate driving system | |
| CN104470105A (en) | Logic protection amplifying grid drive system based on bootstrap circuit | |
| CN204316789U (en) | A kind of self-locking optical excitation raster data model system based on power amplification | |
| CN204316791U (en) | A kind of power amplification formula raster data model system | |
| CN204316796U (en) | A kind of energy-saving power amplification formula raster data model system | |
| CN104470088A (en) | Grid drive system for LED lamp protection system | |
| CN204335037U (en) | A kind of virtual protection amplifying type raster data model system based on boostrap circuit | |
| CN104393742A (en) | Power amplifying circuit and excitation circuit based mixed type gate driving system | |
| CN204335023U (en) | A kind of gate drivers based on boostrap circuit | |
| CN204305404U (en) | Based on the raster data model system of beam excitation formula switch power amplifying circuit | |
| CN204316792U (en) | A kind of power amplification formula mixed type raster data model system | |
| CN204316313U (en) | A kind of new logic protection emitter-base bandgap grading manifold type raster data model system | |
| CN204316811U (en) | A kind of raster data model system of logic-based protection amplifying circuit | |
| CN104470077A (en) | Gate driver based on bootstrap circuit | |
| CN204316804U (en) | A kind of novel grid drive system | |
| CN204316312U (en) | A kind of raster data model system based on switch power amplifying circuit | |
| CN204335053U (en) | A kind of mixed type raster data model system | |
| CN204305403U (en) | Based on the mixed type raster data model system of power amplification circuit and energizing circuit | |
| CN104394629A (en) | Novel gate drive system | |
| CN204335046U (en) | A kind of mixed type raster data model system of logic-based protection manifold type amplifying circuit | |
| CN204316782U (en) | A kind of mixed type raster data model system | |
| CN204316788U (en) | A kind of LED protection system raster data model system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20151122 |
|
| EXPY | Termination of patent right or utility model |