JPS60117820A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS60117820A
JPS60117820A JP58224837A JP22483783A JPS60117820A JP S60117820 A JPS60117820 A JP S60117820A JP 58224837 A JP58224837 A JP 58224837A JP 22483783 A JP22483783 A JP 22483783A JP S60117820 A JPS60117820 A JP S60117820A
Authority
JP
Japan
Prior art keywords
level
output
input
gate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58224837A
Other languages
Japanese (ja)
Other versions
JPH0552688B2 (en
Inventor
Tsukasa Unenai
宇根内　司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP58224837A priority Critical patent/JPS60117820A/en
Publication of JPS60117820A publication Critical patent/JPS60117820A/en
Publication of JPH0552688B2 publication Critical patent/JPH0552688B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain the change of the threshold level of an input circuit in response to the change of a drive level for a logical IC, by selecting the optimum threshold value of the logical input of said logical IC in accordance with the output level of each independent drive circuit which drives the logical IC. CONSTITUTION:The output of an NAND gate 8 and the output of an NAND gate 7 are set at H and L respectively at a time point (a) when an electric power supply is applied. Thus a transistor (TR) 9 is turned on and the gate of a TR4 has the same level as a TR3. These levels of the TRs 4 and 3 change in response to the drive level. Then the output of the gate 7 changes to H from L when it exceeds the threshold value of a HT inverter at a time point (b). Furthermore the output of the gate 8 changes to L from H. As a result, the TR9 is turned off and the input of the TR4 is fixed at a GND level and becomes insensitive to the drive level. In case the drive level is set at ''2'', the HT inverter output has no change. Therefore the gate level of the TR4 is equal to that set at the time point (a) and varies in response to the drive level.

Description

【発明の詳細な説明】 本発明は、論理集積回路の個々の端子の入力しきい値を
、駆動回路の出力レベルに合せて、自動的に最適値に設
定する機能を備えた入力回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input circuit having a function of automatically setting the input threshold value of each terminal of a logic integrated circuit to an optimum value in accordance with the output level of a drive circuit.

現在、論理集積回路の内部構成には、ＴＬ。Currently, the internal configuration of logic integrated circuits includes TL.

ＥＣＬ　、０ＭＯ８等の種類があるが、これ等の出力回
路は、本来全体の論理回路が同一の内部構成をもつ論理
集積回路で設計されることを前提としているために、個
々の内部構成において最適なレベルを持つ様設計されて
いる。There are types such as ECL and 0MO8, but these output circuits are based on the premise that the entire logic circuit is designed as a logic integrated circuit with the same internal configuration, so it is not optimal for each internal configuration. It is designed to have a high level.

従って、大型システムの設計等において、内部構成の異
なる論理集積回路を組合せて使用するには、２者間にレ
ベル変換回路をそう入するか、ま−たけ新たに論理集積
回路を設計する時点で駆動レベルに合せて個々の入力回
路を設計するか、駆動レベルを変更ならしめるために制
御端子を設ける必要があった。Therefore, when designing a large system, etc., in order to use a combination of logic integrated circuits with different internal configurations, it is necessary to insert a level conversion circuit between the two, or to design a new logic integrated circuit. It was necessary to design individual input circuits according to the drive level, or to provide a control terminal to change the drive level.

しかし、従来の方法は、前者では部品の追加が必要であ
り、後者では駆動レベルに変更が生じた場合新たに回路
を設計し直す必要があり、制御端子を設ける方法では論
理集積回路の端子数が増加してしまうという欠点があっ
た。However, with conventional methods, the former requires the addition of components, the latter requires a new circuit design when the drive level changes, and the method of providing control terminals requires the number of terminals in the logic integrated circuit. The disadvantage was that it increased.

本発明の目的は、この問題を解決し、駆動レベルの変更
に応じて入力回路のしきい値を変更可能な入力回路を提
供することにある。An object of the present invention is to solve this problem and provide an input circuit that can change the threshold value of the input circuit in accordance with changes in the drive level.

すなわち、本発明による入力回路は、少数のトランジス
タを追加し、駆動レベルを判定し、この判定で入力のし
きい値を制御することで、部品の追加９回路の設計変更
、制御端子の増加をすることなく、上述の問題を解決し
たものである。In other words, the input circuit according to the present invention adds a small number of transistors, determines the drive level, and controls the input threshold based on this determination, thereby eliminating the need for adding components, changing the design of nine circuits, and increasing the number of control terminals. This solves the above-mentioned problem without having to do anything.

以下、本発明をその実施例により、図面を参照して詳細
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of embodiments with reference to the drawings.

第１図は本発明の一実施例による入力回路である。すな
わち、入力端子１をＭＯＳ）ランジスタ２．３と、トラ
ンジスタ９のドレインならびにＨＴインバータ６の入力
に接続する。ＭＯＳ）ランジスタ２，３のドレインは、
ＭＯＳトランジスタ４のドレインに接続され、さらにイ
ンバータ５０入力に接続されている。また、ＨＴインバ
ータ６の出力はＮＡＮＤゲート７の入力に接続され、Ｎ
ＡＮＤゲート７の出力はＮＡＮＤゲート８の入力に接続
される。ここでＮＡＮＤゲート８の他方の入力は電源投
入時のリセット回路に接続されている。さらにＮＡＮＤ
ゲート８の出力は、インバータ１１の入力ならびにトラ
ンジスタ９のゲートに接続され、インバータ１１の出力
はトランジスタ１０のゲートに接続されてお如、トラン
ジスタ９のソース、トランジスタ１０のドレインは接続
されて、さらにトランジスタ４のゲートに接続されてい
る。FIG. 1 shows an input circuit according to an embodiment of the present invention. That is, the input terminal 1 is connected to the MOS transistor 2.3, the drain of the transistor 9, and the input of the HT inverter 6. MOS) The drains of transistors 2 and 3 are
It is connected to the drain of MOS transistor 4 and further connected to the input of inverter 50. Further, the output of the HT inverter 6 is connected to the input of the NAND gate 7,
The output of AND gate 7 is connected to the input of NAND gate 8. Here, the other input of the NAND gate 8 is connected to a reset circuit when the power is turned on. Furthermore, NAND
The output of gate 8 is connected to the input of inverter 11 and the gate of transistor 9, the output of inverter 11 is connected to the gate of transistor 10, the source of transistor 9 and the drain of transistor 10 are connected, and Connected to the gate of transistor 4.

第１図の動作を第２図のタイムチャートを使って説明す
る。まず、電源が投入された時間ａで、ＮＡＮＤゲート
８の出力はゝＨ，，ＮＡＮＤゲート７の出力はゝゝＬ　
ｔ＋に設定される。従って、トランジスタ９はＯＮＩ、
、トランジスタ１０はＯＦＦしているため、トランジス
タ４のゲートはトランジスタ３と等しく、駆動レベルに
追従してレベルが動く様に女っている。時間すでは、ま
ず駆動レベルが１の場合に示すとおり、ＨＴインバータ
のしきい値を起えるとＮＡＮＤゲート７の出力は、Ｌ→
Ｈに変化し、さらにＮＡＮＤゲート８の出力はＨ→Ｌと
変化する。これを受けてトランジスタ９はＯＦＦし、ト
ランジスタ１０がＯＮすることでトランジスタ４の入力
はＧＮＤレベルに固定され駆動レベルに不感となる。次
に駆動レベルが２の場合には、ＨＴインバータの出力は
変化しないので、トランジスタ４のゲートレベルは時間
ａの場合と同じく、駆動レベルに追従して動く。The operation shown in FIG. 1 will be explained using the time chart shown in FIG. 2. First, at time a when the power is turned on, the output of the NAND gate 8 is ``H'', and the output of the NAND gate 7 is ``L''.
It is set to t+. Therefore, transistor 9 is ONI,
Since the transistor 10 is OFF, the gate of the transistor 4 is equal to that of the transistor 3, and its level changes in accordance with the drive level. As shown in the case where the drive level is 1, when the threshold of the HT inverter is raised, the output of the NAND gate 7 changes from L to
The output of the NAND gate 8 changes from H to L. In response to this, the transistor 9 is turned off and the transistor 10 is turned on, so that the input of the transistor 4 is fixed at the GND level and becomes insensitive to the drive level. Next, when the drive level is 2, the output of the HT inverter does not change, so the gate level of the transistor 4 follows the drive level as in the case of time a.

以上に述べた事から、トランジスタ４がトランジスタ３
にパラレルに入るか入らないかによ、す、入力回路とし
てのしきい値は図２の如く変化し、駆動レベルに対し最
適値をとるものである。From what has been stated above, transistor 4 is transistor 3
Depending on whether or not parallel input occurs, the threshold value of the input circuit changes as shown in FIG. 2, and takes the optimum value for the drive level.

以上の様に本発明による入力回路は、駆動回路が種々変
化する可能性があるシステムにおいて、常に最適な入力
のしきい値を得るうえで有効な手段である。As described above, the input circuit according to the present invention is an effective means for always obtaining an optimal input threshold in a system where the drive circuit may change variously.

また本説明では、２棟類の入力レベルについての一回路
例を示したが、これは便宜上のものであり、よって本発
明として回路構成、レベルの種類を規定するものではな
い。In addition, in this description, an example of a circuit for input levels of two buildings has been shown, but this is for convenience and does not define the circuit configuration or the type of level according to the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す回路図、第２図は第１
図における各部のタイミングチャートである。 ｌ・°・・・・入力端子ｓ　２　＋　３　＋　４．６　
＋　９・・・・・・ＭＯＳトランジスタ、５．１１叫・
°インバータ、６・°。 ・・・ＨＴインバータ、７，８・旧・・ＮＡＮＤゲート
。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
It is a timing chart of each part in a figure. l・°・・・Input terminal s 2 + 3 + 4.6
+ 9...MOS transistor, 5.11
°Inverter, 6°. ...HT inverter, 7, 8, old...NAND gate.

Claims (1)

【特許請求の範囲】[Claims] 論理集積回路において、その論理入力のしきい値を上記
論理集積回路を駆動する個々独立の駆動回路出力のレベ
ルにより、最適値を選択するようにしたことを特徴とす
る入力回路。1. An input circuit in a logic integrated circuit, wherein an optimum value of a threshold value of a logic input is selected depending on the output level of each independent drive circuit that drives the logic integrated circuit.
JP58224837A 1983-11-29 1983-11-29 Input circuit Granted JPS60117820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224837A JPS60117820A (en) 1983-11-29 1983-11-29 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224837A JPS60117820A (en) 1983-11-29 1983-11-29 Input circuit

Publications (2)

Publication Number Publication Date
JPS60117820A true JPS60117820A (en) 1985-06-25
JPH0552688B2 JPH0552688B2 (en) 1993-08-06

Family

ID=16819950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224837A Granted JPS60117820A (en) 1983-11-29 1983-11-29 Input circuit

Country Status (1)

Country Link
JP (1) JPS60117820A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6276319A (en) * 1985-09-27 1987-04-08 Nec Corp Semiconductor integrated circuit device
WO1997023045A1 (en) * 1995-12-19 1997-06-26 Micron Technology, Inc. Asynchronous self-adjusting input circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5385133A (en) * 1976-12-30 1978-07-27 Matsushita Electric Works Ltd General-purpose interface circuit for digital signal
JPS55141825A (en) * 1979-04-24 1980-11-06 Fujitsu Ltd Cmos output circuit
JPS5710533A (en) * 1980-06-23 1982-01-20 Nec Corp Logical circuit
JPS58137328A (en) * 1982-02-10 1983-08-15 Nec Corp Input circuit
JPS5942646U (en) * 1982-09-09 1984-03-19 日本電気株式会社 input circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2530070C2 (en) * 1975-07-05 1984-10-04 Basf Ag, 6700 Ludwigshafen Insect repellants

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5385133A (en) * 1976-12-30 1978-07-27 Matsushita Electric Works Ltd General-purpose interface circuit for digital signal
JPS55141825A (en) * 1979-04-24 1980-11-06 Fujitsu Ltd Cmos output circuit
JPS5710533A (en) * 1980-06-23 1982-01-20 Nec Corp Logical circuit
JPS58137328A (en) * 1982-02-10 1983-08-15 Nec Corp Input circuit
JPS5942646U (en) * 1982-09-09 1984-03-19 日本電気株式会社 input circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6276319A (en) * 1985-09-27 1987-04-08 Nec Corp Semiconductor integrated circuit device
WO1997023045A1 (en) * 1995-12-19 1997-06-26 Micron Technology, Inc. Asynchronous self-adjusting input circuit

Also Published As

Publication number Publication date
JPH0552688B2 (en) 1993-08-06

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