JPS6149688B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key input circuit for electronic watches, etc., and more particularly to a key input circuit that connects switch contacts between electrodes wired in a matrix and detects key operations based on timing signals. .

Generally, large-scale integrated circuits (LSI) are used in electronic clocks and electronic desktop calculators.
When connecting LSI and many switches, LSI
In order to reduce the number of terminals required, a key input method using timing signals is adopted. However, when such an electronic clock or the like is incorporated into other equipment such as audio equipment, mutually generated noise often becomes a problem, and in particular, timing signals applied to switches may enter the audio equipment. Therefore, in such a case, a corresponding method that does not use a timing signal, that is, a method in which the switch is directly connected to the terminals of the LSI, is used, but this case has the disadvantage that the number of terminals of the LSI increases. As described above, the key input method using a timing signal and the correspondence method have mutually contradictory drawbacks.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a key input circuit that completely eliminates the conventional drawbacks. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention.

S _W1 to S _W9 are switches connected between electrodes in which timing signal T ₁ to T ₃ lines and input signal I ₁ to _{I 3} lines are wired in a matrix, and 1 is a timing signal T ₁
The timing generation circuit 2 for generating ~ _T3 prevents chattering that occurs in the input signals I1 to I3 when any of the switches _SW1 to _SW9 is closed, and also prevents chattering that occurs in the input signals _I1 to _I3 when the switch is closed A memory circuit 3 that holds the output during the period of time is applied with signals T _{1 '} to T _{3 '} having the same timing as the output of the memory circuit 2 and the timing signals T ₁ to _{T 3} of the timing generation circuit 1,
4 is an input dividing circuit that outputs a signal corresponding to a closed switch, and 4 is a timing generation circuit 1 that detects whether any of the switches S _W1 to S _W9 is opened or closed.
5 is a frequency divider circuit that divides the reference frequency signal f ₀ to a desired frequency; 6 is a frequency divider circuit that applies the divided output signal f ₁ of the frequency divider circuit 5 to the timing generation circuit 1; There is a gate circuit that controls this using the output signal _Q1 of the input detection circuit 4.

The timing generation circuit 1 includes a counter 7 that divides the frequency signal _f1 applied via the gate circuit 6.
and NAND gates 9, 10, 11 to which either of the frequency-divided output signals φ ₁ and φ ₂ of the counter 7 and ₁ and ₂ obtained via the inverter 8 are applied to generate signals T ₁ ′ to T ₃ ′. , NAND gate 9, 10, 1
MOS transistor 1 provided corresponding to 1
2, 13, 14 and resistors R ₁ , R ₂ and R ₃ , and the gate electrodes of the MOS transistors 12, 13, 14 are connected to corresponding NAND gates 9, 1, respectively.
Output signals T ₁ ' to T ₃ ' of 0 and 11 are applied, and a power supply voltage V is applied to each drain electrode. Furthermore, the source electrodes of the MOS transistors 12, 13, and 14 are connected to one electrode of the switches _SW1 to SW9 as timing signals _T1 to _T3 , respectively, and the resistors _R1 , _{R2 ,} and _R3 are connected to the power supply voltage V. connected between. Memory circuit 2 is a delay type flip-flop 1
5, 16, 17 and resistors R ₄ to R ₆ connected to their input terminals D, and the other electrodes of the switches S _W1 to S _W9 are connected to the input terminal D as input signals I ₁ to I ₃ . The input dividing circuit 3 is composed of NOR gates _G1 to _G9 , which are NOR gates _G1 to _G3 , _G4 to _G6 , and _G7.
One input terminal of ~ _G9 is connected to the outputs _{2 and 2} of the corresponding delay flip-flops 15, 16, and 17, respectively.
₃ and ₄ are applied, and the output signals T ₁ ' to _{T 2} ' of the timing generation circuit 1 are applied to the other input terminal, respectively, and the output signals S ₁ of the NOR gates G ₁ to _{G 9} are applied.
_-S9 correspond to switches _SW1 to _SW9 , respectively.
The input detection circuit 4 is an OR circuit to which input signals I ₁ to I ₃ are applied.
It consists of a gate 18 and a delay type flip-flop 19 to which the output of the OR gate 18 is applied, and the state is synchronized with the frequency _f1 that is always applied to the clock terminal CL when any of the switches S _W1 to S _W9 is closed. The output Q ₁ is applied to the gate circuit 6 to control the cutoff and conduction of the frequency f ₁ .

Next, the operation will be explained with reference to the timing chart shown in FIG.

The signals T ₁ ′ to T ₃ ′ generated from the outputs φ ₁ and φ ₂ of the counter 7 are signals that sequentially become “0” level in a time-division manner, and these signals T ₁ ′ to T ₃ ′ are applied.
Since the MOS transistors 12, 13, and 14 are transistors with P-type channels, the signal
They are sequentially turned on during the period when T ₁ ′ to T ₃ ′ are at the “0” level. If none of the switches S _W1 to _{S W9} are closed now, the MOS transistors 12 and 1 are closed regardless of whether they are in the "on" state or the "off" state.
Since the outputs of the circuits 3 and 14 are pulled up to the power supply voltage V by the connected resistors _R1 to _R3 , the timing signals _T1 to _T3 remain at the "1" level.

On the other hand, the relationship between the source-drain impedance R _SD of the MOS transistors 12, 13, and 14 in the "on" state and the resistors R ₁ to R ₆ is as follows: R _SD ≪R ₄ to R ₆ ≪ R ₁ to R ₃ It has a satisfactory value.

For example, if switch S _W2 is closed at point A shown in Figure 2, the timing signal
The MOS transistor 13 that outputs T ₂ is in the "off" state at point A, and since R ₄ ≪ R ₂ , the timing signal T ₂ is "0", which is the same as the input signal I ₁ .
become the level. At this time, the delay type flip-flop 15 of the memory circuit 2 maintains its state, its output ₂ is at the "1" level, and the signal applied to the NOR gate G ₂ of the input dividing circuit 3.
Since T ₂ ' is also at the "1" level, the output signal S ₂ is at the "0" level.

From this state, when the timing when the signal T ₂ ' becomes "0" level, the MOS transistor 13 becomes "on" state, and since R _SD ≪ R ₄ , the input signal I ₁
And the timing signal _T2 is pulled up to the "1" level. When the input signal _I1 reaches the "1" level, the state of the delay flip-flop 15 is inverted in synchronization with the frequency signal _f1 applied to its clock terminal CL via the gate circuit 6. At this time, since the signal T ₂ ' is at the "0" level, the NOR gate G ₂ to which this signal T ₂ ' is applied outputs the output S ₂ by the output ₂ of the delay type flip-flop 15 which is at the "0" level.
is the “1” level.

On the other hand, the input signal _I1, which has reached the "1" level, is applied to the delay type flip-flop 19 via the OR gate 18 of the input detection circuit 4, and the delay type flip-flop 19 is inverted in synchronization with the frequency signal _f1 . Set output Q ₁ to “1” level. This output Q ₁ is applied to the gate circuit 6, so the gate circuit 6 cuts off the frequency signal f ₁ from the frequency divider circuit 5, stops the operation of the timing generation circuit 1 as it is, and delays the memory circuit 2. type flip flop 1
5, 16, and 17 are stopped. Accordingly
The output _S2 of the NOR gate _G2 remains at the "1" level.

Furthermore, if _{switch SW2} is opened at point B shown in FIG.
It is applied to a delay type flip-flop 19 via an OR gate 18. Delayed flip-flop 19
Since the frequency signal f ₁ is constantly applied to the clock terminal CL of the device, when the input signal I ₁ reaches the “0” level, it is inverted in synchronization with the frequency signal f ₁ , and its output Q ₁ becomes “0”. "become. Therefore, gate circuit 6
conducts the frequency signal f ₁ and restarts the operation of the timing generation circuit 1, and at the same time applies the frequency signal f ₁ to the memory circuit 2. Therefore, the delay type flip-flop 15 whose output ₂ was at the "0" level is inverted. The output ₂ is set to "1" level. Therefore, the output _S2 of the NOR gate _G2 changes from the "1" level to the "0" level, indicating that the switch _SW2 is opened.

In this way, when none of the switches _SW1 to _SW9 are closed, the timing signals _T1 to _T3 are "1".
The level remains unchanged, Switch S _W1 ~S
Timing signal only when either _W9 is closed
A signal is applied to one of the input signals I ₁ to _{I 3} depending on the timing of T ₁ to T ₃ , and at the same time, the operations of the timing generation circuit 1 and the memory circuit 2 are stopped, so that the switches _SW1 to S The output signals S ₁ to _{S 9} of the input dividing circuit 3 indicating that any one of _W9 is closed are fixed. On the other hand, when the closed switches are opened, the timing generating circuit 1 and the memory circuit 2 start operating again, and the input dividing circuit 3 no longer outputs a signal indicating that the switches _SW1 to _SW9 are closed. That is, depending on the opening and closing of the switches S _W1 to _{S W9} , signals S ₁ to S ₉ corresponding to the switches S _W1 to S _W9 are output corresponding to the opening and closing times of the switches S _W1 to _{S W9} . The same switch signal as the corresponding equation can be obtained.

As described above, according to the present invention, the switches S _W1 to _{S W9}
is not closed, the timing signals T ₁ to _{T 9}
remains at the “1” level, and switch S
This prevents the generation of noise from _{the wiring connected to switches SW1 to SW9 .}
This has the advantage that the number of IC terminals connected to the circuit is reduced, and the same switch signals S ₁ to _{S 9} as in the conventional corresponding system can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. 1... Timing generation circuit, 2... Memory circuit,
3...Input division circuit, 4...Input detection circuit, 5...
...Frequency divider circuit, 6...gate circuit.

Claims (1)

[Claims] 1 A plurality of switches, a timing generation circuit for applying timing signals to the plurality of switches, a memory circuit for storing input signals generated by opening and closing of the switches, and an output of the memory circuit based on the timing of the timing generation circuit. A key input circuit comprising an input dividing circuit that is controlled by a signal synchronized with a signal and outputs a signal corresponding to the switch, and an input detection circuit that detects opening/closing of the switch and controls the timing generation circuit and the storage circuit. The timing generation circuit includes a plurality of MOSFETs for transmitting the timing signal, and a first resistor that holds a signal line to which the timing signal is output at a first potential, and , the memory circuit is
A second resistor is provided to hold the input line at a second potential, and when the switch is closed, the voltage divided by the first resistor and the second resistor is applied to the MOSFET. A key input circuit characterized in that the input is generated by changing to a first potential side.