JPS62258514A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To reduce the delay time until a data is outputted after a clock pulse is changed by outputting an input data immediately when the clock is changed to the 2nd output terminal. CONSTITUTION:When the clock pulse K inputted from a clock pulse input terminal 12 is changed to a high level, the data D inputted from a data input terminal 11 is outputted directly to a data output terminal Q2 provided to the outside of a D latch circuit FF via an N-channel MOSFETq2 turned on by the clock pulse CK of a high level. On the other hand, the input data D is fed alto to the latch circuit FF and latched at the output terminal Q2 of the latch circuit FF.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a signal control technology and a technology that is particularly effective when applied to control of a data signal latch, for example, when applied to a clock synchronous flip-flop circuit. Concerning effective techniques.

[Background Art] There is a D-type flip-flop circuit as shown in FIG. This D-type flip-flop is composed of logic gates 1 to 6, and has a data input terminal 11, a control input terminal 12, and output terminals Q and d. The outputs Q and ζ are output when the control input terminal 12 is at low level (hereinafter referred to as "L").
If the control input terminal 12 is set to a high level (hereinafter referred to as 11H" level), the previous level is maintained regardless of the input signal of the input terminal 11. The signal level of the input terminal 11 at that time.

Each level is determined according to the

FIG. 3 is a time chart when data is input to the D-type flip-flop shown in FIG.

When the data input terminal 11 is at the "L" level, the clock pulse CK changes from the i'Ln level to the "H" level.
”When the level is changed, the logic gate 5
The signal Q output from the output terminal of is set to the "L" level. Conversely, if the control input terminal is set to the 11HTl level while the input terminal 11 is set to the "Hn level," The signal Q is brought to the rtH" level. In this case, the change in the signal Q is not simultaneous with the rise of the clock pulse, but is delayed by the non-negligible delay characteristics caused by the logic gates 1 to 6, as shown in FIG. Thus, a delay time Td is generated with respect to the clock pulse CK.

Therefore, in a circuit such as a shift register or a counter circuit in which a plurality of flip-flops are continuously connected, the delay time of the entire circuit becomes relatively large.

[Object of the Invention] An object of the present invention is to provide a flip-flop circuit with a short delay time from when a clock pulse is changed to when data is output.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, between the data input terminal of a lock synchronized latch circuit such as a D-type flip-flop and a second data output terminal provided outside the flip-flop, and between the first output terminal and the second data output terminal. By providing gate means each controlled by a clock between the output terminal and outputting the input data to the second output terminal immediately when the clock changes, the data is not output after the clock pulse is changed. This achieves the above objective of shortening the delay time until the

[Example] FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In the figure, the circuit FF is surrounded by a two-dot chain line.

This is a latch circuit configured by logic gates 1 to 6 shown in the figure.

The illustrated reference numeral 11 is a data input terminal. CK is a clock pulse that provides timing for taking in data D input from the data input terminal 11. Latch circuit FF
In this embodiment, externally, a P-channel MO3FETq□ and an N-channel MO3FET are used as transfer gates.
A circuit S having a complementary MO3 configuration consisting of 5FETq2 is provided.

This circuit is controlled by a clock pulse CK input from a clock pulse input terminal 12.

The P-channel MOSFET q□ is connected in series between the output terminal Q2 of the D-type latch circuit FF and the output terminal Q provided outside the D-type latch circuit FF. The N-channel MOsFETqz is directly connected between the data input terminal 11 and the output terminal Q of the latch circuit FF.

For example, when the clock pulse CK input from the clock pulse input terminal 12 changes to "H" level, the data D input from the data input terminal 11 becomes LL H.
N turned on by Tl level clock pulse GK
D-type latch circuit F via channel MO3FETq2
It is directly output to a data output terminal Q2 provided outside F. On the other hand, the input data D is also supplied to the latch circuit FF, and passes through each logic gate that constitutes the latch circuit F.
It is latched to the output terminal Q2 of F. Here, when the clock pulse CK is changed to the "it L" level, "L 1
P channel MO3 turned on by 1 level signal
The latched data is output to the output terminal Q2 of the latch circuit FF via the FETq. At the same time, the transmission of data D that had been supplied to output terminal Q□ through N-channel MO8FETq2, which had been turned on, was cut off, and even if data D changed thereafter, it did not affect output terminal Q. The signal latched in the latch circuit FF is output.

As described above, when the clock pulse CK supplied to the latch circuit FF is changed to the "H" level, the input data D from the data input terminal 11 is transferred to the N-channel MOSFET (1) provided in parallel with the latch circuit FF. , and directly to the data output terminal QE, it is possible to shorten the delay time Td from the rising edge of the clock pulse GK until the data is output to the output terminal Q1.

Furthermore, in the above embodiment, a P-channel MO5FET (1) and an N-channel MOSFET (1) and an N-channel MOSFET (1, E T q z, also N channel/L
/P channel /l/MO5F in parallel with MO3FETq2
It is also possible to use a so-called transmission gate formed by connecting ETq.

[Effect] Between the data input terminal of a synchronous latch circuit such as a D-type flip-flop and a second data output terminal provided outside the flip-flop, and between the first output terminal and the second data output terminal.
By providing gate means controlled by a clock between the output terminals of the second output terminal and the second output terminal, the input data is immediately outputted to the second output terminal when the clock pulse changes. The effect of shortening the delay time until the output of It goes without saying that various changes can be made without departing from the gist of the invention.For example, in the above embodiment, the circuit S having a complementary MO5 configuration provided outside the flip-flop is controlled only by the clock pulse GK. However, by using a clock pulse that changes at a timing different from the clock pulse CK, the P-channel MO8FETq1
Alternatively, it is also possible to control one of the N-channel MOS FET q x and the other using the clock pulse CK.

Furthermore, in the above embodiment, the data being output to the output terminal Q provided outside the flip-flop is MOSFET
Although it is controlled by a transmission gate consisting of an ET, it is also possible to control it by using a gate circuit such as an AND gate.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, which is the control of the data signal latch of a D-type flip-flop circuit, but the present invention is not limited to this. It can be applied to general circuits that capture and output data using clock pulses.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention applied to a D-type flip-flop, and FIG. 2 is a circuit diagram showing an example of a conventional D-type flip-flop. The third is the time chart of FIG. 1 to 6...Logic gates constituting a D-type flip-flop, 11...Data input terminal, 12...Clock pulse input terminal, Q, Q,...Data output terminal, q □・・・P channel MO3FET, q2・
...N-channel MO3FET. Figure 2 Figure 3 Procedure correction band (method) Showa 6 similar May 27th

Claims (1)

[Claims] 1. It has an input terminal and a control input terminal, and when the control input terminal is at a first level, the output level is determined by the signal at the input terminal, and the control input terminal is at a first level. a latch circuit whose output level is maintained at the previous level regardless of the signal at the input terminal when the control input terminal is at the second level; and an output terminal that outputs the signal at the input terminal when the control input terminal is at the first level. and a transmission gate circuit that transmits the output of the latch circuit to the output terminal when the control input terminal is at a second level. 2. The flip-flop circuit according to claim 1, wherein the transmission gate circuit comprises complementary transistors that are switched in a complementary manner by a control signal from the control input terminal.