JPH0265521A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To reduce the stray capacitance and to decrease the delay or deterioration in a clock signal by adopting the constitution such that no other transistor(TR) is connected in parallel with a TR controlled by a clock signal. CONSTITUTION:A set/reset TR being connected in parallel with a clock TR 1 is eliminated, TRs 61, 62 are connected in series with TRs 12, 13 forming a data input TR pair in a master circuit 55 and TRs 63, 64 are connected in parallel with a series circuit comprising TRs 12, 61 and 13, 62. TRs 71, 72 are connected in series with TRs 22, 23 forming a data input TR pair respectively and TRs 73, 74 are connected in parallel with a series circuit comprising the TRs 22, 71 and 23, 72. Furthermore, the TRs 61, 72 are driven by an inverted reset signal, inverse of R, the TRs 62, 71 are drive signal by an inverted set signal, inverse of S, the TRs 63, 74 are driven by a set signal S and the TRs 64, 73 are driven by a reset signal R respectively.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a flip-flop circuit with a set terminal and a reset terminal in a semiconductor integrated circuit, and in particular to a flip-flop circuit with an improved set and reset means.
It is related to circuits.

[Prior Art] A flip-flop circuit shown in FIG. 2 has been known as a flip-flop circuit with set and reset terminals suitable for high-speed operation.

This circuit has a first clock transistor 1 driven by a clock signal CK at the input stage, and a second clock transistor 2 driven by a clock inversion signal node.
are provided, and these transistors 1.2 and diodes 3.
The internal clock signal ICK1.4 level-shifted at ICK1.
ICK2 is supplied to the master circuit 5 and the slave circuit 6, and the data signal and data inversion signal are sequentially latched to the master circuit 5 and the slave circuit 6 in synchronization with the internal clock signal.
and slave circuit 6 with set signal S and reset signal R.
It can be set and reset as appropriate.

The data signal and the data inversion signal drive transistors 12 and 13, respectively, in synchronization with the ON operation of transistor 11 driven by internal clock signal ICK2. Each output of transistors 12 and 13 is connected to transistor 1
The master output signals Q' and Q- are fed back to the gates of transistors 18 and 19 via diodes 16 and 17, respectively. Therefore, in synchronization with the ON operation of the transistor 20 driven by the internal clock signal ICKI, the data signal and data inversion signal port are latched by the transistors 18 and 19. Then, the master output signals Q' and ``are given as data signals and data inversion signals to the slave circuit 6.The slave circuit 6 also performs the same operation as described above using transistors 21 to 25, 28 to 30 and diodes 26 and 27.

When the set signal S or the reset signal R is input, the transistor 31 or 32 connected in parallel with the clock transistor 1 is turned on, and the transistor 20.
30 and transistors 31, 34 or 3
Transistor 18.29 or 19.2 by 2.33
8 is short-circuited to realize a set or reset operation.

Note that the transistors 35 to 42 are transistors that apply a bias voltage based on the bias signal B.

[Problems to be Solved by the Invention] The conventional flip-flop circuit with set and reset terminals described above has transistors 31 and 32 controlled by a set signal S and a reset signal R in parallel with the transistor 1 for clock signal input. Since the transistors 31 and 32 are connected, the stray capacitance caused by the transistors 31 and 32 cannot be ignored. Especially when operating at high speed, the internal clock signal ICKI, 2 may be delayed and affect the delay time of the flip-flop circuit, and the stray capacitance may This may cause waveform deterioration.

Therefore, there was a problem in that the operating frequency could not be sufficiently increased.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a flip-flop circuit that can reduce stray capacitance at a clock signal input section and significantly increase the operating frequency.

[Means for Solving the Problems] A flip-flop circuit according to the present invention includes a first transistor driven by a data signal among transistors forming a data input transistor pair, and a reset inversion circuit connected in series with this transistor. a second transistor driven by a signal; a second series circuit of transistors, a third transistor connected in parallel and driven by a set signal, and a fourth transistor of the transistors forming the data input transistor pair driven by a data inversion signal; a fifth transistor connected in series with this transistor and driven by a set inversion signal; A sixth transistor is connected in parallel with the series circuit of the fifth transistor and driven by a reset signal.

In the present invention, the first . No other transistor is connected in parallel with the second clock transistor.

[Function] Conventionally, the short-circuiting of a pair of transistors for data retention was performed in synchronization with only one of the internal clock signals, so the transistor for forcibly fixing this internal clock signal was used for clock input. It was necessary to install it in parallel with the transistor. However, according to the present invention, in addition to the short-circuiting transistor of the data holding transistor pair, the third and sixth transistors are provided for shorting the data input transistor pair synchronized with the other clock of the internal clock signal. Therefore, regardless of the condition of the internal clock 7713, setting and resetting operations can be performed. Therefore, there is no need to provide means for forcibly fixing the internal clock signal. Further, according to the present invention, the second .
The fifth transistor is connected and these are controlled by the reset inversion and self-inversion signals, so even if data is written at the time of set reset, the data write path is cut off and the set and reset operations are ensured. act so that it can be carried out.

In the present invention, since no other transistor is connected in parallel with the clock transistor, the stray capacitance connected to the clock transistor can be reduced, and the operating frequency can be significantly increased.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a flip-flop circuit according to an embodiment of the present invention.

In FIG. 1, the same parts as in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

The first difference between the circuit of this embodiment and the conventional circuit shown in FIG. 2 is that the set and reset transistors 31 and 3 are connected in parallel with the clock transistor.
2 has been deleted.

The second point is that in the master circuit 55, the transistors 1 to 12 forming the data input transistor pair,
Transistors 61 and 62 are connected in series with 13, respectively,
The point that transistors 63.64 are connected in parallel with the series circuit of transistors 12.61 and 13.62, respectively,
In the slave circuit 56, transistors 71 and 72 are connected in series with the transistors 22 and 23, respectively, constituting the data input transistor pair.
．． The point is that transistors 73 and 74 are connected in parallel with the series circuits 71 and 23 and 72.

Note that transistors 61 and 72 are driven by a reset inversion signal, transistors 62 and 71 are driven by a set inversion signal, and transistors 63 and 74 are driven by a set signal S.
The transistors 64 and 73 are driven by the reset signal R
It is driven by

In the above configuration, when the set signal S becomes "1'°, both transistors 31.63 become conductive. These transistors 31.63 are connected to the transistors 20.1 and 20.1, respectively.
1, so the internal clock signal ICKI,
Regardless of whether ICK2 takes a value of "1" or "0", the output terminal of transistor 31.63 becomes "0", while the output terminal of transistor 32.64 becomes "1", so transistor 14.15 become non-conductive and conductive, respectively, and the output signals Q' and Q' become "1" and "0", respectively.

As a result, transistors 18 and 19 become conductive.

It becomes non-conductive and maintains the set state. At this time, since the set inversion signal is "0", the transistor 62 is non-conductive. Therefore, even if the data inversion signal becomes "1", the output of the transistor 19 will be "1". maintain.

On the other hand, when the reset signal R becomes °'1'', both transistors 32 and 64 become conductive.
2.64 are connected to the transistor 2011, respectively, so as mentioned above, the output of the transistor 32.64 is "0" regardless of the internal clock signals CKI and ICK2.
”, while the output of transistor 31.63 is 1”
Therefore, l transistors 1, 4, and 15 are conductive, respectively.
It becomes non-conductive, and each output signal Q'1 becomes '''O''
“1”, resulting in transistor 18.19
become non-conductive and conductive, respectively, to maintain the reset state.

At this time, since the reset inversion signal R is 0'', the transistor 61 is non-conductive. Therefore, even if the data signal becomes ``1'', the output of transistor 18 remains ``1''.

Note that the operation of the slave circuit 56 is also the same as described above, so the details thereof will be omitted.

Thus, according to this embodiment, the correct set.

Reset operation can be performed. Further, since no other transistor is connected in parallel to the clock transistor 1.2, stray capacitance can be reduced.

In the above embodiments, the flip-flop circuit is constructed of FETs, but the effects of the present invention can also be obtained even if the flip-flop circuits are constructed of bipolar transistors.

[Effects of the Invention] As explained above, the present invention has a configuration in which no other transistor is connected in parallel to a transistor controlled by a clock signal, so stray capacitance can be reduced, and clock signal delay and deterioration can be reduced. Normally, the clock signal is the signal that operates fastest in a flip-flop circuit, so the present invention is extremely effective in improving the frequency characteristics of high-speed flip-flop circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a flip-flop circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional flip-flop circuit. 5.55; Master circuit, 6,56; Slave circuit

Claims (1)

[Claims] (1) a first clock transistor that is driven by a clock signal and outputs a first internal clock signal; a second clock transistor that is driven by an inverted clock signal and outputs a second internal clock signal; 1. A pair of data input transistors each inputting a data signal and an inverted data signal in synchronization with one of the second internal clock signals, and a pair of data input transistors in synchronization with the other of the first and second internal clock signals. a flip-flop comprising a data holding transistor pair that holds the input data signal and data inversion signal respectively, and a reset transistor pair that short-circuits the data holding transistor pair based on a set signal or a reset signal. In the circuit, a first transistor of the transistors forming the data input transistor pair is driven by a data signal, a second transistor connected in series with this transistor and driven by a reset inversion signal, and the first transistor is connected in series with the transistor and driven by a reset inversion signal;
, a third transistor connected in parallel with the series circuit of the second transistors and driven by a set signal; and a fourth transistor among the transistors forming the data input transistor pair and driven by a data inversion signal; A fifth transistor connected in series with this transistor and driven by a set inversion signal, and a sixth transistor connected in parallel with the series circuit of the fourth and fifth transistors and driven by a reset signal. , and a flip-flop circuit characterized in that no other transistor is connected in parallel with the first and second clock transistors.