JPS6276319A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To select the input level of an input circuit by connecting the gate of a MOSFET constituting an inverter to the input of other inverter via a selection cut-off element. CONSTITUTION:Assuming the channel widths WP of P-channel MOS transistors (TRs) 5, 10 as respectively '1', '9', and the channel width WN of an N-channel MOS TR 6 as '5'. The channel width ratio WP/WN when the selection cut-off element 11 is not cut off goes to '2' and the input level goes to 2.5V. When the element 11 is turned off, the TR 10 is made nonconductive. Thus, the channel width ratio W>=P/WN goes to 0.2 and the input level goes to 1.6V. Then the inverter 7 acts like an input circuit of TTL level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit device having a CMOS transistor structure.

[Conventional technology]

FIG. 3 is a circuit diagram 7 showing an example of an input circuit of a conventional hardware circuit having a CR, 10S structure. In the case of the P-channel type as well, the gates and drains of the TOS transistor 5 and the N-channel MOS transistor 6 are connected in common, forming an impark 7, and the human power of the inverter 7 is read directly to the input terminal 1 via the resistor 3. . P channel type M
The sources of the OS transistor 5 and the N-channel QMO 8 transistor are connected to the power supply terminal 8 and the ground terminal 9, respectively. The output of the inverter 7 is connected to the output terminal 2, and the output terminal 2 is further connected to the internal gate of the integrated circuit device. The anode of the diode 4 is connected to the ground terminal 9, and the cathode is connected to the input terminal 1 through the resistor 3.The resistor 3 and the diode 4 are connected to the input terminal 1 when an abnormal input, such as 靜'1 qi, is applied to the input terminal 1. A protection resistor and a protection diode are used to protect the input gate of the inverter.

The input level in an integrated circuit having a CMOS structure (hereinafter referred to as CMOS level) is 2 when the power supply voltage is 5V.
．． On the other hand, the input level (hereinafter referred to as TTLI/Bell) in an integrated circuit having a TTL structure is often set to around 1.5V, assuming that the power supply voltage is 5V. The power supply voltage is vDD, the length of the LP channel type MOS transistor is Lp, the channel width is Wp,
(, the threshold voltage is VTP, the hole mobility is IP, the channel length of the N-channel MOS transistor is LN,
When the channel @ is WN, the L threshold voltage is VTN, and the electron mobility is )lN, the drain currents Inp and IDN of the P-channel MOS transistor and the N-channel fiMO8 transistor can be expressed as follows. In the equations (1) and +2, εox is the dielectric constant of the gate oxide film, and fax is the thickness of the gate oxide film. Here, when trying to configure an input circuit for CMO8+ and Bell, the input level is 2.515 VDD, that is, πVnulC>ite IE) p = II) N fx
O(1) - (2) Equation yoTl)... (3) Therefore, the channel width ratio Wp/Ws is expressed by the following equation.

On the other hand, when I tried to configure a TTL level input circuit, the input level was 1.515-Von Vc>E7-5ID
P = IDN and the channel width ratio W P/W
N can be expressed as. (4), Lp in equations (5)
, Vtp, j/p.

If Ls, VTs, )lpi and vDD are set to constant values, one input novel can be set by changing the channel width ratio Wp/WN. Generally, when configuring a CMOS level input circuit, the channel width ratio is WP/W.
N middle school 2. When configuring a TTL+/Bell input circuit, the channel width ratio should be 0.2 in Wp7'NN. Set Lp, Vrp, j/p, LN, and VrNJ/N'.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuit described above has the disadvantage that it has only one input level that is completely fixed in design, and that it requires a lot of management effort.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can select one of two types of input 1/bell.

[Failure to solve the problem]

In the semiconductor integrated circuit device of the present invention, the input terminal is connected to the gate of the first MOS transistor of the type with the first conductor through the first resistor, and the source and drain of the first MOS transistor are connected to each other. The first conductor 'r! is connected to the power supply terminal and the output terminal, and the second conductor 'r! The gate, drain and source of the second AlO3 transistor of the type are respectively connected to the first
The gate, drain and second MOS transistor of the first conductivity type (or second conductivity type) are respectively connected to the source transistor, and the source, drain and gate of the third MOS transistor of the first conductivity type (or second conductivity type) are respectively connected to the first (or a second power supply terminal), the output terminal and the source thereof via the second resistor, and the common connection point of the gates of the first and @2 MOS transistors and the third MOS transistor. The input circuit includes an input circuit having a selective cutting element connected between the gate of the transistor and the gate of the transistor.

[Actual TA example]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

P-channel type MO8 which is the first MOS transistor
The gate and gate of transistor 5 and second MO8I-transistor N-channel mMOS transistor 6
The twins are connected to form an inverter 7, and the input of the inverter 7 is connected to the input terminal 1 via a resistor 3, which is a first resistor. The sources of the P-channel MOS transistor 5 and the N-channel MOS transistor 6 are connected to a first power supply terminal 8 and a connection terminal 9, which is a ridge terminal of the rabbit 2, respectively. The output of the inverter 7 is connected to the output terminal 2, which is further connected to the internal gate of the integrated circuit device.The source of the P-channel 1iVOS transistor 10, which is the third MOS transistor, is connected to the first power supply The drain is connected to the output of the inverter 7, the gate is connected to the power supply terminal 8 of $1 through a second resistor, a pull-up resistor 12, and the input of the inverter 7 through a selective disconnection element 11. connected to.

The anode of the diode 4 is connected to the ground terminal 9, and the cathode is connected to the input terminal 1 via the resistor 3. Impark 7 and P-channel MO8 transistor 10 constitute an inverter 13.

In this circuit, the channels lj4 WP of the P-channel MO8 transistors 5 and 10 are each 1.9, and the channel width WN of the J-channel fJ OS transistor 6 is 5. Channel width ratio Wp, 1Wnh (when the selected cutting element 11 is not cut)
1,+9)15=2F), the input level is VmaTH
= 2.5V. Therefore, inverter 13 is CMO8
+, becomes the bell input circuit. If the selective cutting element 11 is cut here, the P-channel fiMO8 transistor l
0H1 Since its gate is clamped to the power supply side by the pull-up resistor 12, it becomes non-conductive. Therefore, the channel width ratio Wp/Wpt h 1 / 5 = 0.2, and the input level is VIT) (= 1.6 V torfxl. Therefore, it becomes an input circuit of the i7verter 7HT'l'L level. Note that the selective cutting element 11 may be a Ni--Cr film fuse used in a Hierez-type PROMT.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

Terminals and elements in the drawings with the same numbers as in FIG. 1 are equivalent to those in FIG. 1. N-channel type MO8 transistor 14
The source is connected to the ground terminal 9, the drain is connected to the output of the inverter 7, and the gate is connected to the ground terminal 9 via a pull-down resistor 16 and to the input of the inverter 7 via a selective disconnection element 15, respectively.

In this circuit, the channel width Wp of the P-channel type MOS transistor 5 is 2 and N-channel.

Nell type MO8I-Langistaro, 14 channels @W
Let N be 1 and 9. If the selected cutting element 15 is not cut, the channel width ratio WP/wN is 2/(1+9)
Therefore, input 1/bell becomes VrtH=1.6v. Therefore, the inverter 17 becomes a TTL level input circuit. If the selected cutting element 15 is cut here, N channel f
Since the gate of the iMO8 transistor 14 is clamped to the ground side by the pull-down resistor 16, the iMO8 transistor 14 becomes non-conductive. Therefore, the channel width ratio W p7'N N is 2/1=
It becomes 2.

Input 1/bell becomes VxrH=2.5V. Therefore, the inverter 7 becomes a Cz4 OS level input circuit.

〔Effect of the invention〕

As explained above, the present invention allows the input level of the input circuit to be selected depending on the application, whether it is driven by a CMO8 structure integrated circuit or a TTL structure integrated circuit, depending on whether or not to cut the 1-select cutting element. This also has the effect of saving administrative effort.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of first and second embodiments of the present invention, respectively, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor integrated circuit. 1・−・・Input terminal, 2・−・Output terminal, 3・
...Resistance, 4...Diode, 5...
...P-channel MOS transistor, 6...-
・N-channel MO8 transistor, 7... Inverter, 8--- Power supply terminal, 9-- Ground terminal, 10-- P-channel MO8 transistor, 11... ...Selection cutting element, 12...Resistance, 13...--Invar 9, l4-
...-N-1-Yannel MOS transistor, 15-
...-Selective cutting element, 16.--Resistor, 17.
...Inverter. Kaya 1 Ward 21fJ

Claims (1)

[Claims] The input terminal is connected to the first MO of the first conductivity type via the first resistor.
a second MOS transistor of a second conductivity type;
the gate, drain and source of the transistor are respectively connected to the gate, drain and second power supply terminal of the first MOS transistor, and the source of a third MOS transistor of the first conductivity type (or second conductivity type); A drain and a gate are respectively connected to the first power supply terminal (or a second power supply terminal), the output terminal and the source thereof via the second resistor, and the gates of the first and second MOS transistors are connected to the common A semiconductor integrated circuit device comprising an input circuit having a selective disconnection element connected between a connection point and the gate of the third MOS transistor.