JPH088708A - Analog switch circuit - Google Patents

Abstract

PURPOSE:To apply operating power voltage higher than the level of the inter- terminal breakdown strength by sending the output of a logic circuit to the gate of a transfer FET via a voltage conversion circuit and giving the bias voltage to the source of the FET respectively. CONSTITUTION:The operating power voltage VDD and the analog switch operating power voltage VCC are made 3V and 5V respectively in a logic circuit 38 consisting of a micro-CMOS where the inter-terminal breakdown strength is limited at a low level. When a control signal is inputted to a terminal S to secure conduction of an analog switch, the output of an inverter consisting of CMOS 34 and 35 is set to the potential of the VDD. A voltage conversion circuit 20 converts the VDD potential into the potential of the VDD and sends it to the gate of an NMOS 11 consisting a transfer gate. A bias circuit 29 applies the bias voltage decided in proportion to the VCC to the source of the NMOS 11. When the ratio is properly set between the resistors 25 and 26, both gate-source and drain-gate voltages of the NMOS 11 can be kept at a level lower than the inter-terminal breakdown strength of the CMOS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog switch circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional CMOS analog switch circuit. In FIG. 2, VDD is MOS
Operating power supply voltage, GND is ground, I is signal input terminal, O is signal output terminal, S is control signal input terminal, MOS 6 and 7,
The MOSs 8 and 9 respectively constitute inverters, and are 1, 5,
6 and 8 are P-channel MOS transistors (hereinafter referred to as PMO
It may be abbreviated as S. ) 2, 3, 4, 7, and 9 are N-channel MOS transistors (hereinafter, sometimes abbreviated as NMOS), and NMOS 4 and PMOS 5 are connected in parallel to form a transfer gate, and one end thereof receives a signal. The terminal I and the other end are connected to the signal output terminal O. The input of the inverter composed of the PMOS 6 and the NMOS 7 is the control signal input terminal S, and the output of this inverter is the input of the inverter composed of the PMOS 8 and the NMOS 9, the gate of the NMOS 5, and the PMOS 1.
And NMOS2 are connected to the inputs of the inverter. The drain of the PMOS1 is connected to the signal input terminal I, the source of the NMOS2 is connected to the ground GND, the output of the inverter composed of the PMOS1 and the NMOS2 is connected to the source of the NMOS3 and the substrate of the NMOS4, and the drain of the NMOS3. Is connected to the signal input terminal I. The output of the inverter composed of the PMOS 8 and the NMOS 9 is connected to the gate of the NMOS 3 and the gate of the NMOS 4, respectively.

The operation of the analog switch circuit configured as described above will be described below. First, the time when the analog switch is conducting will be described. When a voltage equal to or higher than the threshold voltage of the inverter composed of the PMOS 6 and the NMOS 7 is input to the control signal input terminal S of FIG. 2, the gate of the NMOS 4 receives the VDD potential and the PMOS 5
The potential of GND is applied to the gate of the signal input terminal I
And the signal output terminal O becomes conductive. Then, the potential of VDD is applied to the gate of the PMOS1 and the potential of VDD to the gate of the NMOS3, so that the PMOS1 and the NMOS3 become conductive, and
The substrate potential of the MOS4 is made equal to that of the signal input terminal I.

Next, the time when the analog switch is cut off will be described. The control signal input terminal S has a PMOS 6 and an NMOS.
When a voltage equal to or lower than the threshold voltage of the inverter configured with 7 is input, the gate of the NMOS 4 has the potential of GND,
The potential of VDD is applied to the gate of the PMOS 5 to cut off the signal input terminal I and the signal output terminal O. And NM
Since the VDD potential is applied to the gate of OS2, NM
OS2 becomes conductive, and makes the substrate potential of the NMOS4 equal to the GND potential.

[0005]

However, in the above-mentioned conventional configuration, a semiconductor process in which the breakdown voltage between the gate and source, between drain and source, and between drain and gate of the MOS transistor is suppressed to a low level by miniaturization of the semiconductor process is adopted. When used, the inverter in the logic circuit has a problem that a high VDD exceeding the withstand voltage value cannot be used because an operating power supply voltage (hereinafter referred to as VDD) voltage is applied between the terminals. It was Also, VD
Since the D voltage is limited by the withstand voltage value, N which constitutes the transfer gate when a signal having a high DC voltage is input.
There is a problem in that the gate-source voltage of the channel MOS transistor cannot be sufficiently secured, the on-resistance becomes large, and further, it is cut off.

The present invention solves such a conventional problem and provides an analog switch circuit capable of suppressing the gate-source voltage and the drain-gate voltage of an N-channel MOS transistor within a withstand voltage range. The purpose is to provide.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention uses a CM output signal of a CMOS logic circuit.
A voltage conversion circuit for converting into an analog switch operating power supply voltage separated from the OS logic operating power supply voltage, and applying this voltage converted control signal to the gate of an N-channel MOS transistor forming a transfer gate when the analog switch is conducting. , A bias circuit for applying a DC potential to the source of the N-channel MOS transistor in proportion to the analog switch operating power supply voltage.

[0008]

According to the present invention, with the above configuration, the voltage between the terminals of the MOS transistor in the analog switch circuit can be suppressed below the withstand voltage, and the on-resistance of the NMOS transistor forming the transfer gate can be made sufficiently small. An analog switch circuit having a high switching speed can be realized.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an analog switch circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes the entire analog switch circuit, and V
CC is analog switch operating power supply voltage, VDD is CMO
S operating power supply voltage, GND is ground, I is signal input terminal, O
Is a signal output terminal, and S is a control signal input terminal. Reference numeral 11 is a second NMOS forming a transfer gate, one end of which is a signal input terminal I and the other is a signal output terminal O.
Connected to. A second resistor 12, a second NPN transistor (hereinafter referred to as NPN) 13, a current source 14,
The second diode 15, the first diode 16, the first NPN 17, the first resistor 18, the first NMOS 19
And constitute a voltage conversion circuit 20, and this circuit 20 is
CMOS level zero V input to the gate of OS19
And the CMOS operating power supply voltage VDD to the analog switch operating power supply voltage VCC and the base of the NPN17.
The voltage is converted into the sum of the voltage between the emitter and the voltage across the resistor 18, and this voltage is transmitted to the gate of the NMOS 11.

On the other hand, the NMOS 21, the NMOS 22, and the resistor 23 constitute a substrate potential switching circuit 24 for switching the substrate potential of the NMOS 11, and the circuit 24 inputs an output signal of a logic circuit 38 composed of CMOS described later, When the substrate potential of the NMOS 11 is conductive, the NMOS 1
The source potential is set to 1 and the switching is performed so that it becomes equal to the ground potential at the time of interruption.

The resistors 25, 26, NPN 27,
The current source 28 constitutes a bias circuit 29 for applying a DC potential to the source of the NMOS 11, and a bias voltage whose output impedance is kept low can be obtained from the bias voltage output terminal B. The bias voltage output terminal B is connected to the + input terminal of the amplifier 31 via the resistor 30, and
The DC voltage of the source of the NMOS 11 is applied from the output terminal of the. Reference numerals 32 and 33 are resistors that determine the gain of the amplifier 31. A is an input terminal of the amplifier 31.

Further, PMs that respectively constitute inverters
OS 34 and NMOS 35, and PMOS 36 and N
A CMOS logic circuit 38 is configured with the MOS 37.
39 is a voltage source connected to the voltage conversion circuit 20, 40 is C
A voltage source connected to the MOS logic circuit 38.

The operation of the analog switch circuit of this embodiment having the above-described structure will be described below. First, the operation when the analog switch is on will be described. When a voltage equal to or lower than the threshold voltage of the inverter composed of the PMOS 34 and the NMOS 35 is input to the control input signal terminal S, the output of this inverter becomes the potential of the operating power supply voltage VDD of the CMOS logic circuit 38. Then, the NMOS 19 of the voltage conversion circuit 20 becomes conductive, and all the current supplied by the current source 14 flows to the ground potential GND, so that NPN1
The base potential of the current mirror circuit composed of 7 and NPN 13 becomes almost zero V, and the collector current of NPN 13 is cut off. Therefore, the collector voltage of the NPN 13 does not cause a voltage drop due to the resistor 12,
It becomes the analog switch operating power supply voltage VCC. Therefore, the gate voltage of the NMOS 11 becomes the analog switch operating power supply voltage VCC, and the source potential V _{S of the} NMOS 11 from the bias circuit 29 is V _S = {R ₂₆ / (R ₂₅ + R ₂₆ )} · VCC-V _BE27 Therefore, the gate-source voltage V _{GS of} NMOS 11
Is V _GS = VCC-[{R ₂₆ / (R ₂₅ + R ₂₆ )} · VCC-
V _BE27] However, R _25: the resistance value of the resistor 25, R _26: the resistance value of the resistor 26, V _BE27: the base-emitter voltage of NPN27. Further, at this time, since the potential of the analog switch operating power supply voltage VCC is applied to the gate of the NMOS 21, the source and drain of the NMOS 21 become conductive and the NMO
The substrate potential of S11 is made equal to the potential of the signal input terminal I.

Therefore, the operating power supply voltage VDD of the CMOS logic circuit 38 is 3V, the analog switch operating power supply voltage VCC is 5V, the withstand voltage between the terminals of the MOS transistors is 3.85V, the resistance 25 is 64 kΩ, and the resistance 26 is 36.
kΩ, NPN27 base-emitter voltage 0.7
If V and the amplifier 31 are ideal amplifiers, the gate-source voltage of the NMOS 11 is 2.5 V, the drain-gate voltage is -2.5 V, and the voltage between the terminals of the MOS transistor incorporated in this circuit is CMOS. Logic circuit 3
Even if a voltage of 3 V or more is not applied inside 8 and a signal having a DC voltage is input, the ratio between the resistance 25 and the resistance 26 of the bias circuit 29 is set so that the gate-source voltage of the NMOS 11 is within the withstand voltage. By setting the voltage to be suppressed, even if the analog switch operating power supply voltage VCC exceeding the withstand voltage is used, the NMOS 11 can be made conductive while keeping the voltage between the terminals of the MOS transistor below the withstand voltage.

Next, the operation when the analog switch circuit is cut off will be described. The control signal input terminal S has a PMOS 34
When a signal having a voltage equal to or higher than the threshold voltage of the inverter configured by the NMOS and the NMOS 35 is input, the output of this inverter becomes the GND potential.
9 is cut off, the current mirror circuit composed of NPN 17 and NPN 13 operates, and NPN 13 instantaneously flows a collector current that is a mirror ratio of NPN 17. But N
Collector voltage of PN13 is by cathodic terminal of the diode 15, because it is limited so as not corresponding to a voltage below the base-emitter voltage across the NPN17 resistor 18, the collector current I _C13 of NPN13 is stationary _Where I _C13 = (VCC-V _R18 -V _BE17 ) / R ₁₂ where V _{R18 is} the voltage across resistor 18 and V _{BE17 is the} NPN.
17, the base-emitter voltage, R ₁₂ : the resistance value of the resistor 12. At this time, the NMOS 21 is cut off and the NM
The OS 22 is turned on because the output of the inverter composed of the PMOS 36 and the NMOS 37 has the potential of the operating power supply voltage VDD of the CMOS logic circuit 38. Then, the substrate potential of the NMOS 11 is connected to the GND potential via the resistor 23.

Therefore, the current value of the current source 14 is 50 μA, the resistance 18 is 1 kΩ, the base-emitter voltage of the NPN 17 is 0.7 V, and the diode 15 is set with the same setting as the constant of the bias circuit 29 when the analog switch is conducting. If the voltages across the diode 16 are equal, the NMOS1
1 has a gate voltage of 0.75V, and NMOS 11 has a gate-source voltage of -1.75V.
1 becomes lower than the threshold voltage for conduction, so NMOS1
1 is cut off.

As described above, according to this embodiment, the CMO
When the first operating power supply voltage VDD, which is the power supply for the logic circuit 38 composed of S, is set below the withstand voltage of the MOS transistor and the output of the logic circuit 38 becomes above the threshold value of the first NMOS 19, the current source 14 First NPN
All the current supplied to 17 is passed to the ground potential through the first NMOS 19. Thereby, the second NPN 13
Since the base voltage of the second NPN 13 becomes almost equal to the ground potential, the collector current of the second NPN 13 is cut off, and the second resistor 12
No voltage drop occurs, and the gate potential of the second NMOS 11 becomes equal to the second operating power supply voltage VCC. The potential of the source of the second NMOS 11 is given a voltage proportional to the second operating power supply voltage VCC by the bias circuit 29, so that the gate of the second NMOS 11 can operate even when it is conductive.
Bias circuit 29 is applied to the voltage between the source and the drain-gate.
By adjusting the voltage of 1, the voltage can be suppressed within the range of the breakdown voltage, and the switching speed equivalent to that of the conventional analog switch circuit can be obtained.

The first resistor 18 is not provided, and the first N
The mirror ratio of the current mirror circuit composed of PN17 and the second NPN13 is multiplied by a real number, preferably 1: 1 to 1:
Set to about 10, or connect a resistor whose one end is grounded to the emitter of the second NPN 13,
Even if the mirror ratio of the current mirror circuit composed of 7 and the second NPN 13 is set to a real multiple, preferably about 1: 1 to 1:10, the same effect can be obtained.

[0019]

As is apparent from the above embodiments, the present invention provides a voltage conversion circuit for converting an output signal of a CMOS logic circuit into an analog switch operation power supply voltage separated from a CMOS logic operation power supply voltage, and this voltage. A bias circuit that applies the converted control signal to the gate of an N-channel MOS transistor that forms a transfer gate when the analog switch is on, and applies a DC potential to the source of the N-channel MOS transistor in proportion to the analog switch operating power supply voltage. Since it is provided, the voltage between the terminals of the MOS transistor in the analog switch circuit can be suppressed to be lower than the withstand voltage, the on-resistance of the NMOS transistor forming the transfer gate can be sufficiently reduced, and the switching speed is high. Analog switch times It can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an analog switch circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional analog switch circuit.

[Explanation of symbols]

VCC Analog switch operating power supply voltage (second operating power supply voltage) VDD CMOS logic operating power supply voltage (first operating power supply voltage) GND Ground S Control signal input terminal I Signal input terminal O Signal output terminal A Amplifier input terminal B Bias voltage Output terminal 10 Analog switch circuit 11 Second N-channel MOS transistor 12 Second resistor 13 Second NPN type transistor 14 Current source 15 Second diode 16 First diode 17 First NPN type transistor 18 First Resistor 19 First N-channel MOS transistor 20 Voltage conversion circuit 21, 22 N-channel MOS transistor 23 Resistor 24 Substrate potential switching circuit 25, 26 Resistor 27 NPN type transistor 28 Current source 29 Bias circuit 30, 32, 33 Resistor 31 Amplifier 34 36 P-channel MOS transistor 35, 37 N-channel MOS transistor 38 CMOS logic circuits 39 and 40 a voltage source

Claims (4)

[Claims] 1. A CM for an output signal of a CMOS logic circuit
A voltage conversion circuit for converting into an analog switch operating power supply voltage separated from the OS logic operating power supply voltage, and applying this voltage converted control signal to the gate of an N-channel MOS transistor forming a transfer gate when the analog switch is conducting. An analog switch circuit that provides a DC potential of the source of the N-channel MOS transistor in proportion to the analog switch operating power supply voltage. 2. A second operating power supply voltage VDD which is a power supply for a logic circuit composed of CMOS and which is separated from the first operating power supply voltage VDD.
And a current source connected to the operating power supply voltage VCC, and an output of the current source are connected to a collector through a first diode, and a first resistor is connected to an emitter of a primary side of a current mirror circuit. Forming a secondary side of the current mirror circuit with a first NPN transistor, and a collector connected to the second operating power supply voltage VCC via a second resistor.
A second NPN transistor having an emitter connected to the ground, an anode connected to the anode of the first diode, and a cathode connected to the collector of the second NPN transistor, The first N having the drain connected to the cathode of the first diode and the source grounded
A channel MOS transistor, a logic circuit composed of CMOS for controlling the gate voltage of the first N-channel MOS transistor, a cathode of the second diode, a collector of the second NPN type transistor, and a second resistor. A second N channel M having one end connected to the gate, one end connected to the input terminal, and the other end connected to the output terminal
An OS transistor, a bias circuit for applying a DC potential proportional to the second operating power supply voltage VCC to the source of the second N-channel MOS transistor, and a substrate potential of the second N-channel MOS transistor for the second N-channel An analog switch circuit comprising a source of a MOS transistor and a substrate potential switching circuit for switching to a ground potential. 3. A mirror ratio of a current mirror circuit which does not have a first resistor and is composed of a first NPN type transistor and a second NPN type transistor is multiplied by a real number, preferably 1: 1 to 1:10. The analog switch circuit according to claim 2, wherein the analog switch circuit is set to a certain degree. 4. A mirror ratio of a current mirror circuit comprising a first NPN transistor and a second NPN transistor is multiplied by a real number by connecting a resistor whose one end is grounded to the emitter of the second NPN transistor. , Preferably 1:
The analog switch circuit according to claim 2, wherein the analog switch circuit is set to about 1 to 1:10.