JPH0237833A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a logic circuit by enlarging influence on the output terminal of the operation of two P-channel MOS transistors and two N-channel MOS transistors connected in series between two power sources. CONSTITUTION:Two P-channel MOS transistors 3 and 4 and two N-channel MOS transistors 5 and 6 are connected in series between the two power sources, and the gate and the drain of the transistors 3 and 6 connected on the sides of the power sources are connected. The output of a gate circuit to receive an input signal is inputted to the gate of the transistors 4 and 5, the output of the gate circuit to receive the input signal is connected to the input of an inverter circuit to which the P-channel MOS transistor 7 and the N-channel MOS transistor 8 are connected in series, and the output of the inverter and the junction of the transistors 4 and 5 are connected to an output terminal 9. Thus, an undershoot and an overshoot are suppressed and the malfunction of the logic circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to complementary MO8 integrated circuits, and more particularly to output circuits.

[Conventional technology]

An equivalent circuit diagram of a conventional output circuit is shown in FIG.

In the conventional output circuit, an input signal applied to an input terminal 1 is received by an inverter 14, and the inverter 14 drives a CMOS inverter in which a P-channel MO8) and an N-channel MOS transistor 8 are connected in series, and the output of this CMOS inverter is The configuration was such that the output terminal 9 was connected to the .

[Problem to be solved by the invention]

In the conventional output circuit described above, the channel widths of the P-channel MO 8) and the N-channel MOS transistor 8 constituting the output buffer are set sufficiently large so as to satisfy the required current drive capability. At this time,
The output ° signal rises or falls rapidly. The drawback is that a large current flows at the beginning of the output change, causing undershoots and overshoots in the output waveform, causing malfunctions in subsequent logic circuits.

[Means to solve the problem]

According to the present invention, the first. second two P
channel MOS transistor and the first. A gate circuit in which two second N-channel MOS transistors are connected in series, the first P-channel MOS transistor connected to the power supply side and the second N-channel MOS transistor have their gates and drains connected, and receive an input signal. The output of the remaining second
0P channel MOS transistor, first N channel M
The input signal is input to the gate of the OS transistor and is the output of the gate circuit that receives the input signal. An output circuit is obtained in which the output of this inverter and the connection point between the 20th P-channel MOS transistor and the first N-channel MOS transistor are connected to the output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention.

In an example where an inverter is used as a gate circuit that receives an input signal, 1 is an input terminal that receives an input signal, 2 is an inverter that receives an input signal, and a first P channel M is connected between the two power supplies.
OS transistor 3, second P-channel MOS transistor 4, first N-channel MOS transistor 5, second
ON channel MO8) transistors are connected in series, the first P channel MOS transistor 3 and the second ON channel MO3) transistor 6 connect the gate and drain, and the 20th P channel MOS transistor 4 and the first N channel MOS The output of inverter 2 is connected to the gate of transistor 5. In addition, the output of the inverter 2 is connected to the input of an inverter configured by connecting a third P-channel MOS transistor 3) and an N-channel MOS transistor 8 in series, and the output of this inverter and the second P-channel MOS transistor 8 are connected to each other.
A connection point between OS transistor 4 and first N-channel MOS transistor 5 is connected, and an output terminal 9 is further connected to the connection point.

Here, P channel MOS transistors 3 and 4 and N channel MOS transistors 5 and 6 are set to a gm that satisfies the required current drive capability, and P channel MOS transistor 3 and
) Langistav, N-channel MOS transistor 80g
The operation will be described when m is set to be, for example, 0.4 times that value, and inverter 2 is also set to gm that can drive each MOS transistor 3, 4, 5, 6, and 7.8.

First, considering the case where the input signal changes from low level to high level, the output of inverter 2 changes from high level to low level, and the second P-channel MOS transistor 4, third P-channel MOS transistor 8) turns on rapidly and the first ON channel MOS transistor 5
, the third N-channel MOS transistor 8 is suddenly turned off. At this time, if we consider the potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 by separating the potential at the connection point between the third P-channel MOS transistor 8) and the N-channel MOS transistor 8, the potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 can be considered as Since the gate and drain of the P-channel MOS transistor 3 are connected, the source potential of the second P-channel MOS transistor is a potential that is the difference between the power supply (+) and the threshold potential of the first P-channel MOS transistor 3. , therefore the second P-channel MOS
The potential at the connection point between the transistor 4 and the first N-channel MOS transistor 5 is from the power supply (+) to the first P-channel MOS transistor 5.
The threshold potential of the OS transistor 3 becomes a different potential. However, this point depends on the third P channel M
O8) Ranjistaf and N-channel MOS transistor 8
Since the output terminal 9 is connected to the connection point of the output terminal 9, the potential of the output terminal 9 rises to the potential of the power supply (+).

Conversely, when the input signal changes from high level to low level, the output of inverter 2 changes from low level to high level, and the second P-channel MOS transistor 4 and third P-channel MOS transistor 7 are quickly turned off. death,
The first ON channel MOS transistor 5 and the third N channel MOS transistor 8 are turned on rapidly. Similar to when the input signal changes from low level to high level,
The potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 is the power supply (-).
The threshold potential of the second ON channel MO8) reaches the final potential, but since the connection point between the third P-channel MO8) and the third N-channel MOS transistor 8 is connected, the output terminal 9
The potential of decreases to the potential of the power supply (-). In either case, in response to a change in the input signal, the gm of the third P-channel MOS transistor 7 and the N-channel MOS transistor 8 is changed to the first. 20th P channel MOS transistor 3.4, N
Since the potential of the output terminal 9 is set to be 0.4 times that of the channel MOS transistors 5 and 6, the change in the potential of the output terminal 9 is the same as that of the first. Second
P-channel MOS transistors 3, 4 . N channel M
The operation of OS transistor 5.6 is the third P-channel MO.
3) Langistaffe is more dominant than the operation of the N-channel MOS transistor 8, and the influence of the potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 is large. Therefore, undershoot and overshoot of the output terminal can be suppressed.

FIG. 2 is an equivalent circuit diagram of another embodiment of the present invention. 1st
Similar to the embodiment in the figure, a P-channel MOS is connected between the two power supplies.
Transistors 3, 4. N-channel MOS transistor 5
, 6 are connected in series, and the P-channel MOS transistor 3
, N-channel MOS transistor 6 has its drain and gate connected, and the connection point between P-channel MOS transistor 4 and N-channel MOS transistor 5 is constructed by connecting P-channel MOS transistor 8) and N-channel MOS transistor 8 in series. Connect to the inverter output and also connect to the output terminal.

The gates of P-channel MOS transistors 4 and 7 are connected to the output of a NAND circuit 12 which receives a signal obtained by inverting the input signal and control signal 10 via an inverter 11, and the gate of N-channel MOS transistor 5.8 is connected to the input signal. and the output of the NOR circuit 13 into which the control signal 10 is input. When the control signal 10 is at a low level, the operation is similar to that in the first embodiment. Conversely, when the control signal lO is at high level, N
The output of the AND circuit 12 is at a high level, and the output of the NOR circuit 13 is at a low level, so that the P channel MOS transistors 4, 7 and the N channel MOS transistors 5, 8 are all turned off, allowing the output terminal 9 to be in a high impedance state.

〔Effect of the invention〕

As explained above, the first power source is connected between the two power supplies. The second two P-channel MOS transistors and the first and second two N-channel MOS transistors are connected in series, and the 10th P-channel MOS transistor and the second ON-channel MOS transistor connected to the power supply side have gates and drains, respectively. The output of the gate circuit that receives the input signal is input to the gates of the remaining second P-channel MOS transistor and the first N-channel MOS transistor, and the output of the gate circuit that receives the input signal is input to the gate of the remaining second P-channel MOS transistor and the first N-channel MOS transistor.
Connect to the input of an inverter circuit in which an S transistor and an N-channel MOS transistor are connected in series, and connect the output of this inverter and the connection point between the second P-channel MOS transistor and the first ON-channel MOS transistor to the output terminal. The effect of the present invention will be explained by comparing the conventional technique and the case of Example 1.

In Figure 1, 1. Second P-channel MOS transistors 3, 4 . N channel MOS transistor 5.60g
m, the 30th P channel MOS transistor 7, N
The gm of channel MOS transistor 8 is 0.5 to 0.1.
As a result of running a circuit simulator 3 (SPICE) after changing the voltage up to 100%, the degree of reduction in undershoot is shown in Fig. 4, and the simulation waveform is shown in Fig. 5. As will be seen, when the gm ratio is set to 0.5 or less, both overshoot and undershoot can be suppressed to less than half compared to conventional circuits.

In the present invention, the first and second
The operation of the P-channel MOS transistor and N-channel MoS transistor is made to operate more dominantly than the operation of the third P-channel MOS transistor and N-channel MOS transistor, which constitute the conventional output buffer, with respect to the output terminal. By increasing the influence of , undershoot and overshoot can be suppressed, and subsequent malfunctions of the logic circuit can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, Fig. 3 is a circuit diagram showing a conventional output circuit, and Fig. 4 is a circuit diagram showing a conventional output circuit. FIG. 1 is a graph showing the under-short ratio as a result of the circuit simulation according to the embodiment of the present invention shown in FIG. 1, and FIG. 5 is a simulation waveform diagram of the circuit simulation according to the embodiment of the present invention shown in FIG. l...Input terminal, 2...Inverter,
3...first P-channel MOS transistor,
4...Second P-channel MOS transistor,
5...First N-channel MOS transistor,
6... Second ON channel MOS transistor,
7...Third P-channel MOS transistor,
8...3rd ON channel MOS transistor,
9... Output terminal, 10... Control signal,
11...Inverter, 12...NAN
D circuit, 13...NOR circuit. Agent Patent Attorney Shinwa Uchihara 3rd Time Book

Claims (1)

[Claims] A first P-channel MOS transistor and a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor are connected in series, and the first P-channel MOS transistor and the second P-channel MOS transistor are connected in series. The gates and drains of the N-channel MOS transistors are connected to each other, and the output of a gate circuit that receives an input signal is input to the gates of the second P-channel transistor and the first N-channel MOS transistor, and the output of this gate circuit is input to the gates of the second P-channel transistor and the first N-channel MOS transistor. is further connected to the input of an inverter configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in series, and the second P-channel MOS transistor and the first N-channel MOS
An output circuit characterized in that a connection point of a transistor and an output of the inverter are connected, and an output terminal is connected to the connection point.