JPH02112317A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPH02112317A
JPH02112317A JP26538788A JP26538788A JPH02112317A JP H02112317 A JPH02112317 A JP H02112317A JP 26538788 A JP26538788 A JP 26538788A JP 26538788 A JP26538788 A JP 26538788A JP H02112317 A JPH02112317 A JP H02112317A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
output
tr
undershooting
overshooting
malfunction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26538788A
Inventor
Yasuko Aoki
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To suppress undershooting and overshooting and to prevent the malfunction of a logical circuit thereafter by making more dominant the operation of a first transistor(TR) than the operation of a second TR, and making larger the effect on an output terminal.
CONSTITUTION: An inverted input signal to an inverter 3 composed as an output buffer is inputted to the gate between an N-channel MOS TR 4 and a P-channel MOS TR, which are reversely connected in series between two power sources, and the output of its contact point and the inverter 3 is connected to an output terminal 8. Thus, a sharp leading edge and trailing edge of the output signal are prevented, and the undershooting and overshooting of the output waveform can be prevented from being the factor of the malfunction for the logical circuit thereafter.
COPYRIGHT: (C)1990,JPO&Japio
JP26538788A 1988-10-20 1988-10-20 Output circuit Pending JPH02112317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26538788A JPH02112317A (en) 1988-10-20 1988-10-20 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26538788A JPH02112317A (en) 1988-10-20 1988-10-20 Output circuit

Publications (1)

Publication Number Publication Date
JPH02112317A true true JPH02112317A (en) 1990-04-25

Family

ID=17416470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26538788A Pending JPH02112317A (en) 1988-10-20 1988-10-20 Output circuit

Country Status (1)

Country Link
JP (1) JPH02112317A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192716A (en) * 1990-11-26 1992-07-10 Mitsubishi Electric Corp Mos transistor output circuit
JPH057142A (en) * 1991-01-28 1993-01-14 Mitsubishi Electric Corp Output buffer circuit
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US5870347A (en) * 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5898638A (en) * 1997-03-11 1999-04-27 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US5917758A (en) * 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US6014759A (en) * 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6044429A (en) * 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US8892974B2 (en) 2003-06-12 2014-11-18 Round Rock Research, Llc Dynamic synchronization of data capture on an optical or other high speed communications link

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192716A (en) * 1990-11-26 1992-07-10 Mitsubishi Electric Corp Mos transistor output circuit
JPH057142A (en) * 1991-01-28 1993-01-14 Mitsubishi Electric Corp Output buffer circuit
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5910920A (en) * 1996-10-28 1999-06-08 Micron Technology, Inc. High speed input buffer
US6437600B1 (en) 1996-11-04 2002-08-20 Micron Technology, Inc. Adjustable output driver circuit
US6326810B1 (en) 1996-11-04 2001-12-04 Micron Technology, Inc. Adjustable output driver circuit
US5917758A (en) * 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US6084434A (en) * 1996-11-26 2000-07-04 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6069504A (en) * 1997-01-06 2000-05-30 Micron Technnology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US6256255B1 (en) 1997-03-11 2001-07-03 Micron Technology, Inc. Multi-bank memory input/output line selection
US5870347A (en) * 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US5898638A (en) * 1997-03-11 1999-04-27 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US6122217A (en) * 1997-03-11 2000-09-19 Micron Technology, Inc. Multi-bank memory input/output line selection
US6130855A (en) * 1997-03-11 2000-10-10 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US6519719B1 (en) 1997-06-13 2003-02-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6014759A (en) * 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6272608B1 (en) 1997-07-10 2001-08-07 Micron Technology, Inc. Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals
US6415340B1 (en) 1997-07-10 2002-07-02 Micron Technology, Inc. Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
US6044429A (en) * 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6091646A (en) * 1998-02-17 2000-07-18 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US8892974B2 (en) 2003-06-12 2014-11-18 Round Rock Research, Llc Dynamic synchronization of data capture on an optical or other high speed communications link

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