JPH03248620A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress overshoot and undershoot by limiting a gate-source voltage fed to a 1st one-condition MOS transistor(TR) and a 2nd opposite-conduction MOS TR so as to limit a current flowing to an output terminal. CONSTITUTION:The potential at a point A is applied to the gate of a 2nd N- channel MOS TR 8 in the output circuit, then a power voltage VPP is inputted till the power voltage VPP reaches 2.VTN or over and the TR 8 is completely turned on. Moreover, when the voltage VPP reaches 2.VTN or over, a limited voltage RN.VPP/(R'+RN) is inputted as a gate potential and the TR 8 is turned on. Since the potential at a gate point B is inputted to a 1st P-channel MOS TR 5 similarly, 0V is inputted till the voltage VPP reaches 2.VTR or over and the TR 5 is turned on. When the voltage VPP reaches 2.VTR or over, a limited voltage R''.VPP/(R''+RP) is inputted as a gate potential and the TR 5 is turned on. Thus, the TRs 5, 8 are turned on regardless of the power voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit constructed from complementary MO3 (CMoS) integrated circuits.

[Conventional technology]

An equivalent circuit diagram of a conventional output circuit of this type is shown in FIG.

This output circuit consists of a P-channel MOS transistor 100
and an N-channel MOS transistor 200 are connected in series to form a CMO3 connected between two power supplies, and the input signal 1 is inputted to the gate of each transistor 100, 200 through an inverter 300, and the source of each transistor , the connection point of the drain is connected to the output terminal 400.

[Problem to be solved by the invention]

In the conventional output circuit described above, in order to satisfy the required current drive capability, it is necessary to
The channel width of S transistor 200 is set large. However, in such a configuration, the output signal rises and falls rapidly, and a large current flows at the beginning of the output change, and this current flows into the inductance parasitic to the output terminal, causing an undershoot in the output waveform. Overshoot is likely to occur. In particular, the higher the power supply voltage is, the larger the current value becomes, so these undershoots and overshoots become larger as the power supply voltage becomes higher, causing a problem in that they cause malfunctions in subsequent logic circuits.

An object of the present invention is to provide an output circuit that suppresses such undershoot and overshoot.

[Means to solve the problem]

The output circuit of the present invention includes first and second MOS transistors of one conductivity type (for example, P channel) and first and second MOS transistors of opposite conductivity type (for example, N channel) connected in series. The second one-conductivity type MOS transistor and the first opposite-conductivity type MOS transistor are connected between the first and second power supplies, and a gate circuit for outputting an input signal is connected to each gate, and the gate circuit of these MOS transistors is Connect output terminals to the interconnection points. Further, the output of the first limited voltage output circuit is input to the gate of the second reverse conductivity type MOS transistor, and the output of the second limited voltage output circuit is input to the gate of the first single conductivity type MOS transistor. are doing. Each of the first and second limited voltage output circuits is configured to output a voltage that limits the voltage between the power supplies and keeps each of the MOS transistors on at all times.

[Effect]

According to the present invention, by limiting the gate-source voltages applied to the first one-conductivity type MOS transistor and the second opposite-conductivity type MOS transistor, the current flowing to the output terminal is limited, and the parasitic This suppresses overshoot and undershoot by limiting the current flowing into the inductance.

(Example〕 Next, the present invention will be explained with reference to the drawings.

(First Embodiment) FIG. 1 is an equivalent circuit diagram of a first embodiment of the present invention. In the figure, 1 is an input signal, 2 is a gate circuit that receives the input signal, 3 is a first limited voltage output circuit, and 4 is a second limited voltage output circuit. Further, the first P-channel MOS transistor 5. a second P-channel MOS transistor;
first N-channel MOS transistor OFF, and second ON
Channel MOS transistors 8 are connected in series between two positive and negative power supplies. And the second P
Channel MOS transistor and first N-channel MO
The output of the gate circuit 2 is input to each gate of the S transistor 8, and the output of the first limited voltage output circuit 3 is input to the gate of the second N channel MOS transistor 8.
The output of the second limited voltage output circuit 4 is input to the gate of the P-channel MOS transistor 5 . In addition, a second P-channel MOS transistor and a first N-channel MOS
An output terminal 9 is connected to a connection point between the source and drain of the transistor.

FIG. 2 is a circuit diagram showing an example of the output circuit of FIG. 1.

Here, an inverter 16 is used as a gate circuit that receives input signal 1. The first limited voltage output circuit 3 is a P-channel MO whose gate is connected to the power supply (-).
S transistor 10 and N connected to gate voltage (+)
A transmission gate is formed by a channel MOS transistor 11, and two N-channel MOS transistors 12 whose gates and drains are connected to this transmission gate are connected in series, and these are connected between power supplies (+) and (-). There is. A point A connecting the transmission gate and the N-channel MOS transistor 12 is connected to the gate of the second N-channel MOS transistor 8.

Similarly, the second limited voltage output circuit 4 connects the gates and drains of two P-channel MOS transistors 13, and has a transmission gate formed by a P-channel MOS transistor 14 and an N-channel MOS transistor 15. are connected in series, and these are connected between the power supply (+) and (-). And P
The point B connecting the channel MOS transistor 13 and the transmission gate is connected to the first P-channel MO
It is connected to the gate of S transistor 5.

3(a) shows the state in which the potential at point B in the first limited voltage output circuit 3 changes in accordance with changes in the power supply voltage
).

Power supplies (+) and (-) are connected by a transmission gate and two N-channel MOS transistors 12, and the transmission gate connects the gates of the P-channel MOS transistors 1° to the power supply (-) and N-channel MOS transistors 12.
The gate of channel MOS transistor 11 is connected to the power supply (+)
It is always on because it is connected to the On the other hand, since the two P-channel MOS transistors 12 have their gates and drains connected and are connected in series, N
Assuming that the threshold voltage of the channel MOS transistor is VTN, it turns on when the power supply voltage is 2×■TN or more. Therefore, the potential at point A is the power supply voltage ■DD is 2.
■ Until A, the same voltage as VDD is output, and ■. 2・
(a) In the above case, the potential RN obtained by resistance-dividing the on-resistance R' of the transmission gate and the on-resistance R8 of the two N-channel MOS transistors 12 with respect to VDD becomes Vat+/(R'+RN).

Similarly, the potential at point B in the second limited voltage output circuit 4 is also
The change is made as shown in FIG. 3(b).

That is, when the power supply voltage IID is less than 2·vtp, the transmission gate is on, but the P channel MOS transistor 13 is off, so that the power (-) is output to point B. Power supply voltage ■. When the voltage exceeds 2·VTP, the P-channel MOS transistor 13 turns on, so the transmission gate on-resistance R#,
If the on-resistance of the two P-channel MOS transistors 13 is R1, then R# ・VDD/ (R' +RP)
becomes.

According to this output circuit, since the potential at point A is input to the gate of the second N-channel MOS transistor 8, V is input until the power supply voltage DD reaches 2·VTN, and the second N-channel MOS transistor 8 is completely turned on. Also, when VDD exceeds 2・VTM, the limited voltage R,・Van/(R' +RN
) is input as the gate potential, which also turns on. Similarly, since the potential at point B is input to the gate of the first P-channel MOS transistor 5, the power supply voltage van
OV is input until becomes 2·VTP, and the first P-channel MOS transistor 5 is turned on.

Further, when VDI becomes 2·VTP or more, the limited voltage R″·■DD/(R″+R,) is input as the gate potential, and this also becomes an on state.

Therefore, regardless of the power supply voltage, the first P channel M
OS) Langimeta 5. Second N-channel MOS transistor 8 is turned on and always operates as an inverter. At this time, the current value In that can be passed through the first P-channel MOS transistor 5 is . =-βCVas
VTP)”/2, and the gate-source voltage VC
It can be seen that as S increases, In increases. Normally, when the power supply voltage increases, ■. However, in this embodiment, a constant voltage value of R#·V, ゎ/(R"+RP) is input to the gate of the first P-channel MOS transistor 5, so the gate-source voltage increases. v, 3
is Vcs= (I R' / (R' + RP))
Vo.

It doesn't take more than that ■. is limited accordingly. This is the second
The same applies to N-channel MOS transistor 8. Therefore, the first P-channel MOS transistor 5
．． By setting the gain of the second N-channel MOS transistor 8 to be more dominant than that of the second P-channel MOS transistor and the first N-channel MOS transistor, the current flowing through the inductance parasitic to the output terminal can be suppressed. This makes it possible to suppress overshoot and undershoot due to power supply voltage fluctuations, and prevent subsequent malfunctions of the logic circuit.

(Second Embodiment) FIG. 4 is an equivalent circuit diagram of a second embodiment of the present invention. Similar to the first embodiment, a P-channel MOS is connected between the two power supplies.
Transistors 5 and 6 and N-channel MOS transistors 8 and 8 are connected in series.

The first limited voltage output circuit 3A is connected to the gate of the second N-channel MOS transistor 8, and the first
A second limited voltage output circuit 4A is connected to the gate of the channel MOS transistor 5.

The first limited voltage output circuit 3A has a resistor 19 and two diodes 20 connected in series between two power supplies, and a resistor 1
A voltage is output from the connection point A between 9 and the diode 20. Similarly, the second limited voltage output circuit 4A connects two diodes 20 and a resistor 19 in series between two power supplies, and outputs a voltage from connection point B.

Here, the output terminal 9 is connected to the connection point between the second P-channel MOS transistor and the first N-channel MOS transistor, while the gate of the second P-channel MOS transistor is connected to the input signal 1 and the control signal. 21 is connected to the output of the NAND circuit 17 which inputs the inverted signal via the inverter 16, and the gate of the first N-channel MOS transistor is connected to the output of the NOR circuit 18 to which the input signal 1 and the control signal 21 are input manually. is connected to.

Therefore, in this circuit, when the control signal 21 is at a low level, the operation is similar to that in the first embodiment.

That is, a constant voltage value dropped by diode 20 is applied to each second N-channel MOS transistor 8. By inputting the signal to the first P-channel MOS transistor 5, the same operation as in the first embodiment is performed.

On the other hand, when the control signal 21 is at a high level, the NAND circuit 1
The output of the NOR circuit 18 is at a high level, the output of the NOR circuit 18 is at a low level, the second P-channel MOS transistor 6 and the first N-channel MOS transistor 7 are all turned off, and the output terminal 9 can be brought into a high impedance state.

〔Effect of the invention〕

As explained above, the present invention connects the first and second one-conductivity type MOS transistors and the first and second opposite-conductivity type MOS transistors in series between the power supplies, and connects the second one-conductivity type MOS transistor
Configuring an inverter with an S transistor and a first reverse conductivity type MOS transistor, and then limiting gate-source voltages applied to the first single conductivity type MOS transistor and the second reverse conductivity type MOS transistor, respectively. This has the effect of limiting the current flowing to the output terminal, suppressing overshoot and undershoot that occurs due to current flowing into the parasitic inductance of the output terminal, and preventing subsequent malfunctions of the logic circuit.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of the first embodiment of the present invention, Fig. 2 is a specific circuit diagram of an example of Fig. 1, and Figs. 3 (a) and (b).
4 is an equivalent circuit diagram of the second embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of an example of a conventional output circuit. 1... Input signal, 2... Gate circuit, 3... First
limited voltage output circuit, 4... second limited voltage output circuit, 5... first P channel MOS transistor, 6...
...Second P-channel MOS transistor, 7...First N-channel MOS transistor, 8...Second N-channel MOS transistor
Channel MOS transistor, 9... Output terminal, 10
...P channel MOS transistor, 11...N channel MOS transistor, 12...N channel MO
S transistor, 13...P channel MOS transistor, 14...P channel MOS transistor, 15
... N channel MOS transistor, 16 ... Inverter, 17 ... NAND circuit, 18 ... NOR circuit,
19...Resistor, 20...Diode, 21...Control signal, 100...P channel MOS transistor,
200...N channel MOS transistor, 300...
...Inverter, 400...Output terminal. Figure 2 Figure 3 (a) (b) 2・VTII-V 帥

Claims (1)

[Claims] 1. First and second MOS transistors of one conductivity type and first and second MOS transistors of opposite conductivity type are connected in series and connected between the first and second power supplies, The second MOS transistor of one conductivity type and the first MOS transistor of opposite conductivity type have respective gates connected to a gate circuit for outputting an input signal, and an output terminal connected to an interconnection point of these MOS transistors. , the second reverse conductivity type MOS
The output of the first limited voltage output circuit is input to the gate of the transistor, and the output of the second limited voltage output circuit is input to the gate of the first one-conductivity type MOS transistor. Each of the limited voltage output circuits outputs a voltage that limits the voltage between the power supplies and turns on each of the second reverse conductivity type MOS transistor and the first one conductivity type MOS transistor at all times. An output circuit characterized by comprising: 2. first and second P-channel MOS transistors;
The first and second N-channel MOS transistors are connected in series and connected between positive and negative power supplies, and the second P-channel MOS transistor and the first N-channel MOS transistor have input signals applied to their respective gates. A gate circuit that outputs the voltage is connected, and an output terminal is connected to the interconnection point of these MOS transistors, and the output of the first limited voltage output circuit is input to the gate of the second N-channel MOS transistor, 2. The output circuit according to claim 1, wherein the output of the second limited voltage output circuit is input to the gate of the first P-channel MOS transistor.