JPH04321321A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a next stage by suppressing the overshoot/undershoot of an output circuit. CONSTITUTION:An output inverter consists of transistors(TRs) 3, 4, 5, 6 and the output potential of the output inverter does not reach a power supply potential less than the threshold level of the TR3 or 6. An input signal is also fed to a delay circuit 2 and a 2nd inverter composed of TRs 7, 8 is driven by a delay input signal applied from the delay circuit 2. The output of the 1st inverter and the output of the 2nd inverter are connected in common and since an output waveform is changed in two stages, then the overshoot and the undershoot of the output gas suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to complementary MOS integrated circuits, and more particularly to output circuits.

0002

2. Description of the Related Art A conventional output circuit is shown in FIG. The conventional output circuit has a configuration in which an input signal 30 is input to a CMOS inverter 33 in which a P-channel MOS transistor 31 and an N-channel MOS transistor 32 are connected in series, and an output terminal 34 is connected to the output of this inverter 33. . P-channel MOS transistor 31 and N-channel MOS transistor 32 have their respective channel widths set sufficiently large to satisfy the required high-level output current and low-level output current.

0003

[Problems to be Solved by the Invention] The conventional output circuit described above has a CM
Since the channel widths of the P-channel MOS transistor 31 and the N-channel MOS transistor 32 constituting the OS inverter 33 are set to be sufficiently large, the output signal rises and falls rapidly. As a result, a large current flows when the output signal starts to change, causing undershoots and overshoots in the waveform of the output signal, causing malfunctions in logic circuits to which such output signals are supplied.

0004

SUMMARY OF THE INVENTION The present invention provides an output circuit having an output inverter connected between a first power source and a second power source, wherein the output inverter includes a P-channel type first load transistor; It is constructed by connecting a P-channel type first switching transistor, an N-channel type second switching transistor, and an N-channel type second load transistor in series, and the input signal is the first switching transistor, the second N-channel type switching transistor, and the second N-channel type load transistor.
The delay circuit, which is supplied to the gate of the second switching transistor and is supplied with the input signal, transmits the delayed input signal to a P-channel type third transistor connected in series between the first power supply and the second power supply.
The common drain of the first and second switching transistors is supplied to the gates of the switching transistor and the N-channel type fourth switching transistor, and the common drain of the first and second switching transistors is supplied to the third switching transistor.
, and function as an output node.

[0005]

When the input signal changes, the output inverter temporarily shifts the output node to a voltage level that is lower than the power supply level by the thresholds of the first and second load transistors. A switching transistor transitions the output node to the final voltage level.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention. 1 is an input signal, and this input signal 1 becomes an in-phase delayed input signal in a delay circuit 2. 2 power supply VCs
The first P-channel MOS transistor 3 is connected between C and GND.
, a second P-channel MOS transistor 4, a first N-channel MOS transistor 5, and a second N-channel MOS transistor 6 are connected in series.
The P-channel MOS transistor 3 and the second N-channel MOS transistor 6 have their gates and drains connected, respectively. Input signal 1 is input to the gates of second P-channel MOS transistor 4 and first N-channel MOS transistor 5.

[0007] Furthermore, there is a third
P-channel MOS transistor 7 and N-channel MOS
Inverter 1 configured by connecting transistors 8 in series
5 are connected, and these MOS transistors 7, 8
The output of the delay circuit 2, that is, the delayed input signal, is supplied to the gate of the delay circuit 2. The output of this inverter 15 is connected to the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5, and the output terminal 9 is further connected to the connection point.

Here, the delay circuit 2 sets a delay value so that the delayed input signal changes immediately after a change in the input signal 1 operates the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5. Set.

First, consider the case where the input signal 1 changes from high level to low level, the second P channel transistor 4 is turned on and the first N channel MOS transistor 5 is turned off.

At this time, the potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 is changed to the potential at the connection point between the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5.
When considered separately from the connection point of the channel MOS transistor 8, since the gate and drain of the first P-channel MOS transistor 3 are connected, the source potential of the second P-channel MOS transistor 4 is the same as the power supply VCC. The potential is lowered by the threshold potential of the P-channel transistor 3 of No. 1. Therefore, the second P-channel MOS transistor 4 and the first N-channel MOS
The potential at the connection point of transistor 5 is a potential lower than the power supply VCC by the threshold potential of first P-channel MOS transistor 3.

Immediately after this, the delay circuit 2 changes the delayed input signal from a high level to a low level, and the third P-channel MOS transistor 7 is turned on, so that the output terminal 9 rises to the potential of the power supply VCC.

The same applies when the input signal 1 changes from a low level to a high level, and the output terminal 9 changes from a high level to a low level, but a detailed explanation will be omitted for the sake of brevity. In other words, it always operates as an inverter. Next, the first
The advantages of the embodiment will be explained. The channel widths of P-channel MOS transistors 3 and 4 and N-channel MOS transistors 5 and 6 are set to the minimum within a range that satisfies the rise and fall times required for output terminal 9, and when input signal 1 changes. After that, P channel MOS transistor 4
, even if the N-channel MOS transistor 5 is turned on, the output terminal 9 is kept at the power supply potential VCC or GN by the P-channel MOS transistor 3 and the N-channel MOS transistor 6.
It doesn't reach D. This means that even if overshoot or undershoot occurs, the overshoot or undershoot of the potential relative to the power supply potential becomes smaller. P channel MOS transistor 7, N channel M
Since the delay value of the delay circuit 2 is set so that the OS transistor 8 operates after the second P-channel MOS transistor 4 and the first N-channel MOS transistor 5 operate, the output terminal 9 is finally connected to the power supply potential. VCC
Or reach GND.

Furthermore, P channel MOS transistors 3,
4. Even if the channel widths of the N-channel MOS transistors 5 and 6 are too small to satisfy the output current required for the output terminal 9, the delay value of the delay circuit 2 is set so that the operation is performed as described above. 3 P channel MO
By setting the channel widths of the S transistor 7 and the third N-channel MOS transistor 8, the required output current value can be finally satisfied.

FIG. 4 shows circuit simulation (SPICE
) depicts the output waveforms of the conventional output circuit and the output circuit according to the embodiment of the present invention.

As is clear from FIG. 4, in the output waveform of the embodiment, overshoot and undershoot are reduced by about 50% compared to the conventional example.

FIG. 2 is an equivalent circuit diagram of a second embodiment of the present invention. Similar to the first embodiment, P channel MOS transistors 3 and 4 and N channel M are connected between the two power supplies VCC and GND.
OS transistors 5 and 6 are connected in series, and P channel M
OS transistor 3, N channel MOS transistor 6
connect the gate and drain respectively. P channel M
OS transistor 4 and N channel MOS transistor 5
The connection point between the two terminals is connected to the output of an inverter 15 formed by connecting a P-channel MOS transistor 7 and an N-channel MOS transistor 8 in series, and is also connected to an output terminal 9.

The output of the NAND circuit 13, which receives as input a signal obtained by inverting the input signal 1 via the inverter 10 and a signal obtained by inverting the control signal 11 via the inverter 12, is applied to the delay circuit 2 and the gate of the P-channel MOS transistor 3. Enter.

Furthermore, the output of the inverter 10 and the control signal 11
The output of the NOR circuit 14 which receives as input is input to the delay circuit 15 and the gate of the N-channel MOS transistor 5.

When the control signal 11 is at a low level, the operation is similar to that of the first embodiment. When the control signal 11 is at a high level, the output of the NAND circuit 13 is at a high level, the output of the NOR circuit 14 is at a low level, the output of the delay circuit 2 is at a high level, and the output of the delay circuit 15 is at a low level. transistors 4, 7, N-channel MOS transistor 5,
8 are all turned off, and the output terminal 9 can be placed in a high impedance state. The second embodiment also has P channel M.
The OS transistor 4 or the N-channel MOS transistor 5 first changes the potential to a threshold potential lower (or higher) than the power supply potential VCC or GND, and then the P-channel MOS transistor 7 or the N-channel MOS transistor 8 finally changes the potential to the target value. Since the value is changed, there is an advantage that overshoot or undershoot does not occur.

[0020]

As described above, the present invention has the effect of suppressing overshoot and undershoot and preventing subsequent malfunction of the logic circuit.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a second embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a conventional example.

FIG. 4 is a graph simulating the output waveform of the output circuit.

[Explanation of symbols]

1 Input signal 2, 15 Delay circuit 3 First P-channel MOS transistor 4 Second
P-channel MOS transistor 5 First N-channel MOS transistor 6 Second N-channel MOS transistor 7 Third P-channel MOS transistor 8 Third N-channel MOS transistor 9 Output terminals 10, 12, 15 Inverter 13 NAND circuit 14 noah circuit

Claims (3)

[Claims] 1. An output circuit having an output inverter connected between a first power source and a second power source, wherein the output inverter includes a P-channel type first load transistor;
It is configured by connecting a P-channel type first switching transistor, an N-channel type second switching transistor, and an N-channel type second load transistor in series, and the input signal is supplied to the gates of the first and second switching transistors. , the delay circuit to which the input signal is supplied supplies the delayed input signal to a P-channel type third switching transistor connected in series between the first power source and the second power source;
An output that is supplied to a gate of a channel-type fourth switching transistor, and a common drain of the first and second switching transistors is connected to a common drain of the third and fourth switching transistors to function as an output node. circuit. Claim 2: The delay circuit is configured such that the input signals are first and second.
2. The output circuit of claim 1, wherein the delayed input signal changes when the switching transistor completes switching. 3. The input signal is supplied to a logic circuit together with a control signal, and the logic circuit supplies the input signal to the delay circuit and the first and second switching transistors when the control signal is at an active level, and when the control signal is inactive. 2. The output circuit according to claim 1, wherein when the level is reached, the logic circuit turns off the first, second, third, and fourth switching transistors to put them in a high impedance state.