JP2644368B2 - Input signal buffer circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an input signal buffer circuit.

(Prior Art) Recently, the use of semiconductor devices has increased, and an input signal buffer circuit of the semiconductor device that has a small dead band of an input switching level and responds at high speed is required.

FIG. 4 is a circuit diagram of a conventional input signal buffer circuit, and FIG.
The figure shows the relationship between the input switching level of the input signal in the input buffer circuit and the power supply voltage. FIG. 6 is a signal waveform diagram of the input buffer circuit.

In Figure 4-Figure 6, I is the input signal, O is the output signal, N21 is the node name, V _cc is the power supply voltage, V _ss is the ground voltage, Q
each P-channel MOS transistor _{p 21~Q p} 23 is, Q _n 21
To Q _n 23 are each N-channel type MOS transistor, the NOT circuit INV7, VIH is High side input switching level, VIL is
Low-side input switching level.

Next, the operation of the input buffer circuit will be described with reference to FIGS.

First, when the input signal I is at the logic voltage "L", the transistor Q _p 21, Q _p 22 is turned on, the transistor Q _n 21, Q _n 22 is turned off, the node N21 is at logic voltage "H", if the output signal O is logic voltage "L", the transistor Q _p 23 is turned on, the transistor Q _n 23 is an off the input switching level of the input signal I Hi
It has shifted to the gh side.

Next, when the input signal I becomes logical voltage "H", the transistor Q _p 21, Q _p 22 is turned off, since the transistor Q _n 21, Q _n 22 is turned on, the node N21 is in the logical voltage "L", the output signal O is the logic voltage "H", the transistor Q _p 23 is turned off, the transistor Q _n 23 is turned on, the input switching level of the input signal I is shifted to the Low side.

Thus, the transistor Q _p to which the input signal I is input is
21, Q _p 22, Q _n 21, Q _n 22 connected in parallel with transistor Q _p 2
3, since a signal having the same phase as the input signal I is input to Q _n 23, when the input signal I is at the logic voltage “L”, the input switching level is shifted to the high side, and the input signal I is changed to the logic voltage “H”. "
When, the input switching level shifts to the low side.

Therefore, for example, as shown in FIG. 6, after the input signal I transitions from the logic voltage "L" to the logic voltage "H", even if the level of the logic voltage "H" is slightly lowered due to reflection or the like, it is difficult to malfunction. Has features.

(Problems to be Solved by the Invention) However, in the conventional input signal buffer circuit, the malfunction due to reflection or the like after the transition of the input signal is small as described above, but the dead band of the input switching level as shown in FIG. Is large, the response to the transition of the input signal is slow.

In view of the foregoing, it is an object of the present invention to reduce a malfunction due to reflection or the like after a transition of an input signal and reduce a dead zone of an input switching level to speed up a response to a transition of an input signal.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a solution of the present invention is to provide an input signal buffer circuit comprising a first complementary MOS transistor to which an input signal is input. A group, a first complementary MOS transistor that receives a signal in phase with the input signal, and a second complementary MOS transistor that receives a signal in phase opposite to the input signal and delayed from the input signal. Are connected to each other in an array.

According to a second aspect of the present invention, there is provided a first complementary MOS transistor which receives a signal in phase with the input signal instead of the first complementary MOS transistor according to the first aspect. MOS transistor and a third complementary MOS inputting a signal having a phase opposite to that of the input signal and delayed from the input signal
The transistor has a second complementary MOS transistor group connected in series.

Further, a solution taken by the invention of claim (3) is that in the configuration of the input signal buffer circuit according to claim (1) or (2), the input signal buffer circuit is out of phase with the input signal and delayed from the input signal. The delay time of the first complementary type
The sum of the amount of current flowing through the P-channel MOS transistor group of the MOS transistor group and the amount of current flowing through the P-channel MOS transistor of the third complementary MOS transistor is the N-channel type of the first complementary MOS transistor group. The time when the current flowing through the MOS transistor group is less than
And the sum of the amount of current flowing through the N-channel type MOS transistor group of the first complementary type MOS transistor group and the amount of current flowing through the N-channel type MOS transistor of the third complementary type MOS transistor is the first complementary type. This configuration adds a configuration including a delay circuit that makes the time shorter than each of the times when the amount of current flowing through the P-channel MOS transistor group of the MOS transistor group becomes equal to or less than the current amount.

(Operation) According to the configuration of the invention of claims (1) and (2), the first complementary MOS transistor group to which an input signal is input is input to the first complementary MOS transistor group to which the input signal is input. Since the transistor is connected in parallel with the second complementary MOS transistor that receives a signal that is in phase and delayed from the input signal, the first and second complementary MOS transistors immediately after the transition of the input signal This prevents a malfunction due to reflection of an input signal or the like, and after a lapse of a predetermined time, the second complementary MOS transistor allows the dead band of the input switching level to be reduced to prepare for the next transition.

Further, according to the configuration of the invention of claim (3), the input signal buffer circuit of claim (1) or (2) has a phase opposite to that of the input signal input to the first complementary MOS transistor group and the input signal Since a delay circuit that makes the delay time of the signal delayed from the signal shorter than a predetermined time is provided, after a transient state in which a malfunction is likely to occur is completed and the output signal is determined, the next input signal transition is prepared. The dead zone can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an input signal buffer circuit according to an embodiment of the present invention, and FIG. 2 (A) is input switching of the input signal I after a lapse of a predetermined time from a transition of the input signal I in the input signal buffer circuit. FIG. 2B is a diagram illustrating a relationship between a level and a power supply voltage, and FIG. 2B is a diagram illustrating a relationship between an input switching level of the input signal I and a power supply voltage immediately after a transition of the input signal I in the input signal buffer circuit. FIG. 3 is a signal waveform diagram of the input signal buffer circuit.

In Figure 1-Figure 3, I is the input signal, O is the output signal, N11, N12 each node name, V _cc is the power supply voltage, V _ss is the ground voltage, Q _p 11~Q _p 15 each P-channel type MOS transistor, Q _n 11~Q _n 15 are each n-channel type MOS transistor.

Then, P-channel MOS transistor Q _p 11 and N-channel MOS transistor Q _n 11 and P-channel type MOS
Transistor Q _p 12 and N-channel MOS transistor Q _n 1
2 constitutes a first complementary MOS transistor group GCMOS1.

The first complementary MOS by a P-channel MOS transistor Q _p 13 and N-channel MOS transistor Q _n 13
Transistor CMOS1 is a P-channel MOS transistor
Second complementary by the Q _p 15 and N-channel MOS transistor Q _n 15 MOS transistors CMOS2 is, P-channel type
MOS transistor Q _p 14 and N-channel MOS transistor
By a Q _n 14 with third complementary MOS transistors CMOS3 is configured respectively, a first complementary MOS transistor CMOS and second complementary MOS transistor group by the third complementary MOS transistors CMOS3 GCMOS2 is It is configured.

Also, in the figure, INV1 to INV6 are negation circuits,
H is the high-side input switching level, and VIL is the low-side input switching level.

Next, the operation of the input signal buffer circuit will be described with reference to FIGS.

First, when the input signal I is at the logic voltage "L", the transistor Q _p 11, Q _p 12 is turned on, the transistor Q _n 11, Q since _n 12 is off, the node N11 is at logic voltage "H", the output signal O is logic voltage "L", the node N12 is at logic voltage "H", the transistor Q _p 13 is turned on, the transistor Q _p 14, Q _p 15 is turned off, the transistor Q _n 13 is turned on, the transistor Q _n 14, Q _n Reference numeral 15 is on, and the input switching level of the input signal I is shifted to the low side.

Next, when the input signal I becomes logical voltage "H", the transistor Q _p 11, Q _p 12 is turned off, the transistor Q _n 11, Q _n 12 is turned on, the node N11 is in the logical voltage "L", the output signal O is the logic voltage "H", the transistor Q _p 13 is off, since the transistor Q _n 13 is turned on, the less the delay time of the NOT circuit INV2~INV6 node N12 is a logic voltage "H" state And the transistors Q _p14 and Q _p15 are off and the transistor Q _n 1
4, Q _n 15 maintains the ON state, and the input switching level of the input signal I further shifts to the Low side.

Thus, the transistor Q _p to which the input signal I is input is
11, Q _p 12, Q _n 11, Q _n 12 connected in parallel with transistor Q _p 1
3, Q _n 13 receives a signal in phase with the input signal I, and immediately after the input signal I transitions from the logic voltage “L” to the logic voltage “H”,
Since the input switching level further shifts to the low side, as shown in FIG. 3, after the input signal I transitions from the logic voltage “L” to the logic voltage “H”, the logic voltage “H” level is changed by reflection or the like. It has the characteristic that it does not easily malfunction even if it is slightly lowered. That is, the dead zone of the input switching level immediately after the transition of the input signal I is as large as the conventional one as shown in FIG. 2 (B).

Next, when the delay time generated in the NOT circuits INV2 to INV6 elapses after the input signal I transitions from the logic voltage “L” to the logic voltage “H”, the node N12 becomes the logic voltage “L” and the transistor Q _p 14 , Q _p15 are turned on, and the transistors Q _n14 and Q _n15 are turned off, and the input switching level shifts to the high side, so that the input signal I easily transitions to the logic voltage “L”. That is, the dead zone of the input switching level after a lapse of a predetermined time from the transition of the input signal I becomes small as shown in FIG. 2 (A).

Similarly, when the input signal I changes from the logic voltage “H” to the logic voltage “L”, the input switching level is shifted to the high side when the input signal I is at the logic voltage “H”.
Immediately after the transition from the logic voltage “H” to the logic voltage “L”, the input switching level further shifts to the high side,
When the delay time generated at INV2 to INV6 elapses, the input switching level shifts to the low side.

As described above, the input signal buffer circuit according to the present embodiment has few malfunctions due to reflection or the like until a certain time elapses from the transition of the input signal I, and after a certain time elapses from the transition of the input signal. Has the characteristic that the dead band of the input switching level is reduced and the response to the next transition of the input signal is made at a high speed. In this case, the delay time of the negation circuits INV2 to INV6 is determined so that the logic voltage of the note N12 is inverted after the transition state of the transition of the input signal I ends and the output signal O is determined as shown in FIG. I do.

(Effect of the Invention) As described above, according to the input signal buffer circuit according to claim 1 or 2, the first complementary MOS transistor group to which the input signal is input is provided with the same phase as the input signal. Since the second complementary MOS transistor that receives a signal as an input and the third complementary MOS transistor that receives a delayed and delayed signal as an input signal are connected in parallel,
Immediately after the transition of the input signal, there is little malfunction due to reflection, etc., and after a lapse of time consisting of the transition of the input signal, the dead zone of the input switching level becomes small, and the transition of the next input signal is quickly responded. large.

According to the input signal buffer circuit of the invention of claim (3), the delay time of the signal which is in phase with the input signal input to the first complementary MOS transistor group and which is delayed from the input signal is set to a predetermined value. Since a delay circuit that makes the time longer than that of the input signal is provided, the dead band is reduced in preparation for the next transition of the input signal after the transient signal, which is likely to malfunction, is completed and the output signal is determined, so the dead band is reduced. Nevertheless, malfunctions are unlikely to occur.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input signal buffer circuit according to one embodiment of the present invention, and FIG. 2 (A) shows the input signal switching level of the input signal after a lapse of a predetermined time from the transition of the input signal in the input signal buffer circuit. A diagram showing a relationship with a power supply voltage,
FIG. 2B is a diagram showing the relationship between the input switching level of the input signal and the power supply voltage immediately after the transition of the input signal in the input signal buffer circuit. FIG. 3 is a signal waveform diagram of the input signal buffer circuit. 4 is a circuit diagram of a conventional input signal buffer circuit, FIG. 5 is a diagram showing a relationship between an input switching level of an input signal and a power supply voltage in the conventional input signal buffer circuit, and FIG. 6 is a view showing the conventional input signal buffer circuit. FIG. 3 is a signal waveform diagram of a buffer circuit. I ...... input signal O ...... output signal N11, N12, N21 ...... node name V _cc ...... supply voltage V _ss ...... ground voltage _{Q p 11~Q p 15, Q p} 21~Q p 23 ...... P -channel type MOS transistor _{Q n 11~Q n 15, Q n} 21~Q n 23 ...... n -channel type MOS transistor CMOS1 ...... first complementary MOS transistors CMOS2 ...... second complementary MOS transistors CMOS3 ...... third Complementary CMOS transistors GCMOS1... First complementary MOS transistor group GCMOS2... Second complementary MOS transistor group INV1 to INV7... NOT circuit D... Delay circuit VIH... Low-side input switching level

Claims (3)

(57) [Claims] A first complementary MOS transistor group to which an input signal is input; a first complementary MOS transistor to which a signal in phase with the input signal is input; An input signal buffer circuit, wherein a second complementary MOS transistor to which a signal delayed from an input signal is input is connected in parallel with each other. 2. A first complementary MOS transistor which receives a signal in phase with the input signal instead of the first complementary MOS transistor according to claim 1, and has a phase opposite to that of the input signal. An input signal buffer circuit comprising a second complementary MOS transistor group in which a third complementary MOS transistor that receives a signal delayed from the input signal is connected in series. 3. The input signal buffer circuit according to claim 1, wherein the delay time of the signal which is in phase opposite to the input signal and delayed from the input signal is equal to the first complementary time. P-channel type MOS transistor group
The amount of current flowing through the transistor group and the third complementary MOS
The time during which the sum of the amount of current flowing through the P-channel type MOS transistor and the amount of current flowing through the N-channel type MOS transistor group of the first complementary type MOS transistor group is less than or equal to the first complementary type MOS transistor group; And the amount of current flowing through the N-channel MOS transistor group of the third complementary MOS transistor.
A delay circuit is provided that causes the sum of the amount of current flowing through the OS transistor and the amount of current flowing through the P-channel MOS transistor group of the first complementary MOS transistor group to be later than each of the time periods. An input signal buffer circuit characterized by the above-mentioned.