JP3994802B2 - Malfunction prevention circuit and integrated circuit device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a malfunction prevention circuit and an integrated circuit device using the malfunction prevention circuit, and more particularly to a malfunction prevention circuit provided between an input terminal of an integrated circuit and an internal circuit to prevent malfunction due to the influence of static electricity or surge voltage. is there.
[0002]
[Prior art]
An integrated circuit device obtained by converting a digital logic circuit into an IC has a TTL (Transistor Transistor Logic) or C-MOS (Complementary-MOS) type logic circuit configuration and is widely used in various electronic devices. It is known that the impedance of the input terminal of such an integrated circuit device is generally very high, and is therefore easily affected by static electricity, surge voltage, and the like.
[0003]
Among these circuits, especially when static electricity or surge is superimposed on signal lines used for clocks, strobes, etc., the circuit will malfunction even if it is momentary noise. . Therefore, conventionally, a smoothing circuit using RC (resistor, capacitor) is inserted into the corresponding signal line, and its time constant is set to the limit that does not adversely affect the signal pulse. By doing so, the signal passes, and static electricity and surge are smoothed by this RC smoothing circuit, so that it does not exceed the threshold (logic change point) of the logic circuit inside the IC. It is possible to prevent malfunction due to surge.
[0004]
[Problems to be solved by the invention]
As described above, when an RC smoothing circuit is used as a malfunction prevention circuit of an integrated circuit device, a high-speed signal cannot be used, and thus the operation speed of the logic circuit is lowered. Further, in order to increase the electrostatic resistance, there is no method other than increasing the time constant of the RC smoothing circuit, and as a result, the signal speed is inevitably reduced. Furthermore, since a waveform having an excessive response in which the rising and falling characteristics of the signal are deteriorated is applied to the input of the internal logic circuit of the IC, a through current in the circuit (especially in a C-MOS circuit, The complementary conductivity type MOS transistors are not turned on at the same time, and there is also a disadvantage that the number of through currents is small).
[0005]
An object of the present invention is to provide a malfunction prevention circuit capable of effectively preventing malfunctions due to static electricity, surges, etc., and an integrated circuit device using the same, without slowing down the signal and increasing the through current.
[0006]
[Means for Solving the Problems]
A malfunction prevention circuit according to the present invention is a malfunction prevention circuit provided between an input terminal of an integrated circuit and an internal circuit for preventing malfunction due to static electricity or surge, and is applied to the input terminal and higher than a power supply voltage. A pulse detecting means for detecting a superposed pulse at a level lower than the level and the ground potential; a delay means for delaying the input signal by at least a time longer than a delay time in the pulse detecting means; and the pulse for a time longer than the delay time. The extension means for extending the detection output of the detection means, and the non-existence period of the output of the extension means derives the output of the delay means as it is, and the existence period holds the output level of the delay means immediately before And a level holding means for deriving. The level holding means is level latch means for latching the immediately preceding input signal level in response to the detection output.
[0007]
Another malfunction prevention circuit according to the present invention is a malfunction prevention circuit provided between an input terminal of an integrated circuit and an internal circuit for preventing malfunction due to static electricity or surge, and is applied to the input terminal and supplied with a power supply voltage. A pulse detection means for detecting a superposed pulse of a higher level and a level lower than the ground potential ; a delay means for delaying the input signal by at least a time longer than a delay time in the pulse detection means; and a time longer than the delay time. It includes an extending means for extending the detection output of the pulse detecting means, and a gate means for on / off controlling the output of the delay means in accordance with the output of the extending means. The gate means is a logical product circuit that performs a logical product of the output of the delay means and the detection output.
[0008]
The pulse detection means includes positive and negative pulse detection means for detecting the positive and negative superimposed pulses, and logical sum means for combining the detection outputs of these positive and negative pulse detection means. This logical sum output is used as the detection output.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Referring to FIG. 1, an input signal A is supplied from an input terminal 1 of a logic IC to a positive pulse detection circuit 2, a negative pulse detection circuit 3, and a delay circuit 6. The positive pulse detection circuit 2 detects a large positive voltage pulse that exceeds the power supply voltage. The negative pulse detection circuit 3 detects a large negative pulse that is lower than the ground potential.
[0010]
The detection pulses B and C which are detection outputs of both the pulse detection circuits 2 and 3 are input to the OR circuit 4. The logical sum output D is extended by the pulse extension circuit 5 to become the control signal E of the level holding circuit 7 by extending the pulse width. The input signal F delayed by the delay circuit 6 is delayed by a predetermined time (G) and supplied to a logic circuit (not shown) inside the IC via the level holding circuit 7.
[0011]
The level holding circuit 7 has a function of passing the input signal F as it is during the non-existence period of the output pulse E of the pulse stretching circuit 5, and holding and outputting the level immediately before the existence period of the output pulse E. As will be described later, a latch circuit can be used.
[0012]
FIG. 2 is an example of the waveform of each part showing the operation of the circuit of FIG. 1. Assume that A to G in FIG. 2 correspond to the waveforms of the signals A to G in FIG. Assume that the input signal shown in FIG. 2A is applied to the input terminal 1.
[0013]
Until the noise such as static electricity indicated by X in the figure is superimposed, the detection pulse is not output from the positive and negative pulse detection circuits 2 and 3, and therefore the control signal E from the pulse stretching circuit 5 is not output. Therefore, the level holding circuit 7 derives the input F as it is.
[0014]
When the next positive pulse indicated by X is input, the positive pulse detection circuit 2 detects this pulse X higher than the power supply voltage, and a high detection pulse B is output during that interval. In the portion Y, a pulse lower than the ground potential is detected by the negative pulse detection circuit 3, and a high detection pulse C is output during that interval. The logical sum of these two detection pulses is calculated, and a signal D indicating the application timing of the superimposed pulse due to static electricity or the like is output from the logical sum circuit 4.
[0015]
In order to reliably cut off the input signal at this timing, the pulse extending circuit 5 extends the pulse width by delaying the signal D or the like, and the control signal E is sent to the level holding circuit 7. Entered. Here, the input signal A itself is given an appropriate delay by the delay circuit 6 in consideration of the signal delay in the positive / negative pulse detection circuit, the OR circuit, the pulse extension circuit, etc., and is input to the level holding circuit 7. Is done.
[0016]
In the level holding circuit 7, as described above, the non-existing period (low level period) of the control signal E is derived as it is while the input signal passes as it is, and the existing period (high level period) is derived while holding the previous level. By doing so, the signal having the waveform of FIG. 2G is supplied to the logic circuit inside the IC, and the superimposed pulse such as static electricity is removed. Therefore, it is possible to prevent malfunction.
[0017]
Next, the relationship between the waveform at the moment when static electricity or the like is applied and the timing of each part signal waveform will be described with reference to FIG. 3 is an enlarged view of a portion indicated by 100 in FIG. 2, and the reference numerals A to D are the same as those in FIG.
[0018]
In FIG. 3, a indicates the transition time required for transition from high to low of the original signal A, b indicates the delay time of the positive pulse detection circuit 2, c indicates the delay time of the OR circuit 4, and d Indicates the extension time in the pulse extension circuit 5, and e indicates the delay time of the delay circuit 6. X and y represent timing margins.
[0019]
At this time, with respect to appropriate timing margins x and y (parameters that vary depending on circuit signal speed, surrounding circuit, assumed static electricity behavior, etc.), the delay is set so that a + b + c + x> e and d> e + y. If the times d and e are set, the influence of static electricity or the like can be completely removed from the input signal A as shown by G in FIG.
[0020]
FIG. 4 is a diagram showing a specific example of the circuit of FIG. 1. In the positive pulse detection circuit 2, when the input signal greatly exceeds the positive power supply Vcc, the transistor Q1 and the diode D1 are brought into conduction, and the collector current is supplied to the transistor Q1. Therefore, a high pulse is output via the collector resistor R1 and the buffer G1. Also in the negative pulse detection circuit 3, when the input signal greatly exceeds the ground potential, the transistor Q2 and the diode D2 become conductive, and similarly, a high pulse is output via the resistor R2 and the inverter I1.
[0021]
The pulse stretching circuit 5 can be easily realized by taking the OR of the delayed pulse by the resistor R3 and the capacitor C1 and the input pulse by the OR gate 51. Since the delay circuit 6 is for delaying signal transmission, it can be realized by providing a plurality of stages of gates (True Gates) G1 to G5 in series.
[0022]
FIG. 5 shows an example of the level holding circuit 7 in FIGS. 1 and 4, which includes an inverter 72 that inverts the control signal E and a level latch circuit 71 that performs level latch control by the output of the inverter 72. . When the control signal E is at the low level, the input F becomes the output G as it is, and when the control signal E is at the high level, the level of the previous input F is latched and output.
[0023]
FIG. 6 shows another example of the pulse stretcher circuit 5. Instead of the RC delay circuit (see FIG. 4), gates (True Gates) 52 to 55 connected in series are used.
[0024]
FIG. 7 is a block diagram of another embodiment of the present invention, and the same parts as those in FIG. In this example, a gate circuit 9 is used instead of the level holding circuit 7 of FIG. 1, and the other configuration is the same as that of FIG. That is, the input signal F is completely cut off by the gate circuit 9 while the output pulse E of the pulse extension circuit 5 is present (while the pulse E is at a high level), and during the other periods, the input signal F As shown in FIG. 8, an example of the gate circuit 9 is shown.
[0025]
That is, the logical product of the inverted signal of the control signal (gate signal) E and the input signal F is calculated by the AND gate 91 to obtain an output G. In this example, unlike the example of FIG. 1, the input signal is completely cut off while the gate signal E is present. Therefore, the portion indicated by 100 in FIG. When noise is superimposed during period 2, the output G is at a low level during that period. However, depending on the use of the signal A, it may not be possible, and it is used in such a case. Become. For example, the signal A may be a clock signal or a strobe signal.
[0026]
【The invention's effect】
As described above, according to the present invention, since it is not necessary to use a time constant circuit such as a smoothing circuit that greatly affects the signal waveform, it is possible to prevent malfunction without reducing the signal speed and increasing the through current. effective.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a timing chart of each part showing the operation of the block of FIG. 1;
FIG. 3 is a timing chart showing an enlarged portion indicated by 100 in FIG. 2 in terms of time.
FIG. 4 is a diagram showing a specific example of the block of FIG. 1;
5 is a diagram illustrating an example of a level holding circuit in FIGS. 1 and 4. FIG.
FIG. 6 is a diagram illustrating another example of a pulse stretching circuit.
7 is a block diagram of another embodiment of the present invention. FIG. 8 is a diagram showing an example of the gate circuit 9 of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input terminal 2 Positive pulse detection circuit 3 Negative pulse detection circuit 4 OR circuit 5 Pulse extension circuit 6 Delay circuit 7 Level holding circuit 9 Gate circuit

Claims (6)

A malfunction prevention circuit provided between an input terminal of an integrated circuit and an internal circuit for preventing malfunction due to static electricity or surge ,
Pulse detecting means for detecting a superimposed pulse applied to the input terminal and having a level higher than a power supply voltage and a level lower than a ground potential ;
Delay means for delaying the input signal by a time at least greater than the delay time in the pulse detection means;
An extension means for extending the detection output of the pulse detection means by a time greater than the delay time;
The malfunction is characterized in that the non-existence period of the output of the stretching means derives the output of the delay means as it is, and the existence period includes level holding means that holds and derives the output level of the delay means immediately before Prevention circuit.   2. The malfunction prevention circuit according to claim 1, wherein the level holding means is level latch means for latching a previous input signal level in response to the detection output. A malfunction prevention circuit provided between an input terminal of an integrated circuit and an internal circuit for preventing malfunction due to static electricity or surge ,
Pulse detecting means for detecting a superimposed pulse applied to the input terminal and having a level higher than a power supply voltage and a level lower than a ground potential ;
Delay means for delaying the input signal by a time at least greater than the delay time in the pulse detection means;
An extension means for extending the detection output of the pulse detection means by a time greater than the delay time;
And a gate means for controlling on / off of the output of the delay means in accordance with the output of the extension means.   4. The malfunction prevention circuit according to claim 3, wherein the gate means is a logical product circuit that makes a logical product of the output of the delay means and the detection output.   The pulse detection means includes positive and negative pulse detection means for detecting the positive and negative superimposed pulses, and logical sum means for logically combining the detection outputs of these positive and negative pulse detection means. 5. The malfunction prevention circuit according to claim 1, wherein a sum output is used as the detection output.   An integrated circuit device comprising the malfunction prevention circuit according to claim 1.

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