JP3245573B2 - Bidirectional buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bidirectional buffer circuit, and more particularly to a bidirectional buffer circuit used for an input / output unit in an LSI circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in the number of pins and the scale of LSIs, the collision of input / output signals on a bus connected to the input / output terminals of a bidirectional buffer, that is, the sum of noise due to bus fight, has increased. This is a problem when testing the LSI. That is, as is generally known, when the sum of the noises increases, the power supply voltage or the ground level fluctuates, and the internal circuit of the LSI malfunctions. As a countermeasure, a method of adjusting the I / O switching timing of the enable signal of the bidirectional terminal at the time of testing the LSI has also been proposed. However, the timing is adjusted to various timings due to device manufacturing variations and circuit path differences. It is extremely difficult.

When the input state / output state of the bidirectional buffer is switched between the input signal level and the output signal level at the time of switching, that is, at the time of switching from the input state to the output state, the input signal level is changed. "0"
Or "1" (hereinafter referred to as "0" / "1") to the output signal level "0" / "1", or at the time of switching from the output state to the input state, the output signal level "
In each case from 0 "/" 1 "to the input signal level" 0 "/" 1 ", no bus fight occurs, however, in the LSI test, the failure detection rate is improved under all input / output conditions. This is an inevitable task, and it is not possible to switch only the above combinations only by testing.

Referring to FIG. 7, which shows a block diagram of a generally known conventional first bidirectional buffer circuit, the conventional first bidirectional buffer circuit includes an input buffer 11 for an input interface and a supply of an enable signal E. And a bi-directional terminal 10 for input / output, which is a three-state buffer that is activated in response to the input signal and is composed of an output buffer circuit 12 for an output interface.

Next, the operation of the first conventional bidirectional buffer circuit will be described with reference to FIG. 7 and FIG. 8 which is a time chart showing the waveforms of the signals of various parts. First, in the input mode, the enable signal E Becomes "0", and in response to this, the output buffer 12 is in a high impedance state (hereinafter "").
HiZ ″), an output signal O (hereinafter referred to as an internal output signal) from an internal circuit (not shown) is cut off, and no external output signal SO is output to the bidirectional terminal 10. On the other hand, an input signal from the bidirectional terminal 10 is shown. No external input signal S
I is supplied after the output buffer 12 is completely “HiZ”, and is taken in as an input signal I (hereinafter referred to as an internal input signal) to an internal circuit via the input buffer 11. Note that the output signal SO and the input signal SI
Are collectively represented as a signal S.

Next, in the output mode, the enable signal E
Becomes "1". In response to this, the output buffer 12 becomes conductive, and the internal output signal O is output as the output signal SO to the bidirectional terminal 10. At this time, the supply of the input signal SI is stopped, that is, cut off.

In this conventional first bidirectional buffer, input / output modes are switched at the same time as the level transition timing of the enable signal E as shown in FIG. Accordingly, an ideal enable signal (original enable signal) EA having no delay / advance with respect to the input / output mode switching timing is supplied from an enable signal generation circuit of an internal circuit (not shown), and the output buffer 12 outputs this enable signal. When the cutoff / conduction operation is performed in response to the transition without timing delay, when the input mode is switched to the output mode, the input signal SI is cut off at the same time as the original enable signal EA rises from "0" to "1". When the output buffer 12 is turned on to pass the internal output signal O and output as the output signal SO, on the contrary, when the mode is switched from the output mode to the input mode, the original enable signal EA changes from "1" to "0". At the same time as the fall, the output buffer 12 becomes "HiZ", that is, the cutoff state, and the internal output signal O is blocked. And, the receiving state of the input of the input signal SI. For convenience of explanation, in FIG. 8, each level of the signals S, SI, and SO is represented by 0/1 or 1/0,
The signal SO / SI cut off corresponding to “HiZ” of the output buffer 12 is represented by Z.

However, in practice, the timing of the enable signal E and the response time of the output buffer 12 are not always in the above-mentioned ideal state due to device manufacturing variations, circuit path differences, and the like. Generally, a delay / advance occurs with respect to the switching timing. Here, for convenience of explanation, it is assumed that the timing of the enable signal E is delayed with respect to the switching timing of the input / output mode, and the response of the output buffer 12 is not delayed.

Here, when switching from the output mode to the input mode, the supply timing of the input signal SI is earlier than the timing when the output buffer 12 changes from the conductive state to the cutoff state due to the delay of the timing of the enable signal E. When the level is opposite to the level of the output signal SO that has been output up to that time, a large current flows into the output buffer 12 from the outside or a large current flows from the output buffer 12 to the outside. That is, noise occurs. As a result, the power supply voltage temporarily supplied to the internal circuit decreases and the ground potential increases,
As a result, a malfunction of the internal circuit may occur. The above phenomenon occurs when the bus to the outside is temporarily set to the input signal S.
This is caused by the common use of I and the output signal SO. The sharing of the input / output signals of the bus is called a bus fight, and the above-mentioned sharing period is called a bus fight period TF.

Conversely, when switching from the input mode to the output mode, the cut-off timing of the input signal SI is later than the timing at which the output buffer 12 changes from the cut-off state to the conductive state, and the level of the input signal SI becomes lower than that of the output signal SO. When the level is opposite to the level, the same phenomenon as described above occurs. At this time, the output buffer 12 remains "HiZ" for a period corresponding to the delay of the enable signal E after switching to the output mode, and this period is called a bus float period B.

A second conventional bidirectional buffer circuit disclosed in Japanese Patent Laid-Open No. 2-119425 (Literature 1) which suppresses noise generation due to the bus fight has a common reference character as a component common to FIG. Referring to FIG. 9, which is similarly denoted by a block with a / number, the second conventional bidirectional buffer circuit includes a buffer circuit section 1 common to the first conventional bidirectional buffer circuit, and a bidirectional terminal. 10, a delay circuit 102 for delaying the enable signal E for a predetermined time, a NAND circuit 103 for performing a NAND operation of an output of the delay circuit 102 and the enable signal E, and an inverter 104 for inverting an output of the NAND circuit 103 And the input signal SI / output signal S controlled by the output of the NAND circuit 103 and the output of the inverter 104 inserted between the buffer circuit unit 1 and the bidirectional terminal 10. And a transfer gate 105 for performing a connection / disconnection.

The operation of the second conventional bidirectional buffer circuit will be described with reference to FIG. 9. Delay circuit 102 delays input enable signal E by a predetermined time (hereinafter, control delay time), and outputs the output. It is supplied to one input of the NAND circuit 103. The NAND circuit 103 performs a NAND operation on the enable signal E supplied to the other input and the output of the delay circuit 102, and supplies the output to one input of the inverter 104 and one input of the transfer gate 105, respectively. The transfer gate 105 is formed by commonly connecting the sources and drains of the PMOS transistor and the NMOS transistor, and receives the output of the NAND circuit 103 at the gate of the PMOS transistor and the output of the inverter 104 at the gate of the NMOS transistor. . In each steady state of the input mode or the output mode, the two input levels of the NAND circuit 103 are always the same, that is, “0” and “0” in the former and “2” in the latter.
1 "and" 1 ", and therefore the output of the NAND circuit 103 is" 0 ", so that the transfer gate 105 is conductive.

Next, when switching from the output mode to the input mode, the enable signal E changes from "1" to "0". In response to the transition of the enable signal E from “1” to “0”, the output buffer 12 transitions from the conductive state to the “HiZ” (interrupted) state. On the other hand, during the control delay time, NA
The ND circuit 103 outputs "1", and as a result, the transfer gate 105 is temporarily cut off during this delay time. Even if the input signal SI is supplied within the cutoff time, the transmission of the input signal SI to the internal circuit is prevented. Therefore, even if the output buffer 12 has not completed the transition to the high impedance state, the output signal SO is not output. And input signal SI
, No bus fights occur.

Conversely, when the mode is switched from the input mode to the output mode, similarly, the enable signal E changes from "0" to "0".
In response to the transition to “1”, the NAND circuit 103 outputs “1” for the control delay time, and the transfer gate 105
Is temporarily shut off during this delay time. If the output buffer 12 is completely switched from “HiZ” to the conductive state within the time of the cutoff state, no bus fight occurs naturally.

Therefore, by appropriately selecting the control delay time, bus fight at the time of mode switching can be prevented.

However, in the case where there are various timing differences such as the supply timing of the input signal and the switching of the three-state buffer for the output due to the manufacturing variation of the device or the difference of the circuit path, all of these are possible. It is extremely difficult and impractical to appropriately set the control delay time to correspond to the case. In addition to the above reasons, if the actual bus fight period is long and exceeds the control delay time for some reason, the bus fight cannot be prevented even by the second bidirectional buffer circuit.

[0017]

In the above-described conventional first bidirectional buffer circuit, when switching from the output mode to the input mode, the supply timing of the input signal is determined based on the timing at which the output buffer circuit changes from the conductive state to the cutoff state. The output buffer circuit becomes conductive from the cut-off state when the level is opposite to the level of the output signal that was being output up to that point, or conversely, when switching from the input mode to the output mode. If the cutoff timing of the input signal is later than the timing of the state, and furthermore, if the level of the input signal being input is opposite to the level of the output signal, a bus fight occurs,
The noise caused by the inflow of a large current into the output buffer circuit or the outflow of a large current from the output buffer circuit causes a drop in the power supply voltage supplied to the internal circuit and a rise in the ground potential temporarily. As a result, there is a disadvantage that a malfunction of the internal circuit may occur.

The second conventional bidirectional buffer circuit which suppresses noise generation due to the bus fight has a difference in input / output signal supply timing due to device manufacturing variations and circuit path differences, and a three-state buffer for output. There is a drawback that it is extremely difficult to properly set the control delay time so as to correspond to all possible cases when there are various timing differences such as the switching operation timing difference. . In addition to the above-mentioned reason, there is a disadvantage that the bus fight cannot be prevented when the actual bus fight period is long and exceeds the control delay time for some reason.

An object of the present invention is to appropriately cope with a difference in supply timing of input / output signals and a difference in operation timing of a three-state bus due to manufacturing variations of devices, differences in circuit paths, and the like. An object of the present invention is to provide a bidirectional buffer circuit capable of reliably preventing fight.

[0020]

According to a first aspect of the present invention, a bidirectional buffer circuit has an input / output bidirectional terminal, an input terminal connected to the bidirectional terminal, and an output terminal connected to an input terminal of an internal circuit. An input buffer for an input interface; and a three-state buffer activated in response to a first level of an enable control signal, wherein an input terminal is an internal output terminal which is an output terminal of the internal circuit, and an output terminal is the bidirectional. A buffer circuit unit having an output buffer for an output interface connected to each of the terminals, and an internal output signal that is an output signal of the internal circuit in response to a first level of the enable control signal. Output as an external output signal from a terminal, and shut off the internal output signal and stop the external output signal in response to a second level of the enable control signal. A bidirectional buffer circuit for supplying an external input signal supplied to the bidirectional terminal to the internal circuit as an internal input signal, wherein the internal output signal and the external output signal or the external input signal and the enable control signal are enabled. In response to detection of a bus fight state in which the signal is supplied and the external output signal and the external input signal are simultaneously present at the bidirectional output terminal, the enable signal is suppressed during the bus fight state. A bus fight prevention circuit that supplies the enable control signal controlled as described above to a control input of the output buffer; and a three-state buffer that is activated in response to a first level of the enable signal. The output buffer is lower than the output buffer at a predetermined ratio by a predetermined ratio. It is constituted by a low drive buffer end together connected in parallel.

According to a second aspect of the present invention, there is provided a bidirectional buffer circuit having an input / output bidirectional terminal, and an input interface input buffer having an input terminal connected to the bidirectional terminal and an output terminal connected to an input terminal of an internal circuit. And a three-state buffer activated in response to a first level of an enable control signal, wherein an output terminal is connected to an internal output terminal which is an output terminal of the internal circuit, and an output terminal is connected to the bidirectional terminal. An output buffer for an interface; and a buffer circuit unit having an output buffer for an interface.
And outputs an internal output signal, which is an output signal of the internal circuit, as an external output signal of the bidirectional terminal in response to the second control signal level, and shuts off the internal output signal in response to a second level of the enable control signal. A bidirectional buffer circuit that stops the external output signal and supplies an external input signal supplied to the bidirectional terminal to the internal circuit as an internal input signal, wherein the internal output signal and the external output signal or the external input signal are provided. (Hereinafter referred to as an external input / output signal) and the enable signal, in a state where the external output signal and the external input signal exceeding a predetermined first threshold value are simultaneously present at the bidirectional output terminal. A first combining enable controlled to suppress the enable signal during the first bus fight state in response to detection of the first bus fight state; A first bus fight prevention circuit for supplying a signal to a control input of the output buffer; and a supply of the internal output signal, the external input / output signal, and an enable signal corresponding to the enable control signal, to the bidirectional output terminal. In response to the detection of the second bus fight state in which the external output signal and the external input signal having a predetermined second threshold value or less are present at the same time, the second bus fight state is detected during the second bus fight state. A second bus fight prevention circuit for supplying a second combined enable signal controlled to suppress the enable signal to a control input of the output buffer;
A combining circuit for logically combining the first and second combined enable signals and outputting the enable control signal; and a three-state buffer activated in response to a first level of the enable signal, and having a driving capability. The output buffer is configured to have a lower driving capability at a predetermined ratio than the output buffer and a low drive buffer in which input terminals are connected in parallel with each other and output terminals are connected in parallel.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIG. 1 in which constituent elements common to FIG. 1, the bidirectional buffer circuit of the present embodiment shown in the figure has a common input terminal as in the prior art, a bidirectional terminal 10 described later, and an output terminal having an input terminal T of an internal circuit (not shown).
A three-state buffer which is activated in response to the supply of an enable signal and an input buffer 11 for an input interface connected to each I. The input terminal is bidirectionally connected to an internal output terminal TO which is an output terminal of an internal circuit. Terminal 1
0, and a bidirectional terminal corresponding to an internal output signal O and an output signal SO, in addition to a buffer circuit section 1 composed of an output buffer 12 for an output interface connected to each of the output signals SO and SO. A bus fight prevention circuit for receiving a supply of the input / output signal S and the enable signal E and for supplying a combined enable signal EC controlled to suppress the enable signal E to the control input of the output buffer 12 in response to detection of the bus fight state; 2 and a three-state buffer that is activated in response to the supply of an enable signal E input via the enable signal input terminal TE and has a drive capability of about 1/10 or less of the drive capability of the output buffer. The output buffer 12 includes a low drive buffer 3 connected in parallel with the output buffer 12.

The bus fight prevention circuit 2 has a predetermined threshold voltage VT, compares the level of the internal output signal O with the level of the input / output signal S, and responds to a mismatch between these signals O and S. A mismatch detection circuit 21 for outputting a mismatch detection signal CD, and an enable signal synthesis circuit 2 for outputting a synthesis enable signal EC controlled to invalidate the enable signal E during the output period of the mismatch detection signal CD.
2 is provided.

The mismatch detecting circuit 21 has, for example, one input terminal connected to the internal output terminal TO and the other input terminal connected to the bidirectional terminal 1.
Two-input exclusive OR (EXOR) connected to 0
It can be realized by a circuit or the like.

The enable signal synthesizing circuit 22 includes, for example,
One of the inverting input terminals is supplied with the enable signal E and the other of the positive input terminals is supplied to the mismatch detecting circuit 2.
1 can be realized by a two-input NOR circuit or the like which outputs the combined enable signal EC by connecting the output terminal to the enable terminal of the output buffer 12 and outputting the combined enable signal EC. Note that this NOR
The circuit may include a positive input terminal instead of the inverting input terminal, and an inverter having an output terminal connected to the positive input terminal and inverting the enable signal E.

FIG. 1 is a time chart showing the level value of each signal in the input mode / output mode, and FIG. 3 is a time chart showing the waveform of each signal in the input mode / output mode. With reference to the operation of the present embodiment, first, an enable signal generation circuit of an internal circuit (not shown) corresponds to an ideal enable signal (original enable signal) EA having no delay / advance with respect to the input / output mode switching timing. The operation of preventing bus fight when the input signal "0" in the input mode is switched to the output signal "1" in the output mode in response to the supply of the enable signal E supplied to the enable signal input terminal TE will be described. .

In FIG. 3, when the mode changes from the input mode to the output mode, the enable signal E changes from "0" to "1". Here, for convenience of description, the standard rising timing of the enable signal E at the enable signal input terminal TE is time T1, and the rising timing of the enable signal E at the source of the enable signal E of the internal circuit is time T0. Define. Further, the variation range of the rising timing of the enable signal E at the enable signal input terminal TE due to LSI manufacturing variation or the like is defined as time T0 to time T2, and this time T2 is a time delayed from time T1 by T0 to T1. I do. Here, for convenience of explanation, there is no bus fight prevention circuit 2 and low drive buffer 3, and therefore the enable signal E is directly supplied to the output buffer 12, that is, the same state as the conventional first bidirectional buffer. And The current driving capability of the output buffer 12 is 24 mA, and the current driving capability of the low driving buffer is 2 mA.
And

At this time, "0" level is applied to the bidirectional terminal 10 as the input signal SI until the timing of the time T1 in accordance with the timing of the level transition of the enable signal E. However, in fact, the rising timing of the enable signal E varies in the range from time T0 to time T2 due to manufacturing variations of the LSI. At this time, if the rising timing of the enable signal E is earlier than the standard time T1 and varies in the direction of the time T0, the bidirectional terminal 1
During the period from T0 to T1, "0" is supplied as the input signal SI, and at the same time, the output signal from the internal circuit (hereinafter referred to as an internal output signal) O "because the output buffer 12 is still conductive.
1 "propagates to output a corresponding output signal SO" 1 ", thereby causing a bus fight.On the contrary, the rising timing of the enable signal E is delayed by T from the standard time T1.
If it fluctuates in two directions, T1-T
During the period 2, the input signal SI is not supplied, and at the same time, the output buffer 12 is in a high impedance state (hereinafter "HiZ"), so that a bus float occurs.

Next, the present embodiment including the bus fight prevention circuit 2 and the low drive buffer 3 in the case where the rising timing of the enable signal E is earlier than the standard timing and the former bus fight varies in the direction of time T0. The operation will be described. First, in the periods T0 to T1, the mismatch detection circuit 21 of the bus fight prevention circuit 2
An exclusive OR operation is performed on the input signal SI and an output signal (hereinafter, an internal output signal) O from an internal circuit. At this time, as described above, the input signal SI is “0” and the internal output signal O is “
Since the mismatch state is “1”, the mismatch detection circuit 21
Becomes "1" and supplied to the positive input terminal of the enable signal synthesizing circuit 22. Since the enable signal E "1" which has already risen is supplied to the inverting input terminal of the enable signal synthesizing circuit 22, the enable signal synthesizing circuit 22 outputs these mismatch detection signals CD ".
1 and the inverted value "0" of the enable signal E, and outputs a composite enable signal EC "0." At this time, the low drive buffer 3 starts conducting in response to the rise of the enable signal E, and the internal state of the low drive buffer 3 starts. Output signal L corresponding to output signal O
O starts to be output, which causes a bus fight. However, since the driving capability is as low as 1/12 of the output buffer 12, the influence on the malfunction is small.

Next, in the periods T1 and T2, the output signal LO of the low drive buffer 3 further rises toward "1",
When the potential S of the bidirectional terminal 10 becomes equal to or higher than the threshold voltage VT of the mismatch detection circuit 21, the logical value of the internal output signal O matches the potential S, and the mismatch detection signal CD becomes "0". The enable signal synthesis circuit 22 outputs the mismatch detection signal CD "
The output buffer 12 performs a NOR operation on “0” and the inverted value “0” of the enable signal E and outputs a combined enable signal EC “1.” The output buffer 12 responds to the supply of the combined enable signal EC “1” by “HiZ”. From the internal output terminal TO, that is, the internal output signal O ″.
1 "and the potential S of the bidirectional terminal 10 rapidly become the same potential, that is, the output signal SO" 1 "at the same level as the internal output signal O" 1 ". Since the supply of SI "0" ends, the bus fight does not occur due to the output signal SO "1", and therefore, the bus fight that occurs during the entire period T0 to T2 is caused only by the low drive buffer 3, Noise generated by bass fight can be greatly reduced.

In the above example, the case where the input signal is switched from the input signal "0" in the input mode to the output signal "1" in the output mode has been described. , When the output signal is switched to “0” in the output mode, or when the output signal is “1” in the output mode and the input signal in the input mode is “1”.
It goes without saying that the same operation is performed when the signal is switched to "0" and when the signal is switched from the output signal "0" in the output mode to the input signal "1" in the input mode.

FIG. 2 shows an overall time chart summarizing the above description. The bus fight period TF itself is generated by the low drive buffer in the same manner as in the prior art. There is no change from 8.

Next, comparing the noise value of the present embodiment with the first conventional example (hereinafter referred to as the conventional example) using specific numerical examples, the driving capability of the output buffer is as described above. 24 mA, the driving capability of the low driving buffer is 2 mA, and the impedance of the ground through which the driving current flows is 5Ω.
Assume that two bidirectional buffer circuits simultaneously bus fight. For convenience of explanation, the noise value per one bidirectional buffer circuit is simply the drive current × ground impedance (V), and the sum of the noise is the noise value of each bidirectional buffer circuit × the bidirectional buffer circuit performing bus fight simultaneously. (V).

Conventional noise sum = (24 mA × 5Ω)
× 32 = 3.84 V Total noise of this embodiment = (2 mA × 5Ω) × 32 =
0.32 V, and the total noise can be reduced to 1/12.

For this reason, it is possible to avoid a phenomenon in which the LSI malfunctions due to the noise of the conventional bus fight, and the LSI test becomes defective.

Next, a second embodiment of the present invention will be described with reference to FIG. 4 in which constituent elements common to those in FIG. This embodiment is different from the first embodiment in that the bus fight prevention circuit 2 is replaced by a mismatch detection circuit 21 and an enable signal synthesis circuit 22 of the bus fight prevention circuit 2.
, A bidirectional terminal 1 corresponding to the output signal SO,
A low threshold buffer 43 having a low threshold voltage VTL is provided at the input of the input / output signal S of 0, and the input / output signal S is supplied with the internal output signal O, the input / output signal S, and the enable signal E. Bus fight prevention circuit 4 that outputs a first combined enable signal EC1 controlled to suppress enable signal E in response to detection of a bus fight state when the level is equal to or higher than low threshold voltage VTL.
And an inconsistency detection circuit 51 and an enable signal synthesis circuit 52 similar to the inconsistency detection circuit 21 and enable signal synthesis circuit 22 of the bus fight prevention circuit 2, and a high threshold voltage VTH is applied to the input of the input / output signal S. Receiving the internal output signal O, the input / output signal S, and the enable signal E to detect the bus fight state when the level of the input / output signal S is lower than the high threshold voltage VTH. A second bus fight prevention circuit 5 for outputting a second combined enable signal EC2 controlled in response to suppress the enable signal E, and enable signals EC1 and EC2
And a synthesizing circuit 6 for synthesizing and outputting a synthesizing enable signal EC to supply the control input to the output buffer 12. The buffer circuit section 1, the low drive buffer 3, and the bidirectional terminal 10 other than those described above are common components in the first embodiment.

The bus fight prevention circuit 4 has an input terminal connected to the bidirectional terminal 10, receives the input / output signal S, and sets the input / output signal S to a predetermined low level from the "0" level.
Here, for convenience of explanation, “1” is set to 5 V, and the low threshold buffer 43 of the low threshold voltage VTL which outputs the output signal LS when the level rises to 1V which is １ ／ of the level, and the internal output signal O Output signal LS of low threshold buffer 43
And a mismatch enable circuit 41 that outputs a mismatch detection signal CD1 in response to a mismatch between these signals O and LS, and a combining enable control that disables the enable signal E during the output period of the mismatch detection signal CD1. Signal E
And an enable signal synthesizing circuit 42 for outputting C1.

The bus fight prevention circuit 5 has an input terminal connected to the bidirectional terminal 10, receives the input / output signal S, and sets the input / output signal S to a predetermined high level from the "1" level.
Here, for convenience of explanation, "1" is set to 5 V, and when the voltage drops to 4 V, which is 4/5 of the level, the high threshold buffer 53 of the high threshold voltage VTH which outputs the output signal HS, and the internal output signal O Output signal HS of high threshold buffer 53
A mismatch detection circuit 51 which compares the levels of the signals O and HS and outputs a mismatch detection signal CD2 in response to a mismatch between the signals O and HS, and a combining enable which is controlled to invalidate the enable signal E during the output period of the mismatch detection signal CD2. Signal E
And an enable signal synthesizing circuit 52 for outputting C2.

The combining circuit 6 has, for example, one input terminal connected to the output terminal of the enable signal combining circuit 42 and the other input terminal connected to the output terminal of the enable signal combining circuit 52, and the output terminal connected to the enable terminal of the output buffer 12. And a two-input OR circuit that performs a logical sum (OR) operation on the combined enable signals EC1 and EC2 and outputs the combined enable signal EC.

The combined enable signal EC1 of the output of the bus fight prevention circuit 4 having the low threshold buffer 43 and the combined enable signal EC2 of the output of the bus fight prevention circuit 5 having the high threshold buffer 53 are combined. Circuit 6
When one of them becomes "1", the combined enable signal EC becomes "1", and the output buffer 12 of the buffer circuit unit 1 becomes conductive.

Next, referring to FIG. 4 and FIG. 5 which shows a waveform of each signal in a time chart in the input mode / output mode, first, the input signal in the input mode "
The operation of preventing bus fight when switching from "0" to the output signal "1" in the output mode will be described.

First, the input / output signal S is changed to the input signal SI "0".
When the output signal LO is switched from "0" to "1" in response to the supply of the enable signal E, as described in the first embodiment, when the output signal LO is switched from "0" to the output signal SO "1". Rise towards. The timing (time) when the output signal LO reaches the threshold voltage VTL = 1V of the low threshold buffer 43 and its output LS becomes the "1" level is T10, and the threshold of the high threshold buffer 53 is The timing (time) when the voltage VTH = 4V is reached and the output HS becomes the “1” level is defined as T11.

The non-coincidence detection circuit 41 of the bus fight prevention circuit 4 detects the coincidence between the internal output signal O "1" and the output signal LS "1" at time T10, and detects the non-coincidence detection signal CD1 "0".
Is output. The enable signal synthesizing circuit 42 operates at time T10.
Enable signal E "1" and mismatch detection signal CD1 "
From 0 ", a composite enable signal EC1" 1 "is output.

On the other hand, the mismatch detection circuit 51 of the bus fight prevention circuit 5 detects the match between the internal output signal O "1" and the output signal LS "1" at time T11, and outputs a mismatch detection signal CD.
2 "0" is output. The enable signal combining circuit 52 outputs a combined enable signal EC2 "1" from the enable signal E "1" at time T11 and the mismatch detection signal CD2 "0".

The synthesizing circuit 6 generates a synthesizing enable signal EC.
An OR operation is performed on 1 "1" and the composite enable signal EC2 "1" to generate a composite enable signal EC, which is supplied to the enable signal input terminal of the output buffer 12 of the buffer circuit unit 1. Therefore, the synthesis enable signal EC changes from “0” to “1” at time T10, and the output buffer 12
Becomes conductive from this time T10.

Next, referring to FIG. 4 and FIG. 6 which is a time chart showing waveforms of respective signals in the input mode / output mode, the input signal "1" in the input mode is changed from the input signal "1" in the output mode. The operation of preventing bus fight when switching to the output signal "0" will be described.

When the input / output signal S switches from the input signal SI "1" to the output signal SO "0", first, in response to the supply of the enable signal E, the output signal LO of the low drive buffer 3 is output.
Falls toward "0" and the input signal SI "1" turns off, the input / output signal S changes from the input signal SI "1" to "0".
Start descent toward. The timing (time) when the output signal LO reaches the threshold voltage VTH = 4V of the high threshold buffer 53 and the output HS thereof becomes the “0” level is represented by T2.
1, the threshold voltage VT of the low threshold buffer 43
The timing (time) when L = 1V and the output LS becomes the “0” level is defined as T21.

The non-coincidence detection circuit 51 of the bus fight prevention circuit 5 detects the coincidence between the internal output signal O "0" and the output signal LS "0" at time T20, and detects the non-coincidence detection signal CD2 "0".
Is output. The enable signal synthesizing circuit 52 operates at time T20.
Enable signal E "1" and the mismatch detection signal CD2 "
The composite enable signal EC2 "1" is output from "0".

On the other hand, the mismatch detection circuit 41 of the bus fight prevention circuit 4 detects a match between the internal output signal O "0" and the output signal LS "0" at time T21, and outputs a mismatch detection signal CD.
1 "0" is output. The enable signal combining circuit 42 outputs a combined enable signal EC1 "1" from the enable signal E "1" at time T10 and the mismatch detection signal CD1 "0".

Therefore, the synthesis enable signal EC, which is the output of the synthesis circuit 6, changes from "0" to "1" at time T20.
And the output buffer 12 becomes conductive from this time T20.

As described above, the bidirectional buffer circuit of the present embodiment converts the input signal SI “0” to the output signal S
When switching to O "1", the input signal SI is turned off, and when the level of the input / output signal S of both terminals 10 gradually rises to "1" level by the low drive buffer 3, the low level of the bus fight prevention circuit 4 The threshold buffer 43 is turned on at the low threshold voltage VTL, and its output LS rises rapidly, and conversely, the output signal SO "0" changes from the input signal SI "1".
, The input signal SI turns off, and both terminals 10
When the level of the input / output signal S is gradually lowered to "0" level by the low drive buffer 3, the high threshold buffer 53 of the bus fight prevention circuit 5 is turned off at the high threshold voltage VTH, Its output HS drops rapidly. Therefore, when the level of the output signal SO switches from "1" to "0" or from "0" to "1", the operation can be performed at a higher speed than in the first embodiment.

[0052]

As described above, the bidirectional buffer circuit of the present invention receives the supply of the internal output signal, the external input / output signal, and the enable signal, and responds to the detection of the bus fight state. A bus fight prevention circuit for supplying an enable control signal controlled to suppress the period enable signal to a control input of the output buffer; a three-state buffer activated in response to a first level of the enable signal; Has a low drive buffer connected in parallel with the output buffer at a predetermined ratio with respect to the drive capability of the output buffer, thereby providing input / output signals due to device manufacturing variations and differences in circuit paths.
By properly coping with the difference in the supply timing of the enable signal and the difference in the operation timing of the three-state output buffer, etc., the bus fight due to these factors can be reliably suppressed, and the noise caused by the bus fight can be suppressed. The effect is that generation can be greatly suppressed.

Furthermore, since there is no limit on the duration of the bus fight to be detected, there is an effect that it effectively functions even if the bus fight occurs for a long time for some reason.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a bidirectional buffer circuit of the present invention.

FIG. 2 is a first time chart illustrating an example of an operation in the bidirectional buffer circuit of the present embodiment.

FIG. 3 is a second time chart illustrating an example of an operation in the bidirectional buffer circuit of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the bidirectional buffer circuit of the present invention.

FIG. 5 is a first time chart illustrating an example of an operation in the bidirectional buffer circuit of the present embodiment.

FIG. 6 is a second time chart illustrating an example of an operation in the bidirectional buffer circuit of the present embodiment.

FIG. 7 is a block diagram showing an example of a second conventional bidirectional buffer circuit.

FIG. 8 is a time chart showing an example of an operation in a conventional first bidirectional buffer circuit.

FIG. 9 is a block diagram showing an example of a second conventional bidirectional buffer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer circuit part 2, 4, 5 Bus fight prevention circuit 3 Low drive buffer 6 Synthesis circuit 10 Bidirectional terminal 11 Input buffer 12 Output buffer 21, 41, 51 Mismatch detection circuit 22, 42, 52 Enable signal synthesis circuit 43 Low Threshold buffer 53 High threshold buffer 102 Delay circuit 103 NAND circuit 104 Inverter 105 Transfer gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (8)

(57) [Claims] A bidirectional terminal for input / output, an input buffer for an input interface having an input terminal connected to the bidirectional terminal and an output terminal connected to an input terminal of an internal circuit, and a first enable control signal. A three-state buffer that is activated in response to a level, and has an output buffer for an output interface having an input terminal connected to an internal output terminal that is an output terminal of the internal circuit and an output terminal connected to the bidirectional terminal. A buffer circuit unit, and outputs an internal output signal as an output signal of the internal circuit as an external output signal of the bidirectional terminal in response to a first level of the enable control signal; 2 to shut off the internal output signal and stop the external output signal in response to the external input signal supplied to the bidirectional terminal. A bidirectional buffer circuit that supplies an internal input signal to the internal circuit as an internal input signal, wherein the bidirectional output terminal receives supply of the internal output signal and the external output signal or an external input signal and an enable signal corresponding to the enable control signal; In response to detection of a bus fight state in which an external output signal and the external input signal are simultaneously present, the enable control signal controlled to suppress the enable signal during the bus fight state is controlled by the output buffer. A bus fight prevention circuit to be supplied to an input; a three-state buffer activated in response to a first level of the enable signal; and a driving capability lower than a driving capability of the output buffer at a predetermined ratio. A buffer and a low-drive buffer having input terminals connected in parallel and output terminals connected in parallel. Bidirectional buffer circuit according to claim. 2. The bus fight prevention circuit according to claim 1, wherein: an internal output signal supplied through the internal output terminal; an external output signal output from the bidirectional terminal; or an external input signal input to the bidirectional terminal. (Hereinafter referred to as an external input / output signal) and a mismatch detection circuit for outputting a mismatch detection signal in response to a mismatch between the internal output signal and the external input / output signal; 2. The bidirectional buffer circuit according to claim 1, further comprising: an enable signal synthesizing circuit that outputs the enable control signal controlled to invalidate the enable signal. 3. A two-input exclusive OR circuit having one input terminal connected to the internal output terminal and the other input terminal connected to the bidirectional terminal, respectively. 2. The bidirectional buffer circuit according to 2. 4. The enable signal synthesizing circuit receives the enable signal at one input terminal as an inverting input terminal, connects the other input terminal as a positive input terminal to an output terminal of the mismatch detection circuit, and outputs an output. 3. The bidirectional buffer circuit according to claim 2, further comprising a two-input NOR circuit that outputs the enable control signal from an end. 5. An inverter which receives the enable signal at an input terminal thereof and outputs an inverted enable signal obtained by inverting the enable signal at an output terminal of the enable signal synthesizing circuit, and supplies the enable signal to one of the input terminals. 3. The bidirectional buffer circuit according to claim 2, further comprising: a two-input NOR circuit that receives the other input terminal and connects to the output terminal of the mismatch detection circuit and outputs the enable control signal from the output terminal. 6. An input / output bidirectional terminal, an input buffer for an input interface having an input terminal connected to the bidirectional terminal and an output terminal connected to an input terminal of an internal circuit, respectively, and a first control signal for an enable control signal. A three-state buffer that is activated in response to a level, and has an output buffer for an output interface having an input terminal connected to an internal output terminal that is an output terminal of the internal circuit and an output terminal connected to the bidirectional terminal. A buffer circuit unit, and outputs an internal output signal as an output signal of the internal circuit as an external output signal of the bidirectional terminal in response to a first level of the enable control signal; 2 to shut off the internal output signal and stop the external output signal in response to the external input signal supplied to the bidirectional terminal. A bidirectional buffer circuit for supplying an internal input signal to the internal circuit as an internal input signal, wherein the bidirectional output terminal receives supply of the internal output signal and the external output signal or an external input signal (hereinafter, external input / output signal) and the enable signal; In response to detection of a first busfight state in which the external output signal and the external input signal exceeding a first threshold value are simultaneously present. A first bus fight prevention circuit for supplying a first combined enable signal controlled to suppress the enable signal to a control input of the output buffer; and a correspondence between the internal output signal, the external input / output signal, and the enable control signal. And the external output signal and the external input signal having a predetermined threshold value or less at the bidirectional output terminal. And a second combined enable signal controlled to suppress the enable signal during the second bus fight state in response to detection of a second bus fight state in which the output buffer and the output buffer exist simultaneously. A second bus fight prevention circuit for supplying a control input, a synthesis circuit for logically synthesizing the first and second synthesis enable signals and outputting the enable control signal, and a response to a first level of the enable signal A three-state buffer that is activated in a predetermined manner, and has a driving capability whose driving capability is lower than a driving capability of the output buffer at a predetermined ratio and a low driving buffer in which input terminals and input terminals are connected in parallel. Bidirectional buffer circuit. 7. The first bus fight prevention circuit has an input terminal connected to the bidirectional terminal, receives the input / output signal, and has a predetermined low-level voltage of the input / output signal. A low-threshold buffer that outputs a low-threshold signal when rising above a threshold value of 1. The level comparison between the internal output signal and the low-threshold signal is performed. A first inconsistency detection circuit that outputs a first inconsistency detection signal in response to the inconsistency of the threshold value signal, and a first control that invalidates the enable signal during an output period of the first inconsistency detection signal. A first enable signal synthesizing circuit for outputting a synthesized enable signal, wherein the second bus fight prevention circuit receives the input / output signal when the input terminal is connected to the bidirectional terminal and receives the input / output signal. Set in advance A high-threshold buffer that outputs a high-threshold signal when the second threshold value, which is a high-level voltage, falls below, a level comparison between the internal output signal and the high-threshold signal A second mismatch detection circuit that outputs a second mismatch detection signal in response to a mismatch between the internal output signal and the high threshold signal; and outputting the enable signal during an output period of the second mismatch detection signal. A second enable signal combining circuit that outputs a second combined enable signal controlled to be invalidated, wherein the combining circuit has one input terminal connected to the output terminal of the first enable signal combining circuit and the other input terminal connected to the other end. 7. The bidirectional buffer according to claim 6, further comprising a two-input OR circuit that connects an input terminal to an output terminal of the second enable signal synthesizing circuit and outputs an enable control signal from the output terminal. Circuit. 8. The method according to claim 1, wherein the predetermined ratio is 1/10 or less, and the driving capability of the low driving buffer is 1/10 or less of the driving capability of the output buffer. Bidirectional buffer circuit.