JPH0287711A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To detect a change in an address signal at a high speed by using P, N-channel transistors(TRs) of a prescribed connection and a resistive characteristic component. CONSTITUTION:Sources of P, N-channel TRs QPi, QNi whose drains and gates are connected in common respectively are connected to ground and a TR Qi of a resistive characteristic element connecting to the outputs side and the power supply Vcc. when an address Ai fed to gates of the TR QNi and QPi is fixed to H or L, the TR QPi and QNi are turned off and an output of a NAND gate 1 whose input is at H goes to an L level. On the other hand, when the address Ai changes, the output of the gate 1 goes to an H, a gate stage number is less and number of the TRs is less to detect an address signal change at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that detects a change in a signal.

[Conventional technology]

Recently, in order to speed up the access time of storage elements, changes in address signals have been detected to operate internal circuits.

Conventional semiconductor integrated circuits use a delay circuit and exclusive OR (EXC) to detect changes in address signals as shown in Figure 5.
This was achieved by combining LUSIVE OR) gates. The exclusive OR gate is actually N
It was composed of AND, NOR, and INVERTER gates, or it was composed of transfer gates.

[Problem to be solved by the invention]

The above-mentioned conventional semiconductor integrated circuit has a drawback that the number of transistors is large because it is configured with an exclusive OR gate, and the chip size becomes large.

Furthermore, there is a drawback that detection of a change in the address signal is delayed due to the large number of stages through which the gate passes.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, drains of a P-channel transistor and an N-channel transistor are commonly connected, gates of the P-channel transistor and N-channel transistor are commonly connected as an input, and a source of the N-channel transistor is grounded. The device is characterized in that the source of the P-channel transistor is used as an output, and a resistive element is connected between the output and the power source.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The trains of P-channel transistor QPO and N-channel transistor QNO are commonly connected. The gates of transistor QPO and transistor QNO are also commonly connected to input address signal AO. The source of transistor QNO is grounded. The source of the transistor QPO is used as the output, and the single power of the NAND gate 1 is used. transistor Q
■ Connect the gate between the source of PO and Vcc. An N-channel transistor QO connected to C is connected. As for address signals A1 to An, transistor QP is used similarly to AO.
1~QPn, QN]~QNn, Q1~Qn are connected, and each NAND gate 1 is operated by one person.

If the address signal is fixed to either It i g h or Low, both transistor QPi (same for i=o to n) and transistor QNi are OFF, and NAN
All inputs of D gate 1 become old gh, so the output OUT is Low. Address signal AO is now High
When the voltage changes from h to Low or from Low to old gh, both the transistor QPO and the transistor QNO become ONL near the intermediate potential, and the input of the NAND gate 1 becomes Low. Therefore, 0tJT becomes High, and it is possible to detect that the address signal has changed.

In Figure 2, AO is I and OW is If i in Figure 1.
gh is a timing diagram when changing to h. Even if one or more address signals other than address signal AO change, it can be detected in the same way.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

The sources of the P-channel transistors QPO to QPn are all connected in common and used as an output OUT. Output OUT and V.

A P-channel transistor Q with its gate grounded between 0 and 0
Connect L. If the address signal Ai is fixed at either High or Low, both the transistor QPi and the transistor QNi are turned off, and the output OUT becomes the old gh.

Now, when the address signal AO changes from 1igh to Low or from Low to gh, both transistor QPO and transistor QNO turn on near the intermediate potential.
do. Therefore, the output OUT becomes Low, and it is possible to detect that the address signal has changed.

FIG. 4 is a timing diagram when the address signal AO changes from Low to High in FIG.

Changes in address signals A1 to An can also be detected in the same way as address signal AO.

Although AO to An have been described as address signals in the above two embodiments, the present invention is not limited to A0 to An as address signals, and can similarly detect changes in any signals.

〔Effect of the invention〕

As explained above, the present invention connects a train of P-channel transistors and an N-channel transistor in common,
The gates of the P-channel transistor and the N-channel transistor are commonly connected as an input, the source of the N-channel transistor is grounded, the source of the P-channel transistor is an output, and an element with resistance characteristics is connected between the output and the power supply. By connecting them, changes in the address signal can be detected with a small number of transistors, thereby preventing the chip size from increasing. Furthermore, since the number of gates passing through is one, there is no delay in detecting changes in the address signal, and there is an advantage that high-speed operation is possible.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram of the first embodiment of the present invention, and Fig. 2 is a circuit diagram of the first embodiment of the present invention.
FIG. 3 is a circuit diagram of the second embodiment of the present invention; FIG. 4 is a timing diagram of the circuit of FIG. 3; FIG. 5 is a circuit diagram showing an example of the conventional technology; The figure is number 5
This is a combination circuit diagram for realizing exclusive OR used in the circuit shown in the figure. 1.8.9...NAND gate, 3,6. to...
I NVERTER gate, 11.12...NOR gate, 2.5...Delay circuit, QO, Ql ~ Qn, QNO, QNI ~ QNn-N, channel transistor, QL, QPO, QPI ~ QPn・
...P channel transistor, AO, At~An...
Address signal input, OUT...Address signal change point detection circuit output.

Claims (1)

[Claims] The drains of the P-channel transistor and the N-channel transistor are commonly connected, and the P-channel transistor;
The gates of the N-channel transistors are commonly connected as an input, the sources of the N-channel transistors are grounded,
A semiconductor integrated circuit characterized in that a source of the P-channel transistor is used as an output, and a change in input potential is detected by connecting an element with resistance characteristics between the output and a power supply.