JP2540765B2 - Malfunction prevention test circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention test circuit for preventing malfunction.

[0002]

2. Description of the Related Art Conventionally, an LSI terminal operates in a specific test mode (hereinafter referred to as "non-normal operation mode"). Therefore, the terminal has both the normal operation mode and the non-normal operation mode (hereinafter referred to as "combined terminal"). Is used. In such an LSI, when the power supply voltage fluctuates, the LS
There is a problem that the I operation mode is mistakenly changed to the non-normal operation mode. Therefore, as a method for solving the above problem, a method using a malfunction prevention circuit that detects the state of the terminal and shifts the LSI to the non-normal operation mode only when the detection result is the specific state has been proposed. .

FIG. 3 is a circuit diagram showing a conventional malfunction prevention test circuit.

The conventional malfunction prevention test circuit is composed of two normal operation mode circuits and one non-normal operation mode circuit. One of the normal operation mode circuits is an input circuit having an inverter 302, and the other one is an input circuit having an inverter 309. In the non-normal operation mode circuit, two high voltage detection circuits 331 and 332 are connected to the input terminals of the NAND circuit 315, respectively, and the N
The output terminal of the AND circuit 315 is a circuit connected to the inverter 316.

On the other hand, the high voltage detection circuit 331 has a P channel transistor 30 whose gate input is the power supply voltage.
4. N-channel transistor 305 and inverter 30
6 and 307, and the other high voltage detection circuit 332
Is composed of a P-channel transistor 311, an N-channel transistor 312, and inverters 313 and 314 whose gate input is the power supply voltage.

In the malfunction prevention test circuit, the output of the inverter 302 is the normal operation mode signal 303,
The output of the inverter 309 is the normal operation mode signal 310. Further, the circuit configured by the NAND circuit 315 and the inverter 316 outputs the logical product of the outputs from the high voltage circuits 331 and 332 as the abnormal operation mode signal 317.

In the malfunction prevention test circuit, when the terminals of the LSI are in the normal operation mode, the applied voltage is limited to the range from the ground level to the power supply voltage. Therefore, the normal operation mode signals 303 and 310 are low level or It becomes high level, and the non-normal operation mode signal 317
Is at a low level. Here, a voltage higher than the power supply voltage is applied to the terminals 301 and 308. Then
High-level signals are output from both the high-voltage circuits 331 and 332, and the NAND circuit 315 and the inverter 3 are output.
A high level signal is output from the circuit configured by 16. That is, the abnormal operation mode signal 317 becomes high level, and the operating state of the LSI shifts to the abnormal operation mode.

As described above, in the conventional malfunction prevention test circuit, the operating state of the LSI shifts to the non-normal operation mode only when the voltage applied to each terminal of the LSI becomes higher than the power supply voltage. It This prevents the operating state of the LSI from being erroneously transferred to the non-normal operation mode when the power supply voltage fluctuates.

[0009]

As described above, in the conventional malfunction prevention test circuit, malfunctions due to fluctuations in the power supply voltage are prevented, but the voltage applied to the terminals 301 and 308 causes noise, etc. that has flowed in from the outside. When the voltage becomes higher than the power supply voltage by the high voltage detection circuit 331 and 332,
Detected a high voltage, and the abnormal operating mode signal 31
7 becomes high level, and a transition to the non-normal operation mode is performed. As described above, the conventional malfunction prevention test circuit has a problem that it malfunctions due to inflow of external noise or the like.

An object of the present invention is to provide a malfunction prevention test circuit capable of preventing malfunction caused by the above-mentioned external noise.

[0011]

The malfunction prevention test circuit of the present invention has a plurality of dual-purpose terminals for the normal operation mode and the non-normal operation mode, and detects the states of the dual-purpose terminals to generate a test mode transition signal. In the malfunction prevention test circuit, when a positive voltage equal to or higher than a first predetermined value is applied to at least one of the dual function terminals, a first detection signal indicating the fact is output. Voltage detection circuit,
When a negative voltage lower than a second predetermined value is applied to the dual-purpose terminal, which is different from the dual-purpose terminal to which the high-voltage detection circuit is connected, a second detection signal indicating that is output. A low voltage detection circuit, and a logic means for outputting a logical product of the first and second detection signals output by the high voltage detection circuit and the low voltage detection circuit, respectively, as the test mode transition signal. To do.

In this case, the high-voltage detection circuit includes a first P-channel transistor whose gates are commonly connected to the power supply voltage and an N-channel transistor whose on-state resistance is larger than that of the first P-channel transistor. , The source of the first P-channel transistor is a dual-purpose terminal
And the source of the first N-channel transistor is
Grounded, the drain of the first P-channel transistor and the drain of the first N-channel transistor serve as a common output terminal, and the low-voltage detection circuit has a gate commonly grounded. The second N-channel transistor and the second P-channel transistor whose on-state resistance is larger than that of the second N-channel transistor and the inverter serving as the output terminal, and the source of the second N-channel transistor is the dual-purpose terminal. is connected, the source of the second P-channel transistor is connected to the power supply voltage, the input of the inverter Dre of the second N-channel transistor
Drain of the emission and the second P-channel transistor are commonly connected, logic means, negative logical product of the outputs of the high voltage detection circuit and a low-voltage detection circuit is inputted, calculates these NAND It may be composed of a circuit and an inverter that inverts the output of the NAND circuit.

[0013]

With the above-described structure, when a voltage higher than the power supply voltage is applied to each of the dual-purpose terminals of the LSI, the high voltage detection circuit outputs a first detection signal to that effect, and the low voltage detection circuit operates. A second detection signal indicating that is output. First
And when the second detection signal is output, the logical product of both signals output by the logic means is calculated. As a result, no test mode transition signal is output from the logic means, and the LSI continues to maintain the normal operation mode.

In the malfunction prevention test circuit, the test mode transition signal is output from the logic means only when the high voltage detection circuit detects a voltage higher than the power supply voltage and the low voltage detection circuit detects a voltage lower than the ground level. Is output,
The operating state of the LSI shifts from the normal operation mode to the non-normal operation mode.

As described above, in the present invention, two different voltage applications are set as conditions for shifting to the test mode. External noise and the like are applied to the dual-purpose terminals, so that malfunction due to external noise does not occur.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a malfunction prevention test circuit according to a first embodiment of the present invention.

The malfunction prevention test circuit of this embodiment is composed of two normal operation mode circuits and two non-normal operation mode circuits. One of the normal operation mode circuits includes a terminal 101 to which a power supply voltage is supplied via a resistor 119 inserted in series with respect to the power supply voltage and a capacitor 120 whose one end is grounded, and a terminal 101 connected in series to the terminal 101. And an inverter 102, which is an input circuit. Another one
One is composed of a terminal 108 to which a power supply voltage is supplied via a resistor 121 which is inserted in series with respect to the power supply voltage and a capacitor 122 whose one end is grounded, and an inverter 102 which is connected in series to the terminal 108. Input circuit.

The non-normal operation mode circuit is composed of two detection circuits, a high voltage detection circuit 123 and a low voltage detection circuit 124, which differ in the method of detecting the abnormal operation state. The high-voltage detection circuit 123 is composed of a P-channel transistor 104 and an N-channel transistor 105 whose gate input voltage is the power supply voltage, and inverters 106 and 107. The low voltage detection circuit 124 is composed of an N-channel transistor 111, a P-channel transistor 112 whose gate input voltage is at the ground level, and inverters 113, 114, 115.

The sources of the P-channel transistor 104 and the N-channel transistor 111 each have a dual-purpose terminal 1.
01, the dual-purpose terminal 108 , and the drains are connected to the drains of the N-channel transistor 105 and the P-channel transistor 112, respectively. The source of the N-channel transistor 105 is grounded, and the source of the P-channel transistor 112 is connected to the power supply voltage.
It The inverters 106 and 107 are connected in series, and the input terminal of the inverter 106 is the P-channel transistor 104.
Is connected to the drain side (drain side of the N-channel transistor 105), the output terminal of the inverter 107 NAN
It is connected to one input terminal of the D circuit 116. The inverters 113, 114, and 115 are connected in series, and the input terminal of the inverter 113 is connected to the drain side of the N-channel transistor 111 (P-channel transistor 112).
Of the NAND circuit 116, and the output terminal of the inverter 115 is connected to the other input terminal of the NAND circuit 116.

In the malfunction prevention test circuit, the output from the inverter 102 is the normal operation mode signal 103, and the output from the inverter 109 is the normal operation mode signal 110.
The output from the inverter 117 is the abnormal operation mode signal 1
Eighteen.

Further, in the above-mentioned non-normal operation mode circuit,
By the NAND circuit 116 and the inverter 117,
The logical product of the outputs of the high voltage detection circuit 123 and the low voltage detection circuit 124 is obtained.

In the high voltage detection circuit 123, when a voltage higher than the power supply voltage is applied to the terminal 101, P
The channel transistor 104 and the N-channel transistor 105 are turned on, and the on-state resistance of the N-channel transistor 105 is changed to the P-channel transistor 10.
A high level signal is output because the resistance is set to be larger than the on-state resistance of No. 4. In the low voltage detection circuit 124, the N-channel transistor 111 and the P-channel transistor 112 are turned on when a voltage lower than the ground level is applied to the terminal 108, and the resistance of the P-channel transistor 112 in the on-state is N-channel. A high level signal is output because the resistance of the transistor 111 is set to be larger than the on-state resistance of the transistor 111.

When the malfunction prevention test circuit is in the normal operation mode, the normal operation mode signals 103 and 110 become high level or low level, and the non-normal operation mode signal 1
17 is low level. Here, when noise having the same phase as the power supply voltage flows from the outside, the voltage applied to the terminals 101 and 108 becomes higher than the power supply voltage.
Then, the high voltage detection circuit 123 outputs a high level signal and the low voltage detection circuit 124 outputs a low level signal. The signals output from both the detection circuits are ANDed by the NAND circuit 116 and the inverter 117 to obtain two output signals. As a result, the non-normal operation mode signal 118 becomes low level.

In the malfunction prevention test circuit, the terminal 10
Only when 1 becomes higher than the power supply voltage and the terminal 108 becomes lower than the ground level, the non-normal operation mode signal 118 becomes high level, and the operation mode of the LSI changes from the normal operation mode to the non-normal operation mode. Will be moved to.

FIG. 2 is a circuit diagram showing a malfunction prevention test circuit according to the second embodiment of the present invention.

This malfunction prevention test circuit is the same circuit as the malfunction prevention test circuit of the first embodiment except that the P-channel transistor 112 of the low voltage detection circuit 124 of FIG. 1 is replaced by the resistor 312.

In the malfunction prevention test circuit, the resistor 312 is set to be larger than the on-state resistor of the N-channel transistor 211.

Also in the malfunction prevention test circuit, as in the malfunction prevention test circuit of the first embodiment, the terminal 301
Becomes higher than the power supply voltage and the terminal 308 becomes lower than the ground level, the non-normal operation mode signal 318 becomes high level.

In this embodiment, the signals output from the two detection circuits are NANDed by the NAND circuit and the output is inverted by the inverter. Instead of this, an AND circuit is used. You can take the logical product with

[0031]

As described above, if the malfunction prevention test circuit of the present invention is used, the detection of the non-normal operation state at the two shared terminals is performed by detecting the high voltage at one terminal by using the high voltage detection circuit. At the other terminal, a low voltage detecting circuit is used to detect a low voltage. Therefore, even if noise with a voltage higher than the power supply voltage flows into each terminal from the outside, the state of the terminal is not erroneously detected as an abnormal operating state, and malfunction due to noise flowing from the outside can be prevented. This has the effect of improving the reliability of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a malfunction prevention test circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a malfunction prevention test circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional malfunction prevention test circuit.

[Explanation of symbols]

101, 108, 201, 208, 301, 308 Terminals 102, 106, 107, 109, 113, 114, 1
15, 117, 202, 206, 207, 213, 21
4, 215, 217, 302, 306, 307, 30
9, 313, 314, 316 Inverters 103, 110, 203, 210, 303, 310 Normal operation mode signals 104, 112, 204, 304, 311 P-channel transistors 105, 111, 205, 211, 305, 312 N
Channel transistors 116, 216, 315 NAND circuits 118, 218, 317 Non-normal operation mode signals 119, 121, 212, 219, 221, 318, 3
20 resistors 120, 122, 220, 222, 319, 321 capacitors 123, 223, 331, 332 high voltage detection circuits 124, 224, low voltage detection circuits

Claims (2)

(57) [Claims] 1. A malfunction prevention test circuit having a plurality of dual-purpose terminals for a normal operation mode and a non-normal operation mode, and detecting a state of each dual-purpose terminal to generate a test mode transition signal, wherein at least each of the dual-purpose terminals is provided. A high voltage detection circuit connected to one and outputting a first detection signal indicating that a positive voltage of a first predetermined value or more is applied to the dual-purpose terminal, and the high voltage detection circuit is connected. A low-voltage detection circuit that is connected to a dual-purpose terminal different from the dual-purpose terminal and outputs a second detection signal indicating that a negative voltage of a second predetermined value or less is applied to the dual-purpose terminal; A malfunction prevention test circuit comprising: a voltage detection circuit and a logic means for outputting a logical product of the first and second detection signals respectively output by the low voltage detection circuit as the test mode transition signal. 2. The malfunction prevention test circuit according to claim 1, wherein the high-voltage detection circuit has a first P-channel transistor whose gate is commonly connected to the power supply voltage and a resistance in the ON state. The source of the first P-channel transistor is connected to the dual-purpose terminal, the source of the first N-channel transistor is grounded, and the source of the first P-channel transistor is grounded. Of channel transistor
The drain and the drain of the first N-channel transistor are set as a common output terminal, and the low-voltage detection circuit includes a second N-channel transistor having a gate commonly grounded and a resistor in an on-state.
A second P-channel transistor larger than that of the N-channel transistor and an inverter serving as an output terminal, the source of the second N-channel transistor is connected to the shared terminal, and the source of the second P-channel transistor is The drain of the second N-channel transistor and the drain of the second P-channel transistor are commonly connected to the input of the inverter connected to the power supply voltage, and the logic means is configured to connect the high voltage detection circuit and the low voltage. Malfunction preventing test circuit, which is configured by a NAND circuit that inputs each output of the detection circuit and calculates a NAND of these outputs, and an inverter that inverts the output of the NAND circuit .