JPH08307217A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To prevent malfunction due to fluctuation in a power supply voltage of the semiconductor integrated circuit device. CONSTITUTION: Assuming that a ground potential GND rises by the effect of external noise or the like when an 'H' level is received by an input terminal 1, an 'L' level is applied apparently to a node N1, resulting that a logic level of a nose N2 goes to an 'L' level. Since the nodes N1, N2 are respectively connected to each input terminal of a NAND circuit 11, an 'H' level is outputted to a noninverting interrupt signal input terminal A of an input switch 5 receiving an 'L' level of the node N2 to interrupt the input switch 5. Since a logic level of the node N2 is delayed by a delay circuit 4 and reaches an input side of the input switch 5, a latch circuit 6 holds the logic level before the ground potential GND is fluctuated. Thus, the output of an erroneous logic level to an internal circuit is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an input circuit for preventing malfunction due to fluctuations in power supply potential in an input circuit such as a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a conventional input circuit. This input circuit includes an input terminal 1 and inverters 2 and 3. The input terminal 1 for inputting the input signal IN has a P-channel type MOS transistor (hereinafter referred to as PMOS) 2a and an N-channel type MOS transistor (hereinafter referred to as NMOS) 2b in the inverter 2.
Are connected to the respective gates G. The source S of the PMOS 2a is connected to the first power supply potential VDD,
Drain D is connected to the drain D of the NMOS 2b. The source S of the NMOS 2b is connected to the ground potential GND which is the second power source potential. Furthermore, PMOS
The drain D of 2a is connected to each gate G of the PMOS 3a and the NMOS 3b in the inverter 3. PMO
The source S of S3a is connected to the power supply potential VDD,
The drain D of OS3a is connected to the drain D of NMOS3b. The source S of the NMOS 3b is connected to the ground potential GND. An output signal OUT is output from the drain D of the PMOS 3a and the drain D of the NMOS 3b. In this input circuit, for example, a high level (hereinafter, "H") such as TTL coming into the input terminal 1 is input.
Or a low level (hereinafter referred to as “L”) is inverted by the inverter 2 and further inverted by the inverter 3 so that the MOS level at the output side of the inverter 3, that is, “H” is the power supply potential VDD, “ L ″ is output as the ground potential GND.

[0003]

However, the input circuit of FIG. 2 has the following problems. FIG. 3 is a diagram for explaining a malfunction of the input circuit of FIG. 2 when the ground potential GND changes, where the vertical axis represents voltage and the horizontal axis represents time. With reference to this figure, the ground potential GN
The operation of the input circuit of FIG. 2 when D changes will be described.
When the ground potential GND rises at time t when the “H” input signal IN is input due to the influence of external noise, for example, the potential difference between the power supply potential VDD and the ground potential GND becomes narrower than the normal value. , "H" input signal, this input circuit recognizes this "H" as "L" and outputs an output signal OUT having an incorrect logic level from the output side. That is, as shown in FIG. 3, the logic level of the output signal may be incorrect due to fluctuations in the ground potential GND. Although not shown, the logic level of the output signal may be erroneous due to the fluctuation of the power supply potential VDD.

[0004]

In order to solve the above-mentioned problems, a first invention is connected between a first power supply potential and a second power supply potential, and the input signal level and the first power supply potential are connected. In a semiconductor integrated circuit device including an input circuit for outputting an output signal of a logic level according to a logic level determined based on a power supply potential or a difference from the second power supply potential to an internal circuit,
The following means are provided. That is, the cutoff signal is output when the logical level of the input signal of the input circuit is compared with the logical level of the output signal of the input circuit and an output signal of a logical level not corresponding to the logical level of the input signal is output. And a delay means for delaying the output signal of the input circuit. Further, switch means for blocking the output signal of the delay means when the cutoff signal is output from the comparison means, and passing the output signal of the delay means when the cutoff signal is not output, and the switch means. Latch means for holding the output signal of the delay means that has passed through and outputting it to the internal circuit.

A second invention is connected between a first power supply potential and a second power supply potential, and is based on a difference between the level of an input signal and the first power supply potential or the second power supply potential. In the semiconductor integrated circuit device provided with the input circuit for outputting the output signal of the logic level according to the logic level determined by the above to the internal circuit, the following means are provided. That is, a monostable multivibrator that generates a pulse of a predetermined time width when the logic level of the output signal of the input circuit changes, the delay means of the first invention, and the monostable multivibrator outputs the pulse. Switch means for interrupting the output signal of the delay means while the output signal of the delay means is passed when the pulse is not being output, and the latch means of the first invention.

[0006]

According to the first invention, since the semiconductor integrated circuit device is configured as described above, the logic level of the output signal of the input circuit is held by the latch means. After that, when the first or second power supply potential fluctuates and the logic level of the output signal of the input circuit is not the level corresponding to the logic level of the input signal, the comparison means outputs the cutoff signal. At this time, this output signal is delayed by the delay means and cut off by the switch means. Therefore, it is possible to prevent the output signal of the logic level not corresponding to the logic level of the input signal from being output to the internal circuit. According to the second invention, the logic level of the output signal of the input circuit is held by the latch means. After that, when the first or second power supply potential fluctuates and the logic level of the output signal of the input circuit does not correspond to the logic level of the input signal, the monostable multivibrator outputs a cutoff signal. At this time, this output signal is delayed by the delay means and cut off by the switch means. Therefore, it is possible to prevent the output signal of the logic level not corresponding to the logic level of the input signal from being output to the internal circuit. Therefore, the above problem can be solved.

[0007]

EXAMPLES First Embodiment FIG. 1 (a), (b) is a circuit diagram of the input circuit and the comparator circuit illustrating a first embodiment of the present invention, common to conventional elements in FIG. 2 Common elements are denoted by common reference numerals. This input circuit is provided, for example, in an input section of a semiconductor integrated circuit device or the like, and includes an input terminal 1, an inverter 2, an inverter 3, a delay circuit 4, an input switch 5, a latch circuit 6, and an output terminal 7. Has been done. Input terminal 1 is node N
1 is connected to the input side of the inverter 2, and the output side of the inverter 2 is connected to the input side of the inverter 3. The inverters 2 and 3 are supplied with the first power supply potential VDD and the ground power supply GND which is the second power supply potential. The output side of the inverter 3 is connected to the input side of an input switch 5 which is a switch means via a node N2 and a delay circuit 4 which is a delay means, and the output side of the input switch 5 is an output terminal 7 via a node N3. And is connected to the input side of the inverter 6a. Input switch 5
Is composed of a transfer gate such as an FET, and cuts off the input signal when the positive phase cutoff signal input terminal A is "L" or the negative phase cutoff signal input terminal A / is "H",
It has a function of passing an input signal when the positive phase cutoff signal input terminal A is "H" or when the negative phase cutoff signal input terminal A / is "L". The output side of the inverter 6a is connected to the input side of the inverter 6b, and the output side of the inverter 6b is connected to the input side of the inverter 6a. The inverters 6a and 6b constitute a latch circuit 6 which is a latch means. The comparison circuit shown in FIG. 1B includes a 2-input NAND circuit 11. The first input terminal of the NAND circuit 11 is connected to the node N1 in FIG.
The second input terminal of the NAND circuit 11 is connected to the node N2 in FIG. The output side of the NAND circuit 11 is connected to the input side of the inverter 12, the output side of the inverter 12 is connected to the input side of the inverter 14 via the delay circuit 13, and the output side of the inverter 14 is shown in FIG.
It is connected to the reverse phase cutoff signal input terminal A / of the input switch 5 in (a). The delay time of the delay circuit 13 is as shown in FIG.
It is set to be shorter than the delay time of the delay circuit 4 therein.

FIG. 4 is a time chart for explaining the operation of FIGS. 1 (a) and 1 (b) when the ground potential GND fluctuates, in which the vertical axis represents voltage and the horizontal axis represents time. Has been. With reference to this figure, the ground potential GND
1 (a) and 1 (b) when the value fluctuates (1)
(4) will be described. (1) At time t1, “H” is input to the input terminal 1 and the node N1 is “H”. At this time, the “H” of the node N1 passes through the inverters 2 and 3 and the node N2
Becomes "H", and further, "H" at the node N3 becomes "H" at the node N3 via the delay circuit 4 and the input switch 5. The “H” of the node N3 is latched by the latch circuit 6. (2) At time t2, if the ground potential GND which is the second power supply potential of the input circuit rises due to the influence of external noise or the like, the node N1 apparently becomes “L”, and as a result, the logic level of the node N2. Becomes "L". (3) At time t3, the NAND circuit 11 receives "L" of the node N2 and "H" of the node N1 and outputs "H". The "H" output from the NAND circuit 11 is delayed by the delay circuit 13 via the inverter 12 and further inverted by the inverter 14 to become "H", which is output to the reverse phase cutoff signal input terminal A / of the input switch 5. Then, the input switch 5 is cut off. After the input switch 5 is cut off, the input switch 5
Since the logic level of the node N2 reaches the input side of the delay circuit 4 after being delayed by the delay circuit 4, the latch circuit 6 holds the logic level (that is, "H") before the ground potential GND changes. (4) At time t4, the logic level of the node N2 becomes “H” again, so that the input switch 5 is turned on and time t4.
It becomes the same state as 1. As described above, in the first embodiment, the ground potential G
When ND rises and the logic level of the node N2 does not correspond to the logic level of the input terminal 1, the logic level of the node N2 is cut off by the input switch 5, and the latch circuit 6 changes the ground potential GND to the ground potential GND. Since the logic level before being changed is held, an incorrect logic level is prevented from being output to the internal circuit.

Second Embodiment FIG. 5 is a circuit diagram of a comparison circuit showing a second embodiment of the present invention. This comparison circuit includes a 2-input NOR circuit 21. The first input terminal of the NOR circuit 21 is shown in FIG.
1 is connected to the node N1 and the second input terminal of the NOR circuit 21 is connected to the node N2 in FIG. The output side of the NOR circuit 21 is connected to the input side of the inverter 22, and the output side of the inverter 22 is connected to the delay circuit 23.
Is connected to the input side of the inverter 24, and the output side of the inverter 24 is connected to the negative-phase control signal input terminal A / of the input switch 5 in FIG. The delay circuit 2
The delay time of 3 is set shorter than the delay time of the delay circuit 4 in FIG. FIG. 6 is a time chart for explaining the operation of FIGS. 1A and 5 when the power supply potential VDD fluctuates, in which the vertical axis represents voltage and the horizontal axis represents time. Operations (1) to (4) in FIG. 1A and FIG. 5 when the power supply potential VDD fluctuates will be described with reference to this figure.

(1) At time t1, "L" is input to the input terminal 1 and the node N1 is "L". At this time, the “L” of the node N1 goes to the “L” at the node N2 via the inverters 2 and 3, and the “L” of the node N3 goes to the node N3 via the delay circuit 4 and the input switch 5. It becomes "L". The “L” of the node N3 is latched by the latch circuit 6. (2) At time t2, if the first power supply potential VDD of the input circuit drops due to the influence of external noise, etc.,
The node N1 apparently becomes "H", and as a result, the logic level of the node N2 becomes "H". (3) At time t3, the NOR circuit 21 has the node N
When it receives "H" of 2 and "L" of the node N1, it outputs "L". The “L” output from the NOR circuit 21 is delayed by the delay circuit 13 after passing through the inverter 12 and the inverter 1
The signal is inverted at 4 and becomes "L", which is output to the reverse phase cutoff signal input terminal A / of the input switch 5, and the input switch 5 is cut off. After the input switch 5 is cut off, the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4, so that the latch circuit 6 causes the ground potential GN to be reached.
The logic level (that is, "L") before D changes is retained. (4) At time t4, the logic level of the node N2 becomes “L” again, so that the input switch 5 is turned on and time t4.
It becomes the same state as 1. As described above, in the second embodiment, the power supply potential VDD
When the logic level of the node N2 falls below the level corresponding to the logic level of the input terminal 1, the logic level of the node N2 is cut off by the input switch 5, and the latch circuit 6 changes the power supply potential VDD. Since the previous logic level is retained, an incorrect logic level is prevented from being output to the internal circuit.

Third Embodiment FIG. 7 is a circuit diagram of a comparison circuit showing a third embodiment of the present invention. Elements common to those in FIGS. 1B and 5 are designated by common reference numerals. Is attached. This comparison circuit is shown in FIG.
The output side of the inverter 14 in the comparison circuit shown in (b) is connected to the first input terminal of the 2-input NOR circuit 26 via the inverter 25, and the inverter 2 in the comparison circuit shown in FIG.
4 is connected to the second input terminal of the NOR circuit 26. The output side of the NOR circuit 26 is shown in FIG.
It is connected to the reverse phase cutoff signal input terminal A / of the input switch 5 in (a). FIG. 8 is a time chart for explaining the operation of FIG. 1A and FIG. 7 when the power supply potential VDD and the ground potential GND fluctuate, in which the vertical axis represents voltage and the horizontal axis represents time. There is. Operations (1) to (9) in FIG. 1A and FIG. 7 when the power supply potential VDD and the ground potential GND are changed will be described with reference to this figure.

(1) At time t1, "L" is input to the input terminal 1 and the node N1 is "L". At this time, the “L” of the node N1 goes to the “L” at the node N2 via the inverters 2 and 3, and the “L” of the node N3 goes to the node N3 via the delay circuit 4 and the input switch 5. It becomes "L". The “L” of the node N3 is latched by the latch circuit 6. (2) At time t2, if the power supply potential VDD of the input circuit drops due to the influence of external noise or the like, the node N1 apparently becomes “H”, and as a result, the logic level of the node N2 becomes “H”. (3) At time t3, since the input terminals of the NOR circuit 21 are connected to the node N1 and the node N2, respectively, the negative phase cutoff signal input terminal A / of the input switch 5 is received by receiving "H" of the node N2. "H" is output to and the input switch 5 is shut off. After the input switch 5 is cut off, the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4, so that the logic level before the ground potential GND changes in the latch circuit 6. (That is,
"L") is held. (4) At time t4, the logic level of the node N2 becomes “L” again, so that the input switch 5 is turned on and time t4.
It becomes the same state as 1. (5) At time t5, until “H” is input to the input terminal 1 and the logic level of the node N2 becomes “H”,
"H" is output to the reverse phase cutoff signal input terminal A / and the input switch 5 is cut off.

(6) At time t6, "H" is input to the input terminal 1 and the node N1 is at "H". At this time, "H" of the node N1 becomes "H" at the node N2 via the inverters 2 and 3, and "H" of the node N3 becomes at the node N3 via the delay circuit 4 and the input switch 5. It becomes "H". The “H” of the node N3 is latched by the latch circuit 6. (7) At time t7, if the ground potential GND, which is the second power supply potential of the input circuit, rises due to the influence of external noise or the like, the node N1 apparently becomes “L”, and as a result, the logic level of the node N2. Becomes "L". (8) At time t8, since the input terminals of the NAND circuit 11 are connected to the node N1 and the node N2, respectively, the negative phase cutoff signal input terminal A / of the input switch 5 is received by receiving "L" of the node N2. "H" is output to and the input switch 5 is shut off. After the input switch 5 is cut off, the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4, so that the logic level before the ground potential GND changes in the latch circuit 6. (That is,
"H") is held. (9) At time t9, the logic level of the node N2 becomes “H” again, so that the input switch 5 is turned on and time t.
It becomes the same state as 6. As described above, in the third embodiment, the ground potential G
When ND rises and the logic level of the node N2 no longer corresponds to the logic level of the input terminal 1, or when the power supply potential VDD falls and the logic level of the node N2 corresponds to the logic level of the input terminal 1. If it disappears, the logic level of the node N2 is cut off by the input switch 5, and the latch circuit 6 holds the logic level before the power supply potential VDD fluctuates, so that an erroneous logic level is output to the internal circuit. Is prevented.

Fourth Embodiment FIG. 9 is a circuit diagram of a comparison circuit showing a fourth embodiment of the present invention. This comparison circuit includes a 2-input NAND circuit 31. The first input terminal of the NAND circuit 31 is shown in FIG.
The NAND circuit 31 connected to the node N1 in FIG.
The second input terminal of is connected to the node N2 in FIG. The output side of the NAND circuit 31 has a 2-input NAN.
It is connected to the first input terminal of the D circuit 32. The comparison circuit also includes a 2-input NOR circuit 33. N
The first input terminal of the OR circuit 34 is connected to the node N1 in FIG. 1A, and the second input terminal of the NOR circuit 34 is connected to the node N2 in FIG. 1A. NOR
The output side of the circuit 33 is NANDed through the inverter 34.
It is connected to the second input terminal of the circuit 32. NAND
The output side of the circuit 32 is connected to the positive phase control signal input terminal A of the input switch 4 in FIG. Figure 10
10 is a time chart for explaining the operation of FIG. 1A and FIG. 9 when the power supply potential VDD and the ground potential GND fluctuate, in which the vertical axis represents voltage and the horizontal axis represents time. Operations (1) to (9) in FIG. 1A and FIG. 9 when the power supply potential VDD and the ground potential GND are changed will be described with reference to this figure.

(1) At time t1, "L" is input to the input terminal 1 and the node N1 is "L". At this time, the “L” of the node N1 goes to the “L” at the node N2 via the inverters 2 and 3, and the “L” of the node N3 goes to the node N3 via the delay circuit 4 and the input switch 5. It becomes "L". The “L” of the node N3 is latched by the latch circuit 6. (2) At time t2, if the first power supply potential VDD of the input circuit drops due to the influence of external noise, etc.,
The node N1 apparently becomes "H", and as a result, the logic level of the node N2 becomes "H". (3) At time t3, the NOR circuit 21 of the comparison circuit
Since the respective input terminals of are connected to the node N1 and the node N2 respectively, "L" is output to the positive phase cutoff signal input terminal A of the input switch 5 in response to the "H" of the node N2 and the input switching is performed. The vessel 5 is shut off. Since the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4 after the input switch 5 is cut off, the latch circuit 6
Holds the logic level (that is, "L") before the ground potential GND fluctuates. (4) At time t4, the logic level of the node N2 becomes “L” again, so that the input switch 5 is turned on and time t4.
It becomes the same state as 1. (5) At time t5, until “H” is input to the input terminal 1 and the logic level of the node N2 becomes “H”,
"L" is output to the positive-phase / negative-phase cutoff signal input terminal A, and the input switch 5 is cut off.

(6) At time t6, "H" is input to the input terminal 1 and the node N1 is at "H". At this time, "H" of the node N1 becomes "H" at the node N2 via the inverters 2 and 3, and "H" of the node N3 becomes at the node N3 via the delay circuit 4 and the input switch 5. It becomes "H". The “H” of the node N3 is latched by the latch circuit 6. (7) At time t7, if the ground potential GND, which is the second power supply potential of the input circuit, rises due to the influence of external noise or the like, the node N1 apparently becomes “L”, and as a result, the logic level of the node N2. Becomes "L". (8) At time t8, the input terminals of the NAND circuit 11 are connected to the node N1 and the node N2, respectively, so that the positive phase cutoff signal input terminal A of the input switch 5 is received by receiving "L" of the node N2. "L" is output and the input switch 5 is shut off. Since the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4 after the input switch 5 is cut off, the logic level before the ground potential GND changes in the latch circuit 6. (That is,
"H") is held. (9) At time t9, the logic level of the node N2 becomes “H” again, so that the input switch 5 is turned on and time t.
It becomes the same state as 6. As described above, in the fourth embodiment, the same advantages as those of the third embodiment can be obtained by using the comparison circuit composed of relatively fewer elements than the comparison circuit of FIG.

Fifth Embodiment FIG. 11 is a circuit diagram of a monostable multivibrator showing a fifth embodiment of the present invention. The monostable multivibrator includes an inverter 41. Inverter 41
1 is connected to the node N2 in FIG. 1 (a), the output side of the inverter 41 is connected to the input side of the inverter 42, and the reverse phase cutoff signal input terminal A / of the input switch 43 and the input It is connected to the positive phase cutoff signal input terminal A of the switch 44. The input side of the inverter 41 is connected to the input side of the inverter 45, and is also connected to the positive phase cutoff signal input terminal A of the input switch 43 and the negative phase cutoff signal input terminal A / of the input switch 44. The output side of the inverter 42 is connected to the input side of the input switch 43 via the delay circuit 46, and the output side of the inverter 45 is connected to the input side of the input switch 44 via the delay circuit 47. The output sides of the input switches 43 and 44 are both connected to the input side of the inverter 48, and the output side of the inverter 48 is shown in FIG.
It is connected to the positive phase cutoff signal input terminal A of the input switch 5 in (a). The delay times of the delay circuits 46 and 47 are set shorter than the delay time of the delay circuit 4 in FIG. FIG. 12 shows the power supply potential VDD and the ground potential G.
FIG. 12 is a time chart for explaining the operation of FIG. 1A and FIG. 11 when the ND changes, where the vertical axis represents voltage and the horizontal axis represents time. FIG. 1 in the case where the power supply potential VDD and the ground potential GND fluctuate with reference to FIG.
The operations (1) to (9) in (a) and FIG. 11 will be described.

(1) At time t1, "L" is input to the input terminal 1 and the node N1 is "L". At this time, the “L” of the node N1 goes to the “L” at the node N2 via the inverters 2 and 3, and the “L” of the node N3 goes to the node N3 via the delay circuit 4 and the input switch 5. It becomes "L". The “L” of the node N3 is latched by the latch circuit 6. (2) At time t2, if the first power supply potential VDD of the input circuit drops due to the influence of external noise, etc.,
The node N1 apparently becomes "H", and as a result, the logic level of the node N2 becomes "H". (3) At time t3, since the input side of the inverter 41 is connected to the node N2, “H” of the node N2
In response to this, the input switch 43 is turned on, and "L" is output to the positive phase cutoff signal input terminal A of the input switch 5 to cut off the input switch 5. After the input switch 5 is cut off, the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4, so that the logic level before the ground potential GND changes in the latch circuit 6. (That is,
"L") is held. (4) At time t4, the logic level of the node N2 becomes “L” again, so that the input switch 5 is turned on and time t4.
It becomes the same state as 1. (5) At time t5, when "H" is input to the input terminal 1 and the logic level of the node N2 becomes "H", "L" is output to the positive phase cutoff signal input terminal A and the input switch. 5
Is cut off, the “H” of the node N3 at time t4 is held.

(6) At time t6, "H" is input to the input terminal 1 and the node N1 is at "H". At this time, "H" of the node N1 becomes "H" at the node N2 via the inverters 2 and 3, and "H" of the node N3 becomes at the node N3 via the delay circuit 4 and the input switch 5. It becomes "H". The “H” of the node N3 is latched by the latch circuit 6. (7) At time t7, if the ground potential GND, which is the second power supply potential of the input circuit, rises due to the influence of external noise or the like, an apparent “L” is applied to the node N1, and as a result, the node N2 The logic level becomes "L". (8) At time t8, since the input side of the inverter 45 is connected to the node N2, “L” of the node N2.
In response to this, the input switch 44 is turned on, "L" is output to the positive phase cutoff signal input terminal A of the input switch 5, and the input switch 5 is cut off. After the input switch 5 is cut off, the logic level of the node N2 reaches the input side of the input switch 5 after being delayed by the delay circuit 4, so that the logic level before the ground potential GND changes in the latch circuit 6. (That is,
"H") is held. (9) At time t9, the logic level of the node N2 becomes “H” again, so that the input switch 5 is turned on and time t.
It becomes the same state as 6. As described above, in the fifth embodiment, when the logic level of the output signal of the input circuit changes, the monostable multivibrator that generates a pulse of a predetermined time width is used, which is similar to the third embodiment. Benefits are obtained. The present invention is applicable not only to semiconductor integrated circuit devices but to electronic circuits in general.

[0020]

As described in detail above, according to the first aspect of the present invention, the comparing means compares the logic level of the input signal of the input circuit with the logic level of the output signal of the input circuit to input the input signal. The output signal of the logic level not corresponding to the logic level is output, the delay means delays the output signal of the input circuit, the switch means outputs the cutoff signal from the comparison means. The output signal of the delay means is blocked when the output signal of the delay means is passed, the output signal of the delay means is passed when the cutoff signal is not output, and the output signal of the delay means passed through the switch means is held by the latch means. Since the output signal is output to the internal circuit, it is possible to prevent the output signal of the logic level which does not correspond to the logic level of the input signal from being output to the internal circuit due to the fluctuation of the first or second power supply potential. That. According to the second invention, the monostable multivibrator generates a pulse having a predetermined time width when the logical level of the output signal of the input circuit changes, the delay means delays the output signal of the input circuit, and the switch means. Shuts off the output signal of the delay means when the pulse is output from the monostable multivibrator, passes the output signal of the delay means when the pulse is not output, and the latch means passes the switch means. Since the output signal of the delay means is held and output to the internal circuit, the logic level does not correspond to the logic level of the input signal due to the fluctuation of the first or second power supply potential, as in the first invention. It is possible to prevent the output signal of 1 from being output to the internal circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input circuit and a comparison circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional input circuit.

FIG. 3 is a diagram illustrating a malfunction of FIG.

FIG. 4 is a time chart of FIGS. 1 (a) and 1 (b).

FIG. 5 is a circuit diagram of a comparison circuit according to a second embodiment of the present invention.

FIG. 6 is a time chart of FIGS. 1A and 5.

FIG. 7 is a circuit diagram of a comparison circuit according to a third embodiment of the present invention.

FIG. 8 is a time chart of FIGS. 1A and 7.

FIG. 9 is a circuit diagram of a comparison circuit according to a fourth embodiment of the present invention.

FIG. 10 is a time chart of FIGS. 1A and 9.

FIG. 11 is a circuit diagram of a monostable multivibrator according to a fifth embodiment of the present invention.

FIG. 12 is a time chart of FIGS. 1A and 11.

[Explanation of symbols]

2, 3, 12, 14, 22, 24, 26, 34, 41,
42, 45, 46 Inverter 4 Delay circuit (delay means) 5, 43, 44 Input switch (switch means) 6 Latch circuit (latch means) 11, 25, 31, 32 NAN
D circuit 21, 33 NOR
circuit

Claims (2)

[Claims] 1. It is connected between a first power supply potential and a second power supply potential and is determined based on a difference between the level of an input signal and the first power supply potential or the second power supply potential. In a semiconductor integrated circuit device having an input circuit for outputting an output signal of a logic level according to a logic level to an internal circuit, the logic level of the input signal of the input circuit is compared with the logic level of the output signal of the input circuit. Comparing means for outputting an interruption signal when an output signal of a logical level not corresponding to the logical level of the input signal is outputted, delay means for delaying an output signal of the input circuit, and the interruption signal from the comparing means. Switch means for blocking the output signal of the delay means when the output signal is output, and for passing the output signal of the delay means when the cutoff signal is not output; A latch means for holding and outputting an output signal of the extending means to the internal circuit, the semiconductor integrated circuit device, characterized in that provided. 2. It is connected between a first power supply potential and a second power supply potential and is determined based on a difference between the level of an input signal and the first power supply potential or the second power supply potential. In a semiconductor integrated circuit device having an input circuit for outputting an output signal of a logic level according to a logic level to an internal circuit, a pulse having a predetermined time width is generated when the logic level of the output signal of the input circuit changes. A monostable multivibrator, a delay unit according to claim 1, and an output signal of the delay unit being cut off when the monostable multivibrator is outputting the pulse, and the delay unit being not outputting the pulse. 2. A semiconductor integrated circuit device, comprising: switch means for allowing the output signal of 1. to pass; and latch means according to claim 1.