KR100290892B1 - Complementary metal oxide semiconductor voltage level shift circuit - Google Patents

Abstract

PURPOSE: CMOS voltage level shift circuit is provided to reduce a power and a chip area by using a pull-up transistor and a pull-down transistor when an output node is abruptly pulled up or down. CONSTITUTION: CMOS level shift circuit includes a level shift circuit(40) for outputting a pull-up signal and a pull-down signal after receiving an input signal, and a correction edge detection circuit(50) for generating a pull-up edge detection signal and a pull-down detection signal at the same time. The level shift circuit(40) includes a first transistor(41) having two PMOS transistors, a second transistor(42) having two NMOS transistors, a third transistor(43) having two PMOS transistors and a fourth transistor(44) having two NMOS transistors. PMOS transistors of the first transistor(41) receive an input signal at gate terminals, commonly connect source terminals to a ground terminal, and commonly connect drain terminals to an output terminal. NMOS transistors of the second transistor(42) commonly connect drain terminals to an output terminal, and commonly connect source terminals to a power voltage. PMOS transistors of the third transistor(43) receive an inverted signal at gate terminals, commonly connect source terminals to a ground terminal, and commonly connect drain terminals to an output terminal. NMOS transistors of the fourth transistor(44) commonly connect drain terminals to an output terminal, and commonly connect source terminals to a power voltage.

Description

CMOS voltage level shift circuit {COMPLEMENTARY METAL OXIDE SEMICONDUCTOR VOLTAGE LEVEL SHIFT CIRCUIT}

The present invention relates to a CMOS voltage level shift circuit, in particular to reduce the transition time when the output node has to be pulled up or pulled down rapidly. A suitable CMOS voltage level shift circuit is disclosed.

In general, a fast transition when a switching action occurs will result in an output signal that does not have a value in an unclear region.

Therefore, the level shift circuit switches a low voltage signal to a large voltage region so that noise outside the logic high or logic low in the digital logic system is reduced. It is used to have no) value or errors signal value.

Hereinafter, a conventional CMOS voltage level shift circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram showing a conventional CMOS voltage level shift circuit.

As shown in FIG. 1, a pull-up transistor 10 receiving an input signal IN and outputting an active pull-up signal, and a signal opposite to the input signal ( A pull-down transistor 20 for receiving an active pull-down signal and a level change of an input signal and an opposite signal between the input signal and the rising and falling edges And a detection unit 30 for detecting a falling edge.

Meanwhile, the pull-up transistor 10 includes a first NMOS transistor 11 having an input signal applied to a gate, a drain terminal grounded, and an output terminal connected to a source terminal, and the first NMOS transistor ( 11) a first transistor 12 consisting of two NMOS transistors having a common drain terminal connected to the output terminal and a source terminal commonly connected to a power supply voltage, and a signal opposite to the input signal applied to the gate, A second NMOS transistor 13 having a ground terminal connected and an output terminal connected to a source terminal, a gate connected to an output terminal of the first transistor 12, a source terminal connected to a power supply voltage in common, and a drain terminal connected in common It consists of a second transistor 14 consisting of two NMOS transistors connected to the output terminal of the second NMOS transistor 13.

Here, an output terminal of the first transistor 12 and the first NMOS transistor 11 and a gate of one side of the second transistor 14 are connected, and an output terminal of the second transistor 14 and the second NMOS transistor 13 The gate of one side of the first transistor 12 is connected.

Subsequently, the pull-down transistor 20 includes a third NMOS transistor 15 having a gate connected to an output terminal of the second NMOS transistor 13, a power supply voltage connected to a source terminal, and an output terminal connected to a drain terminal; A third transistor 16 including two PMOS transistors having a drain terminal commonly connected to an output terminal of the third NMOS transistor 15 and a source terminal commonly connected to a ground terminal, and the first NMOS transistor 11 A fourth NMOS transistor 17 having a gate of one side connected to an output terminal of the source terminal, a power supply voltage connected to a source terminal, and an output terminal connected to a drain terminal thereof, and a drain terminal connected to the output terminal of the fourth NMOS transistor 17 in common And a source transistor having a fourth transistor 18 composed of two PMOS transistors commonly connected to the ground terminal.

Here, the output terminal of the third NMOS transistor 15 and the gate of the other side of the fourth transistor 18 are connected, and the output terminal of the fourth NMOS transistor 17 and the gate of the other side of the third transistor 16 are connected.

Subsequently, the detection unit 30 receives the output signals and the first signals of the fourth NMOS transistor 17 and the fourth transistor 18 and performs a logic operation on the first NAND gate 19 to output a second signal, The second NAND gate 21 which receives the output signals of the third NMOS transistor 15 and the third transistor 16 and the second signal of the first NAND gate 19 and performs a logic operation to output the first signal. And a third NAND gate 22 which receives the output signals and the second signal of the fourth NMOS transistor 17 and the fourth transistor 18 and performs a logic operation to output a third signal, and the third NMOS transistor. And a fourth NAND gate 23 that receives the output signal of the third transistor 16 and the first signal and performs a logic operation to output the fourth signal.

The third signal is a signal inverted by the first inverter 24 is applied to the gate of the third transistor 16, the fourth signal is a signal inverted by the second inverter 25 is the fourth transistor Is applied to the gate of (18).

The operation of the conventional CMOS voltage level shift circuit constructed as described above is as follows.

First, when the input signal IN transitions from ″ Low ″ to ″ High ″, Node B becomes ″ 1 ″ and the fourth transistor 18 is turned off. The node A becomes ″ 0 ″ and the first transistor 14 is turned ON.

As a result, the first transistor 12 is turned off, and the node C becomes ″ 0 ″, so that ″ 1 ″ is output as the output signal Out. At this time, the pull-up transistor 10 and the pull-down transistor 20 are boosted by the detector 30 so as to be able to transition from ″ 0 ″ to ″ 1 ″ faster.

In addition, when the input signal transitions from "High" to "Low", the opposite phenomenon occurs and the output signal is set to "0".

However, in the conventional CMOS voltage level shift circuit as described above, the pull-up transistor and the pull-down transistor are respectively used to process the pull-up signal and the pull-down signal when the output node is suddenly pulled up or pulled down. By constructing and using it, there was a problem in that additional hardware was added and chip area was increased.

The present invention has been made to solve the above problems, CMOS voltage level to reduce the power and chip area by processing the pull-up and pull-down signals separately when the output node is suddenly pulled up or pulled down The purpose is to provide a shift circuit.

1 is a circuit diagram showing a conventional CMOS voltage level shift circuit

2 is a circuit diagram showing a CMOS voltage level shift circuit according to the present invention.

3 is a block diagram illustrating a modified edge detection circuit of FIG. 2.

4 is a timing diagram of the crystal edge detection circuit of FIG.

5 is a timing diagram illustrating input and output of a CMOS voltage level shift circuit according to the present invention.

Explanation of symbols for main parts of the drawings

40: level shift circuit 50: crystal edge detection circuit

The CMOS voltage level shift circuit according to the present invention for achieving the above object is a CMOS level shift circuit to reduce the transition time when the output node is to be pulled up or pulled down rapidly, by receiving the input signal pull A level shift circuit for outputting up- and pull-down signals, and a modified edge detection circuit for simultaneously generating pull-up edge detection signals and pull-down edge detection signals.

Hereinafter, a CMOS voltage level shift circuit according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing a CMOS voltage level shift circuit according to the present invention.

As shown in FIG. 2, the input signal IN, ), And a level shift circuit 40 for outputting pull-up and pull-down signals, and a crystal edge detection circuit 50 for simultaneously generating pull-up edge detection signals and pull-down edge detection signals. It is composed.

The level shift circuit 40 may include a first transistor including two PMOS transistors in which an input signal IN is applied to a gate of one side, a source terminal is commonly connected to a ground terminal, and a drain terminal is commonly connected to an output terminal. 41, a second transistor 42 consisting of two NMOS transistors having a drain terminal commonly connected to an output terminal of the first transistor 41 and a source terminal commonly connected to a power supply voltage, and an input to a gate of one side; A third transistor 43 consisting of two PMOS transistors having the opposite signal applied thereto, a source terminal connected to the ground terminal in common, and a drain terminal connected to the output terminal, and a drain at the output terminal of the third transistor 43. Fourth transistor consisting of two NMOS transistors whose terminals are commonly connected and the source terminals are commonly connected to the supply voltage. It consists of the master 44.

Meanwhile, a gate of one side of the first transistor 41 and an output terminal of the third transistor 43 and the fourth transistor 44 are connected, and a gate of one side of the third transistor 43 and the first transistor 41. And an output terminal of the second transistor 42 is connected.

The crystal edge detection circuit 50 includes a first inverter 45 for inverting the output signals of the third transistor 43 and the fourth transistor 44, and a signal inverted by the first inverter 45. And a first NAND gate 46 for receiving a first signal and performing a logic operation to output a second signal, and a second inverter 47 for inverting the output signals of the first transistor 41 and the second transistor 42. ), A second NAND gate 48 for receiving the inverted signal and the second signal of the second inverter 47 and performing a logic operation to output the first signal, and the third transistor 43 and the fourth transistor. A third NAND gate 49 which receives the output signal of the 44 and the second signal and performs a logical operation to output the third signal, and output signals of the first transistor 41 and the second transistor 42 and the third signal; A fourth NAND gate 51 which receives one signal and performs a logical operation to output a fourth signal; A third inverter 52 that receives and inverts the third signal of the third NAND gate 49 and outputs a fifth signal, and receives and inverts the fourth signal of the fourth NAND NAND gate 51. And a fourth inverter 53 for outputting a signal.

Here, the fifth signal of the third inverter 52 is applied to the gate of the other side of the second transistor 42, and the sixth signal of the fourth inverter 53 is applied to the gate of the other side of the fourth transistor 44. .

In addition, the third signal of the third NAND gate 49 is applied to the gate of the other side of the first transistor 41, and the fourth signal of the fourth NAND gate 51 is the other side of the second transistor 42. Is applied to the gate of.

The operation of the CMOS voltage level shift circuit according to the present invention configured as described above is as follows.

3 is a block diagram illustrating the modified edge detection circuit of FIG. 2, and FIG. 4 is a timing diagram of the modified edge detection circuit of FIG. 3.

As shown in FIG. 3, the crystal edge detection circuit 50 receives two input signals a and b and outputs four output signals c, d, e, and f.

That is, as shown in FIG. 4, when the input signals of a and b are input, the negative edge of the a signal is detected to generate pulse signals such as c and e.

Where c is the signal for driving the pull-up transistor, which is ″ Low ″ only at the negative edge, and the rest is kept ″ High ″.

In addition, the e signal is a signal for driving a pull-down transistor, and becomes ″ High ″ only when a negative edge is generated, and the rest is maintained in a ″ Low ″ state.

The signal d for detecting the positive edge is a pulse signal for operating the pull-up transistor, and the signal f is a pulse signal for operating the pull-down transistor.

5 is a timing diagram illustrating input and output of a CMOS voltage level shift circuit according to the present invention.

As shown in FIG. 5, the generated edge detection circuit operates the pull-up and pull-down transistors simultaneously to have a sharp output signal out when an input signal in having a very large transition is applied.

As described above, the present invention has the following effects in the CMOS voltage level shift circuit.

First, the pull-up and pull-down can be handled separately to reduce the power and chip area generated.

Second, it can be used to drive a signal having a large loading impedance.

Claims (3)

In a CMOS level shift circuit that reduces the transition time when the output node should be pulled up or pulled down rapidly, A level shift circuit that receives an input signal and outputs pull-up and pull-down signals, and And a crystal edge detection circuit for simultaneously generating a pull-up edge detection signal and a pull-down edge detection signal. The method of claim 1, wherein the level shift circuit is A first transistor comprising two PMOS transistors having an input signal applied to a gate of one side, a source terminal of which is commonly connected to a ground terminal, and a drain terminal of which is commonly connected to an output terminal; A second transistor including two NMOS transistors having a drain terminal commonly connected to an output terminal of the first transistor and a source terminal commonly connected to a power supply voltage; A third transistor comprising two PMOS transistors having an opposite signal of an input signal applied to a gate of one side, a source terminal of which is commonly connected to a ground terminal, and a drain terminal of which is connected to an output terminal; And a fourth transistor comprising two NMOS transistors having a drain terminal commonly connected to an output terminal of the third transistor and a source terminal connected to a power supply voltage in common. 3. The crystal edge detection circuit of claim 1 or 2, wherein A first inverter for inverting output signals of the third transistor and the fourth transistor; A first NAND NAND gate that receives the inverted signal and the first signal by the first inverter and performs a logic operation to output a second signal; A second inverter for inverting output signals of the first transistor and the second transistor; A second NAND NAND gate configured to receive the inverted signal and the second signal of the second inverter and output a first signal by performing a logic operation; A third NAND NAND gate configured to receive an output signal and a second signal of the third and fourth transistors and output a third signal by performing a logic operation; A fourth NAND NAND gate configured to receive an output signal and a first signal of the first and second transistors and output a fourth signal by performing a logic operation; A third inverter receiving the third signal of the third NAND NAND gate and inverting the third signal to output a fifth signal; And a fourth inverter configured to receive a fourth signal of the fourth NAND NAND gate, invert the fourth signal, and output a sixth signal.