KR100642396B1 - Input-output Line Driving Circuit for Reduced Latency - Google Patents

Abstract

The present invention relates to an input / output line driver circuit, which drives an input / output line on an on-chip by using a driving voltage higher than an external power supply voltage, And more particularly, to an input / output line driver circuit that prevents an operation delay on an on-chip input / output line from occurring and realizes a low CAS latency even under a system environment where the length is getting longer.

I / O line driving circuit, on-chip

Description

[0001] Input-output Line Driving Circuit for Reduced Latency [             

1 shows a configuration of an input / output line driving circuit according to the prior art.

FIG. 2 shows a configuration of an input / output line driving circuit according to an embodiment of the present invention.

FIG. 3 illustrates a configuration of an input / output line driving circuit according to another embodiment of the present invention.

Description of the Related Art

110: 1st level shifter

120: Second-level shifter

210: first boot circuit part

220: Second boot circuit

221: buffer unit

The present invention relates to an input / output line driver circuit for reducing latency, and more particularly, to an input / output line driver circuit for reducing latency, and more particularly, an operation delay on an on-chip input / output line occurs even in a system environment in which an external power supply voltage gradually decreases and a wiring length on an on- Output line driving circuit for preventing a low CAS latency and preventing a low CAS latency.

Conventionally, an input / output line driver circuit, particularly an on-chip input / output line driver circuit, receives an external power supply to drive an input / output wiring on an on-chip. That is, in the conventional on-chip input / output line driving circuit, an inverter type driving circuit having three states depending on the state of an input signal is used, and the input / And the input / output line connected to the interconnection line, which is a wiring line, is driven to a high level which is an external power supply level or a low level which is a ground level.

The operation of the conventional input / output line driving circuit will be described in detail with reference to the accompanying drawings.

1 shows a configuration of an input / output line driving circuit according to the prior art. As shown in the figure, the conventional input / output line driving circuit includes a PMOS (MP) for pull-up driving an output terminal OUT to a power supply voltage (Vdd) level in response to a first input signal in1; And an NMOS (MN) responsive to the second input signal in2 to pull-down drive the output stage out to the ground (Vss) level.

In the above, the conventional input / output line driving circuit has three states (tri-states) according to the states of the first and second input signals in1 and in2. First, when the first and second input signals in1 and in2 are all at a high level, both the PMOS MP and the NMOS MN are turned off to be in a high-impedance state. When the first input signal in1 is at the low level and the second input signal in2 is at the high level, only the PMOS MP is turned on, so that the output terminal out becomes the power supply voltage Vdd level. On the other hand, when the first input signal in1 is at the high level and the second input signal in2 is at the low level, only the NMOS MN is turned on, so that the output terminal out becomes the ground Vss level.

Here, the driving voltage of the conventional input / output line driving circuit is determined by the parasitic capacitance component and the parasitic resistance component of the on-chip wiring, and the on-resistance component of the driving circuit. Assuming that the parasitic capacitance component is "CL", the parasitic resistance component is "RL" and the on-resistance component is "RS", the output voltage when the output terminal out is driven to a high level is Respectively.

The output voltage when the output terminal out is driven to a low level is as follows.

However, as the complexity of the circuit of the semiconductor device increases and the length of the wiring on the on-chip increases, the value of the parasitic resistance RL also increases and the value of the time constant RS + RL CL also increases , The driving speed of the input / output line driving circuit is significantly reduced, and an operation delay occurs on the input / output line. Further, when the value of the external power supply Vdd decreases according to the tendency of the operation power of the semiconductor device to be reduced in recent years, the operation delay phenomenon on the input / output line is further exacerbated. The increase of the input / output line operation delay phenomenon causes a problem of increasing the CAS latency of the DRAM.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method and apparatus for preventing an operation delay on an on-chip input / output line from occurring in a system environment in which an external power supply voltage gradually decreases and a wiring length on an on- And to provide an input / output line driving circuit for reducing latency.

According to an aspect of the present invention, there is provided a level shifter including: a first level shifter for level shifting a first input signal; A second level shifter for level shifting and outputting a second input signal; A pull-up driver for pulling up the output stage to a higher voltage level than the external power supply in response to a signal from the first level shifter; And a pull-down driver for pulling-down driving the output terminal in response to a signal from the second level shifter. The input / output line driving circuit for reducing latency is provided.

In the present invention, the input / output line driving circuit drives an input / output line on an on-chip.

 In the present invention, the first level shifter converts a voltage signal having a higher level than the external power supply or a signal having a ground level in response to the first input signal and outputs the signal.

In the present invention, the second level shifter converts a voltage signal of a higher level or a signal of a ground level into a signal of a higher level than the external power supply in response to the second input signal, and outputs the signal.

In the present invention, it is preferable that the pull-up driver is a PMOS device and the pull-down driver is an NMOS device.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a first boot circuit unit which operates in response to a first input signal, which is supplied with an external power supply and pumping a first voltage signal having a higher voltage level to an output terminal; A second boot circuit unit which operates in response to a second input signal and which is supplied with a ground voltage and pumped to a second voltage signal of a lower voltage level and outputs the second voltage signal to the output terminal; A pull-up driver for pulling up the output terminal to an external power supply level in response to the first input signal; And a pull-down driver for pulling-down driving the output terminal to a ground level in response to the second input signal. The present invention also provides an input / output line driving circuit for reducing latency.

In the present invention, the input / output line driving circuit drives an input / output line on an on-chip.

In the present invention, the first boot circuit unit inverts the first input signal and outputs the inverted first input signal to the first node; A pull-up element for pulling up the second node in response to a signal from the first node; A first capacitor disposed between the first node and the second node; And a first switching unit provided between the second node and the output terminal and operating in response to the first input signal.

In the present invention, the second boot circuit unit buffers the second input signal and outputs the buffered signal to a third node; A pull-down element for pulling-down driving the fourth node in response to a signal from the third node; A second capacitor provided between the third node and the fourth node; And a second switching unit provided between the fourth node and the output terminal and operating in response to the second input signal.

In the present invention, it is preferable that the pull-up driver is a PMOS device and the pull-down driver is an NMOS device.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a block diagram of an input / output line driving circuit according to a first embodiment of the present invention.

As shown in the figure, the input / output line driving circuit according to the present embodiment includes: a first level shifter 110 for level-shifting the first input signal in1; A second level shifter 120 for level shifting and outputting a second input signal in2; A PMOS MP11 for pull-up driving the output terminal OUT to a voltage level (Vdd_boot) higher than the external power supply (Vdd) in response to a signal from the first level shifter 110; And an NMOS (MN12) for pull-down driving the output terminal out in response to a signal from the second level shifter 120. [ The first level shifter 110 includes a PMOS M11 for pulling up the node A, a PMOS M12 for pulling up the node B, And an NMOS M14 for pulling-up driving the NMOS M13 and the node B to be driven. The second level shifter 120 includes a PMOS M15 for pulling up the node C, a PMOS M16 for pulling up the node D, and a pull- And an NMOS M18 for pulling-up driving the node D and an NMOS M17 for driving.

The operation of the first embodiment will now be described.

The first input signal in1 is applied to the NMOS M13 and the NMOS M14 constituting the first level shifter 110 and the second input signal in2 is applied to the NMOS M13 and NMOS M14 constituting the second level shifter 120. [ (M17) and the NMOS (M18).

First, if the first and second input signals in1 and in2 are all at a high level, the NMOS M13 is turned on and the NMOS M14 is turned off in the first level shifter 110, In the level shifter 120, the NMOS M17 is turned off and the NMOS M18 is turned on. Accordingly, in the first level shifter 110, the node A is pulled-down driven to the ground level to turn on the PMOS M12, so that the node B is pulled up to the Vdd_boot level, MP11 are turned off by applying the voltage signal of the Vdd_boot level to the gate. In the second level shifter 120, the node D is pulled-down to the ground level, and the NMOS MN11 is similarly turned off since the voltage signal of the ground level is applied to the gate. Therefore, when both of the first and second input signals in1 and in2 are at the high level, the input / output line driving circuit of this embodiment is in the high impedance state. Vdd_boot is a power supply of a higher voltage level than a general external power supply Vdd and is generated not only by a gate voltage generated through a voltage pump or the like and applied to the PMOS MP11 and the NMOS MN11, MP11).

Next, when the first input signal in1 is at a low level and the second input signal in2 is at a high level, the NMOS M13 is turned off in the first level shifter 110 and the NMOS M14 is turned off. The NMOS M17 is turned off and the NMOS M18 is turned on in the second level shifter 120. [ Accordingly, in the first level shifter 110, the node B is pulled-down to the ground level, and the PMOS MP11 receives the voltage signal of the ground level at the gate thereof and is turned on to turn the output stage out to Vdd_boot Pull-up drive to the level. In the second level shifter 120, the node D is pulled-down to the ground level, and the NMOS MN11 is turned off because the voltage signal of the ground level is applied to the gate. Therefore, when the first input signal in1 is at the low level and the second input signal in2 is at the high level, the input / output line driving circuit of the present embodiment has the output terminal out at a high level, Up drive to the higher voltage level Vdd_boot.

Then, when the first input signal in1 is at the high level and the second input signal in2 is at the low level, the NMOS M13 is turned on in the first level shifter 110 and the NMOS M14 is turned on The NMOS transistor M17 is turned on and the NMOS transistor M18 is turned off in the second level shifter 120. In this case, Therefore, in the first level shifter 110, the node A is pulled-down driven to the ground level to turn on the PMOS M12, so that the node B is pulled up to the Vdd_boot level and the PMOS MP11 Is turned off by applying the voltage signal of the Vdd_boot level to the gate. The node C is pulled down to the ground level in the second level shifter 120 to turn on the PMOS M16 so that the node D is pulled up to the Vdd_boot level and the NMOS MN11 ) Applies the voltage signal of the Vdd_boot level to the gate and is turned on to pull-down drive the output terminal out to the ground level. Therefore, when the first input signal in1 is at the high level and the second input signal in2 is at the low level, the input / output line driving circuit of the present embodiment drives the output terminal out to the ground level in a pull-down manner.

As described above, the input / output line driving circuit according to the first embodiment is configured to perform the pull-up or pull-down driving of the output terminal out in response to the first and second input signals in1 and in2, The output terminal at the time of driving can be driven to a Vdd_boot level higher than the external power supply Vdd. Therefore, the input / output line driving circuit according to the present embodiment drives the on-chip input / output line to a high operating voltage even in a system environment in which the external supply voltage gradually decreases and the wiring length on the on-chip becomes longer, The operation speed can be increased and a low CAS latency can be realized.

FIG. 3 illustrates a configuration of an input / output line driving circuit according to a second embodiment of the present invention. Referring to FIG. 3, the present invention is described as follows.

As shown in the figure, the input / output line driving circuit according to the second embodiment operates in response to the first input signal in1, receives the external power supply Vdd, and pumps the first voltage signal having a higher voltage level A first boot circuit unit 210 for outputting an output signal to an output terminal out; A second boot circuit unit 220 which operates in response to the second input signal in2 and applies the ground voltage Vss to the second voltage signal of a lower voltage level and outputs the second voltage signal to the output terminal out, ; A PMOS M21 for pulling up the output OUT to the external power supply level Vdd in response to the first input signal in1; And an NMOS M22 for pulling-down driving the output terminal OUT to the ground level Vss in response to the second input signal in2.

The first boot circuit 210 includes an inverter INV22 for inverting the first input signal IN1 and outputting the inverted first input signal IN1 to the first node E; A PMOS (M23) for pulling up the second node (F) in response to a signal from the first node (E); A first capacitor (CP) installed between the first node (E) and the second node (F); And a first switching unit X1 provided between the second node F and the output terminal OUT and operating in response to the first input signal IN1.

The second boot circuit unit 220 includes a buffer unit 221 for buffering the second input signal in2 and outputting the buffered signal to the third node G; An NMOS (M24) for pull-down driving the fourth node (H) in response to a signal from the third node (G); A second capacitor (CN) provided between the third node (G) and the fourth node (H); And a second switching unit X2 provided between the fourth node H and the output terminal OUT and operating in response to the second input signal in2.

The operation of the second embodiment will now be described.

The first input signal in1 is input to the gate of the PMOS M21, the inverter INV22 and the first switching unit X1; The second input signal is input to the gate of the NMOS M22 via the inverter INV21 and to the buffer unit 221 and the second switching unit X2, respectively.

First, if the first and second input signals in1 and in2 are all at a high level, the pull-up PMOS M21 and the pull-down NMOS M22 are turned off. The first switching unit X1 is turned off and the first node E is at the ground level Vss because the first input signal in1 is at the high level. In the first boot circuit unit 210, (M23) is turned on. Therefore, the second node F becomes the external power supply level Vdd, and the first capacitor CP is charged with the charge of Cp x Vdd (where Cp is the capacitance of the first capacitor). In the second boot circuit unit 220, since the second input signal in2 is at the high level, the second switching unit X2 is turned off, and the third node G becomes the external power supply level Vdd And turns on the NMOS M24. Therefore, the fourth node H is at the ground level (Vss), and the second capacitor CN is charged with -Cn x Vdd (where Cn is the capacitance of the second capacitor). Therefore, when the first and second input signals in1 and in2 are all at the high level, the input / output line driving circuit of the second embodiment is in a high impedance state, and the second node F and the fourth node H A predetermined charge is charged.

Next, when the first input signal in1 is at a low level and the second input signal in2 is at a high level, the potential of the first node E becomes a high level, and the PMOS M23 is turned off The potential of the second node F becomes 2Vdd in order to conserve the charge amount of the first capacitor CP. Since the first switching unit X1 is turned on, the 2Vdd voltage of the second node F is transferred to drive the output terminal OUT. At this time, the amount of drive charge is determined by the amount of charge charged in the first capacitor CP. The PMOS M21 also receives the first input signal in1 of low level and is turned on to perform pull-up operation of the output terminal out. Therefore, when the first input signal in1 transits from the high level to the low level, the output terminal out is driven first by the voltage of 2Vdd level and then the charge charged in the first capacitor CP is discharged And gradually driven to the external power supply voltage Vdd. On the other hand, since the second input signal in2 stays at a high level, the second boot circuit unit 220 maintains a state in which the charge of -Cn x Vdd is charged in the second capacitor CN. As a result, when the second input signal in2 is at the high level and the first input signal in1 is transited to the low level, the input / output line driving circuit of the second embodiment outputs the output terminal out at the full- Up operation.

Then, when the first input signal in1 is at a high level and the second input signal in2 is at a low level, the potential of the third node G becomes a low level, and the NMOS M24 is turned off The potential of the fourth node H becomes -Vdd in order to conserve the charge amount of the second capacitor CN. Since the second switching unit X2 is turned on, the -Vdd voltage of the fourth node H is transferred to drive the output terminal out. At this time, the amount of drive charge is determined by the amount of charge charged in the second capacitor CN. In addition, the NMOS M22 also receives a high level signal through the inverter INV21 and is turned on to pull-down the output terminal OUT. Accordingly, when the second input signal in2 transits from the high level to the low level, the output terminal out is driven first by the voltage of -Vdd level and then the charge charged in the second capacitor CN is discharged And gradually becomes gradually pulled-down to the ground level (Vss). On the other hand, as the first input signal in1 transitions to the high level, the first boot circuit unit 210 charges the first capacitor CP with the charge of CP x 2 Vdd. As a result, when the first input signal in1 transitions to the high level and the second input signal in2 transitions to the low level, the input / output line driving circuit of the second embodiment turns the output terminal out to the -Vdd voltage level. - It is down-driven.

As described above, the input / output line driving circuit according to the second embodiment is configured to pull-up or pull-down drive the output terminal out in response to the first and second input signals in1 and in2, It is possible to drive the output terminal at the time of driving to 2Vdd level higher than the external power supply Vdd and drive the output terminal at the -Vdd level lower than the ground potential Vss in the pull-down driving. Therefore, in the input / output line driving circuit according to the second embodiment, the on-chip input / output line can be pulled up to a higher voltage or pulled up even more in a system environment in which the external power supply voltage gradually decreases and the wiring length on the on- By pull-down driving at a low voltage, it is possible to prevent the occurrence of the operation delay, thereby increasing the operation speed and realizing the low CAS latency.

As described above, the input / output line driving circuit according to the present invention can be used for pull-up driving an input / output line on an on-chip using a driving voltage having a higher potential than an external power supply voltage, The input / output line is pulled-down driven to prevent the operation delay on the on-chip input / output line from occurring even in a system environment in which the external power supply voltage gradually decreases and the wiring length on the on- It is possible to improve the speed and realize a low CAS latency.

Claims (10)

delete delete delete delete delete A first boot circuit for operating in response to a first input signal, for pumping a first voltage signal having a voltage level higher than that of the first voltage signal, and for outputting the first voltage signal to an output terminal; A second boot circuit part which operates in response to a second input signal, receives a ground voltage, pumps the second voltage signal with a lower voltage level and outputs the second voltage signal to the output terminal; A pull-up driver for pulling up the output terminal to an external power supply level in response to the first input signal; And a pull-down driver for pulling-down driving the output terminal to a ground level in response to the second input signal. 7. The input / output line driving circuit according to claim 6, wherein the input / output line driving circuit drives an input / output line on an on-chip. 7. The apparatus according to claim 6, wherein the first boot circuit portion An inverter for inverting the first input signal and outputting the inverted first input signal to a first node; A pull-up element for pulling up the second node in response to a signal from the first node; A first capacitor disposed between the first node and the second node; And a first switching unit provided between the second node and the output terminal and operating in response to the first input signal. 7. The apparatus according to claim 6, wherein the second boot circuit portion A buffer unit for buffering the second input signal and outputting the buffered signal to a third node; A pull-down element for pulling-down driving the fourth node in response to a signal from the third node; A second capacitor provided between the third node and the fourth node; And a second switching unit provided between the fourth node and the output terminal and operating in response to the second input signal. 7. The input / output line driving circuit according to claim 6, wherein the pull-up driver is a PMOS device and the pull-down driver is an NMOS device.

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