JPH0685654A - Input/output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the input of the output of an output buffer circuit to an input buffer circuit and then to prevent the malfunctions of both buffer circuits by detecting an inactive state of the output buffer circuit and switching the input buffer circuit to an active state. CONSTITUTION:An output buffer control signal CNTA is kept at an H level even though an input buffer control signal CNTB is set at an L level. Therefore the outputs of a NAND 1 and a NOR 2 are set at L levels with an H level of an internal output signal Din and then set at H levels with an L level of the signal Din respectively. Then the outputs of an inverter 6 and the NOR 2 are set at H levels when the signal Din is kept at H and L levels in a NOR 7 since the output of the NAND 1 serves as the input of the inverter 6. Meanwhile the output of the NOR 7 is fixed at an L level and an input buffer circuit is kept inactive. Therefore the output of an output buffer circuit is never inputted to the input buffer circuit and the malfunctions of both buffer circuits can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output buffer circuit, and more particularly to an input / output buffer circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, an input / output terminal portion of a semiconductor integrated circuit is composed of a 3-state type output buffer circuit and an input buffer circuit.

The conventional input / output buffer circuit is
As shown in FIG. 5, the internal output signal Din is a 2-input NAND.
It becomes 1 input of 1 and 2 inputs NOR2, and the output buffer control signal CNTA is the other input of 2 inputs NAND1,
It becomes the input of the inverter 3, and the output of the inverter 3 becomes the other input of the 2-input NOR 2. And 2 inputs N
The output of AND1 becomes the gate input of the P-channel transistor 4 for the driver, and the output of 2-input NOR2 becomes the gate input of the N-channel transistor 5 for the driver as well.

By the way, the source of the P-channel transistor 4 is connected to the power supply potential (VDD), and the output of the 2-input NAND 1 is connected to the gate. The N-channel transistor 5 has a source connected to the ground potential (GND), a gate connected to the output of the 2-input NOR 2, and a drain commonly connected to the drain of the P-channel transistor 4 and connected to the external input / output terminal I-bar O. Here, bar O means inversion of O. The external input / output terminal I-bar O becomes one input of the 2-input NOR9, the input buffer control signal bar CNTB becomes the other input of the 2-input NOR9, and the output of the 2-input NOR9 becomes the external input signal bar I. . Here, the bar CNTB is CNT
B means inversion, and bar I means I inversion.

Next, the operation will be described with reference to the operation timing chart shown in FIG.

First, when both the output buffer control signal CNTA and the input buffer control signal bar CNTB are at the'L 'level, regardless of the value of the internal output signal Din, 2-input N
The output of the AND1 becomes the "H" level, the output of the 2-input NOR2 becomes the "L" level, both the driver P-channel transistor 4 and the N-channel transistor 5 become OFF, and the output buffer circuits (1, 2, 3, 4 and 5) are inactive (high impedance state). At this time, the 2-input NOR 9 constituting the input buffer circuit inputs the input signal from the external input / output terminal I bar O and outputs the inverted signal as the external input signal bar I.
In this state, the input buffer circuit is active. When the input buffer control signal bar CNTB changes from the “L” level to the “H” level while the output buffer control signal CNTA remains at the “L” level, the output of the 2-input NOR 9 is fixed to the “L” level to serve as an input buffer circuit. It becomes inactive.

Further, the input buffer control signal bar CNTB
When the output buffer control signal CNTA changes from “L” to “H” level while the signal is at “H” level, 2-input NAND
A signal obtained by inverting the internal output signal Din is output to the 1- and 2-input NOR2. At this time, at the input / output terminal I bar O, for example, when the internal output signal Din is at the “L” level, the outputs of the 2-input NAND 1 and the 2-input NOR 2 are both at the “H” level. Then, the driver P-channel transistor 4 is turned off, the N-channel transistor 5 is turned on, and the output buffer circuit outputs the “L” level.
Further, when the internal output signal Din is at the “H” level, the outputs of the 2-input NAND 1 and the 2-input NOR 2 are both at the “L” level, the driver P-channel transistor 4 is ON, and the N-channel transistor 5 is OFF. Then, the "H" level is output as the output buffer circuit. And the input buffer control signal bar CNTB is'H '.
The output buffer control signal CNTA remains at "H" level.
Changes from "L" level to "L" level, the output of the 2-input NAND1 is "H" level, regardless of the value of the internal output signal Din.
The output of the 2-input NOR 2 becomes “L” level, both the driver P-channel transistor 4 and the N-channel transistor 5 are turned off, and the output buffer circuit becomes inactive.

In this way, the input buffer circuit and the output buffer circuit are alternately activated to exchange data with the outside.

[0009]

Generally, the above-mentioned input / output buffer circuits are arranged near the external terminals connected to them, and the external terminals are usually arranged on the outer peripheral portion of the chip of the semiconductor integrated circuit. Further, the control signal of the input / output buffer circuit is usually generated internally because the circuit that controls a plurality of circuits normally inputs the signal from another control circuit and assembles the logic. Therefore, the wiring length of the control signal becomes long and signal delay occurs at the end.

In the semiconductor integrated circuit, the operating frequency is increasing year by year, and the access speed to the outside is increasing accordingly. As a result, the input buffer circuit and the output buffer circuit are both activated due to the delay of the control signal. Then, the output of the output buffer circuit is input to the input buffer circuit to cause a malfunction.

The object of the present invention was proposed in view of the above problems of the prior art. In the input / output buffer circuit of a semiconductor integrated circuit, the control signals of the input and output buffer circuits are signals generated by wiring. An object of the present invention is to provide an input / output buffer circuit capable of preventing a malfunction of the input buffer circuit under the influence of an output signal of the output buffer circuit due to a delay and capable of stable operation.

[0012]

According to the present invention, an input / output buffer having an output buffer circuit, a terminal connected to the output of the output buffer circuit, and an input buffer circuit connected to the terminal. In the circuit, there is obtained an input / output buffer circuit characterized by having switching means for detecting the inactive state of the output buffer circuit and switching the input buffer circuit to the active state.

Further, according to the present invention, the output buffer circuit is a three-state output buffer circuit, and the output of the output buffer circuit becomes high impedance when the output buffer circuit is in the inactive state. In the input / output buffer circuit of, the switching means is
The input state of the output buffer circuit, which makes the output of the output buffer circuit high impedance, is detected as the inactive state of the output buffer circuit, and the input buffer circuit is switched to the active state. An output buffer circuit is obtained.

[0014]

According to the present invention, the inactive state of the output buffer circuit is detected, and when the output buffer circuit enters the inactive state, the input buffer circuit is switched to the active state. Since no data is input to the buffer circuit, it is possible to prevent malfunction.

[0015]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an input / output buffer circuit according to an embodiment of the present invention.

The internal output signal Din has two inputs NAND1 and 2
It becomes one input of the input NOR2, and the output buffer control signal C
NTA becomes the other input of the 2-input NAND 1 and the input of the inverter 3, and the output of the inverter 3 is the 2-input NOR.
It is the other input of 2. The output of the 2-input NOR 2 is the gate input of the driver N-channel transistor 5,
It becomes one of the inputs of 4-input NOR7 and 2-input NAND1
The output of the P-channel transistor 4 for the driver is the same.
And the input of the inverter 6, and the output of the inverter 6 becomes one input of the 4-input NOR 7.

The source of the P-channel transistor 4 is the power supply potential (VDD), and the output of the 2-input NAND 1 is connected to the gate. The source of the N-channel transistor 5 is at ground potential (GND), and the output of the 2-input NOR 2 is connected to the gate. The drain of the N-channel transistor 5 and the drain of the P-channel transistor 4 are commonly connected to the external input / output terminal I bar O.

The 4-input NOR 7 is used as an input for 2-input NO.
The output of R2, the output of the inverter 6, the input buffer control signal bar CNTB, and the external input / output terminal I bar O are connected, and the output of the 4-input NOR 7 becomes the external input signal bar I.

Next, the operation will be described with reference to the operation timing chart shown in FIG.

First, when both the output buffer control signal CNTA and the input buffer control signal bar CNTB are at the “L” level, the 2-input N signal is output regardless of the value of the internal output signal Din.
The output of AND1 becomes "H" level, the output of 2-input NOR2 becomes "L" level, both P-channel transistor 4 and N-channel transistor 5 for the driver are turned off, and the output buffer circuit becomes inactive. At this time, the 4-input NOR 7 is connected to the output of the inverter 6 and the 2-input NO.
Since the output of R2 and the input control signal bar CNTB are both at the'L 'level, the input signal from the external input / output terminal I bar O is input and the inverted signal is output as the external input signal bar I. When the output buffer control signal CNTA remains at the “L” level and the input buffer control signal bar CNTB changes from the “L” to the “H” level, the output of the 4-input NOR 7 is fixed at the “L” level and the input buffer The circuit becomes inactive.

Further, the input buffer control signal bar CNTB
Is at'H 'level, output buffer control signal CNTA
Changes from'L 'to'H' level, 2-input NAN
A signal obtained by inverting the internal output signal Din is output to the D1 and 2-input NOR2. At this time, for example, when the internal output signal Din is at the “L” level, the input / output terminal I bar O has two inputs N.
The outputs of the AND1 and the 2-input NOR2 become the "H" level, the driver P-channel transistor 4 becomes OFF, while the N-channel transistor 5 becomes ON, and the "L" level is output as the output buffer circuit. Further, when the internal output signal Din is at the “H” level, the 2-input NA is
The outputs of the ND1 and 2-input NOR2 are both at the'L 'level, the driver P-channel transistor 4 is on, the N-channel transistor 5 is off, and the output buffer circuit is at the'H' level.

When the output buffer control signal CNTA changes from "H" to "L" level while the input buffer control signal bar CNTB remains at "H" level, the internal output signal D
Regardless of the value of in, the output of the 2-input NAND1 becomes the "H" level, the output of the 2-input NOR2 becomes the "L" level, both the driver P-channel transistor 4 and the N-channel transistor 5 are turned off, and the output The buffer circuit becomes inactive.

The basic operation is as described above,
For example, as shown in FIG. 2, the output buffer control signal CNT
When A has a waveform indicated by a dotted line due to a signal delay due to a large wiring capacitance, etc., in the conventional input / output buffer circuit,
Both the input and output buffer circuits become active, causing a malfunction in the input buffer circuit.

However, in this embodiment, the output buffer control signal CNTA is at the "H" level even if the input buffer control signal CNTB is at the "L" level.
The outputs of the 2-input NAND 1 and the 2-input NOR 2 are both at the “L” level when the internal output signal Din is at the “H” level,
When the internal output signal Din is at the “L” level, both are at the “H” level, and the output of the 2-input NAND 1 is the input of the inverter.
The output of the 2-input NOR2 becomes the "H" level when the internal output signal Din is the "L" level when the in is the "H" level, and the output of the 4-input NOR7 is the "L" level. The input buffer circuit is fixed to the level and remains inactive.

In this way, the output buffer control signal CNTA is at the'L 'level, that is, the input buffer circuit becomes active after the output buffer circuit becomes inactive, so that an erroneous signal is not input and a normal operation can be performed.

FIG. 3 is a circuit diagram of an input / output buffer circuit according to another embodiment of the present invention. The internal output signal Din becomes one input of the two-input NAND1 and the two-input NOR2, the output buffer control signal CNTA becomes the other input of the two-input NAND1, one input of the three-input NOR8 and the input of the inverter 3, and the output of the inverter 3 Is the other input of the 2-input NOR2. The output of the 2-input NAND 1 becomes the gate input of the driver P-channel transistor 4, and the output of the 2-input NOR 2 similarly becomes the gate input of the driver N-channel transistor 5.

The P-channel transistor 4 has its source connected to the power supply potential (VDD), its gate connected to the output of the 2-input NAND 1, and the N-channel transistor 5 has its source connected to the ground potential (GND) and its gate connected to the output of 2-input NOR2. , The drain forms a push-pull circuit in common with the P-channel transistor 4 and external input / output terminal I-bar O
Connect to. The 3-input NOR 8 receives the output buffer control signal CNTA and the input buffer control signal bar CNTB as inputs.
And external input / output terminal I-bar O are connected, and 3-input NOR
The output of 8 becomes the external input signal bar I.

Next, the operation will be described with reference to the operation timing chart shown in FIG.

First, when both the output buffer control signal CNTA and the input buffer control signal bar CNTB are at the “L” level, the 2-input NA is set regardless of the value of the internal output signal Din.
The output of the ND1 becomes "H" level, the output of the 2-input NOR2 becomes "L" level, both the P-channel transistor 1 and the N-channel transistor 2 for the driver are turned off, and the output buffer circuit becomes inactive.

At this time, the 3-input NOR 8 has an output buffer control signal CNTA and an input buffer control signal bar CNT.
Since B is at the'L 'level, the input signal from the external input / output terminal I bar O is input and the inverted signal is output as the external input signal bar I. When the output buffer control signal CNTA remains at the “L” level and the input buffer control signal bar CNTB changes from the “L” to the “H” level, the output of the 3-input NOR 8 is fixed to the “L” level and inactive as the input buffer circuit. It becomes the state of.

Further, when the output buffer control signal CNTA changes from "L" to "H" level while the input buffer control signal bar CNTB remains at "H" level, the 2-input NAND1
A signal obtained by inverting the internal output signal Din is output to the 2-input NOR2.

At this time, the input / output terminal I bar O has a 2-input NAN when the internal output signal Din is at the'L 'level, for example.
The output of D1 and 2-input NOR2 becomes'H 'level,
The driver P-channel transistor 4 is turned off, the N-channel transistor 5 is turned on, and an'L 'level is output as an output buffer circuit. Further, when the internal output signal Din is at the “H” level, the two-input NANDs 1 and 2 are
The outputs of the input NOR 2 are both at the “L” level, the driver P-channel transistor 4 is turned on, the N-channel transistor 5 is turned off, and the “H” level is output as the output buffer circuit. When the output buffer control signal CNTA changes from “H” to “L” level while the input buffer control signal bar CNTB remains at “H” level, the output of the 2-input NAND 1 is at “H” level regardless of the value of the internal output signal Din. The output of the 2-input NOR 2 becomes “L” level, both the driver P-channel transistor 4 and the N-channel transistor 5 are turned off, and the output buffer circuit becomes inactive.

The basic operation is as described above,
Similar to the above embodiment, when the output buffer control signal CNTA has a signal delay and has a waveform indicated by a dotted line as shown in FIG. 4, even if the input buffer control signal bar CNTB becomes'L 'level, the output buffer control signal Since CNTA is at the “H” level, the output of the 3-input NOR 8 is fixed at the “L” level and the input buffer circuit remains inactive. Then, the output buffer control signal CNTA is'L '.
The level, that is, the input buffer circuit becomes active after the output buffer circuit becomes inactive, so that an erroneous signal is not input and normal operation can be performed.

The second embodiment is the same as the first embodiment shown in FIG.
Compared with the circuit of the embodiment, there is an advantage that one inverter is unnecessary, the NOR input of the input buffer circuit is reduced by one input, and the number of elements is reduced to realize the same function.

Although the CMOS (complementary) transistor system has been described in the second embodiment, the present invention is not limited to this, and a P channel MOS transistor or N channel transistor system is also applicable.

[0036]

As described above, the input / output buffer circuit of the present invention has a high-level output signal from each output buffer circuit.
The impedance state is detected and the input buffer circuit is switched to the active state. Therefore, even if the control signal is delayed due to wiring capacitance or the like, the input buffer circuit is activated after the output buffer circuit becomes inactive for each terminal. Since no input is made, malfunctions do not occur and stable operation is possible.
An output buffer circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

2 is an operation timing chart of the circuit of FIG.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

4 is an operation timing chart of the circuit of FIG.

FIG. 5 is a circuit diagram of a conventional input / output buffer as an example.

6 is an operation timing chart of the circuit of FIG.

[Explanation of symbols]

 1 2 Input NAND 2 2 Input NOR 3 Inverter 4 Drive P Channel Transistor 5 Drive N Channel Transistor 6 Inverter 7 4 Input NOR 8 3 Input NOR 9 2 Input NOR

Claims (2)

[Claims] 1. An input / output buffer circuit having an output buffer circuit, a terminal connected to the output of the output buffer circuit, and an input buffer circuit connected to the terminal, wherein the inactive of the output buffer circuit An input / output buffer circuit having a switching means for detecting a state and switching the input buffer circuit to an active state. 2. The input / output buffer according to claim 1, wherein the output buffer circuit is a three-state output buffer circuit, and the output of the output buffer circuit becomes high impedance when the output buffer circuit is in the inactive state. In the circuit, the switching means detects a state of an input of the output buffer circuit in which the output of the output buffer circuit has a high impedance as an inactive state of the output buffer circuit, and sets the input buffer circuit to an active state. Input / output buffer circuit characterized by switching.