JPH0983313A - Pulse width adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the separation of an output pulse even when its adjustment range is larger than the input pulse width by cascading together the chopper circuits consisting of gate circuits and delay circuits only in plural stages. SOLUTION: For instance, two chopper circuits 11 and 12 having the same circuit configuration are cascaded to each other in two stages. The circuit 11 consists of an OR gate 13 which defines the pulse given directly as one of both its inputs and an inverter array 15 that consists of the inverters 141 and 142 cascaded to each other and serves as a delay circuit which inputs the pulse serving as one of both inputs of the gate 13 and defines it as the other input after delaying the pulse serving as the input as the gate 13 by a prescribed extent. The circuit 12 consists of an OR gate 16 which defines the pulse given directly from the circuit 11 as one of its both inputs and an inverter string 18 that consists of two inverters 171 and 172 cascaded to each other and defines the pulse serving as one of both inputs of the gate 16 as the other input of the gate 16 after delaying the pulse by a prescribed extent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width adjusting circuit, and more particularly to a circuit for adjusting the pulse width by adjusting the rising or falling edge timing of an input pulse.

[0002]

2. Description of the Related Art In general, a pulse width adjusting circuit of this type generally receives an input pulse IN directly applied thereto as shown in FIG.
OR gate 51 having one input and a plurality of (in this example,
4) inverters 52 ₁ to 52 ₄ is connected in cascade in, OR delays the input pulse IN by a predetermined delay amount
The gate circuit 51 is composed of a chopper circuit composed of an inverter array 53 which is the other input. The amount of delay with respect to the input pulse IN is determined by the number of inverter stages in the inverter train 53.

In the pulse width circuit having the above structure, assuming that the pulse width of the input pulse IN is a, this input pulse IN
The OR gate 51 takes the logical sum of the pulse and the pulse delayed by the inverter array 53 by a predetermined delay amount. Here, the delay amount of the inverter train 53 becomes the adjustment width b of the pulse width of the input pulse IN. As a result, the output pulse OUT having the pulse width of (a + b) is obtained. That is, the pulse width of the input pulse IN is expanded from a to (a + b).

[0004]

However, in the conventional pulse width adjusting circuit having the above structure, the adjusting width (delay amount) in the inverter train 53 is larger than the pulse width a of the input pulse IN.
When b is large, as is apparent from the waveform diagram of FIG. 7, the pulse generated at the point A rises after the fall timing of the input pulse IN,
Separation (hereinafter referred to as separation) occurs in the waveform of the output pulse OUT, and a correct output waveform cannot be obtained.

Further, depending on the input conditions, it is also assumed that the input width IN of the pulse width adjusting circuit is given to the adjustment width b of the pulse width adjusting circuit so as not to cause separation. In this case, various output conditions (power supply voltage, operating temperature, circuit peripheral parts, etc.) of the pulse width adjusting circuit affect whether separation occurs, resulting in an unstable output waveform.

The present invention has been made in view of the above problems, and an object thereof is to prevent separation of output pulses even when the adjustment width is large with respect to the pulse width of the input pulse. It is to provide such a pulse width adjusting circuit.

[0007]

A pulse width adjusting circuit according to the present invention is a circuit for adjusting the pulse width of an input pulse by a predetermined adjusting width by adjusting the rising or falling edge timing of the input pulse. A chopper consisting of a gate circuit that receives a given pulse as one input, and a delay circuit that delays the pulse that is one input of this gate circuit by a delay amount that is smaller than the pulse width of the input pulse and that is the other input of the gate circuit. The circuit is composed of a plurality of cascaded circuits.

In the pulse width adjusting circuit having the above structure, the delay amount in each stage of the chopper circuit is set smaller than the pulse width of the input pulse, so that the pulse width is gradually adjusted without causing separation in each stage. Is done. Then, finally, pulse width adjustment of a desired adjustment width is performed on the input pulse in total. Then, even when the adjustment width is larger than the pulse width of the input pulse, the final output pulse does not cause separation.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, showing an example of application to a positive logic input pulse. The pulse width adjusting circuit according to the present embodiment has a configuration in which, for example, two chopper circuits 11 and 12 having the same circuit configuration are cascade-connected in two stages. Then, in each of the chopper circuits 21 and 22, by using an OR gate as a gate circuit, it can be applied to a positive logic input pulse. In this embodiment,
Although the pulse width adjusting circuit having a two-stage configuration is shown for simplification of description, the present invention is not limited to this, and an arbitrary number of stages configuration can be adopted as necessary.

First, the chopper circuit 11 is composed of an OR gate 13 which receives a directly applied pulse as one input, and a plurality (two in this embodiment) of inverters 14 ₁ and 14 _{2 which} are connected in cascade. It is composed of an inverter train 15 as a delay circuit which delays a pulse which is one input of the gate 13 by a predetermined delay amount and which is the other input of the OR gate 13. Similarly, the chopper circuit 12 is composed of an OR gate 16 which receives a pulse directly applied from the chopper circuit 11 as one input, and two inverters 17 ₁ and 17 _{2 which} are connected in cascade, and serves as one input of the OR gate 16. It is composed of an inverter train 18 which delays a pulse by a predetermined delay amount and uses it as the other input of the OR gate 16.

The pulse width adjusting circuit having the above structure has a circuit structure corresponding to the conventional circuit shown in FIG. That is, in the conventional pulse width adjustment circuit, the adjustment width b is set by the four-stage inverter row 53, whereas in the present embodiment, the adjustment width b is divided into two, d1 and d2 (b = d1 + d).
2), the adjustment widths (delay amounts) d1 and d2 are set to the chopper circuit 1
It is provided in the two-stage inverter rows 15 and 18 of 1 and 12. Here, the delay amounts d1 and d2 are respectively the input pulse I
The condition is that it is smaller than the pulse width a of N. In addition,
To satisfy this condition, the number of divisions is increased to d1, d2,
It may be d3, ....

Next, the circuit operation of the pulse width adjusting circuit according to one embodiment of the above configuration will be described with reference to the waveform diagram of FIG. First, when a positive logic input pulse IN having a pulse width a is given, a pulse delayed by the delay amount d1 is obtained at the point A (the output end of the inverter train 15).
Then, the input pulse IN and the pulse at the point A become two inputs of the OR gate 13, so that the pulse width a of the input pulse IN is expanded to the pulse width (a + d1) at the point B (the output end of the OR gate 13). It will be.

Next, the pulse having the pulse width (a + d1) serves as one input of the OR gate 16 and the other input of the OR gate 16 via the inverter train 18. At this time, at point C (the output end of the inverter array 18), the delay amount d
A pulse having a pulse width (a + d1) delayed by 2 is obtained. Then, at the output end of the OR gate 16, the pulse width (a + d1 + d) is obtained by further expanding the pulse width by d2.
The output pulse OUT of 2) is obtained.

Thus, the pulse width a of the positive logic input pulse IN can be adjusted to the pulse width (a + d1 + d2), and the output pulse OUT having the pulse width (a + b) can be obtained. Further, the adjustment width b is larger than the pulse width a of the input pulse IN.
Is larger, the chopper circuits 11 and 12
Delay amounts d1 and d2 of the inverter trains 15 and 18 in
Since (b = d1 + d2) is set smaller than the pulse width a of the input pulse in, the pulse width is gradually adjusted without separation in each stage, and the adjustment width b is adjusted as a whole. Therefore, the final output pulse OUT does not cause separation.

As described above, a plurality of chopper circuits using OR gates as gate circuits are connected in cascade, and the delay amount of the inverter train in each chopper circuit is set smaller than the pulse width of the input pulse IN. Thus, the pulse width can be adjusted by adjusting the timing of the rising edge of the positive logic input pulse IN, and even if the adjustment width b is larger than the pulse width a of the input pulse IN, the output pulse OUT A stable output waveform can be obtained without causing the separation of.

FIG. 3 is a block diagram showing another embodiment of the present invention, showing an example of application to a negative logic input pulse. The pulse width adjusting circuit according to the present embodiment also has a configuration in which two chopper circuits 21 and 22 having the same circuit configuration are cascade-connected in two stages, as in the case of the previous embodiments.
Then, in each of the chopper circuits 21 and 22, an AND gate is used as a gate circuit so that it can be applied to an input pulse of negative logic.

First, the chopper circuit 21 is composed of an AND gate 23, which receives a directly applied pulse as one input, and two inverters 24 ₁ and 24 ₂ connected in series.
The gate of the gate 23 is delayed by a predetermined delay amount and the other input of the AND gate 23 is provided with an inverter array 25. Similarly, the chopper circuit 22
Is an AND gate 26 having one input of a pulse directly supplied from the chopper circuit 21 and two inverters 2
AND gate 26 is formed by connecting 7 ₁ and 27 ₂ in cascade.
A pulse which is one input is delayed by a predetermined delay amount
It is composed of an inverter array 28 which receives the ND gate 26 as another input.

Here, the adjustment width of this pulse width adjustment circuit is set to b
In this case, as in the case of the previous embodiment, this adjustment width b is divided into two parts d1 and d2 (b = d1 + d2), and the adjustment widths (delay amounts) d1 and d2 are stored in the chopper circuits 21 and 22. Two inverter rows 25 and 28 are provided. Also,
The delay amounts d1 and d2 are required to be smaller than the pulse width a of the input pulse IN, respectively. In order to satisfy this condition, the number of divisions may be increased to become d1, d2, d3, ....

Next, the circuit operation of the pulse width adjusting circuit according to another embodiment of the above configuration will be described with reference to the waveform diagram of FIG. First, when a negative logic input pulse IN having a pulse width a is applied, a pulse delayed by the delay amount d1 is obtained at the point A (the output end of the inverter array 25).
The input pulse IN and the pulse at the point A become two inputs of the AND gate 23, so that the point B (AND gate 2
This means that the pulse width a of the input pulse IN is expanded to the pulse width (a + d1) at the output terminal 3).

Next, the pulse having the pulse width (a + d1) serves as one input of the AND gate 26 and also serves as the other input of the AND gate 26 via the inverter array 28. At this time, a pulse having a pulse width (a + d1) delayed by the delay amount d2 is obtained at the point C (the output end of the inverter array 28). Then, at the output end of the AND gate 26, the pulse width (a + d1 +) is obtained by expanding the pulse width by d2.
The output pulse OUT of d2) is obtained.

Thus, the pulse width a of the negative logic input pulse IN can be adjusted to the pulse width (a + d1 + d2), and the output pulse OUT having the pulse width (a + b) can be obtained. Also, as in the case of the previous embodiment, the input pulse I
Even when the adjustment width b is larger than the pulse width a of N, the inverter array 1 in the chopper circuits 21 and 22 is
Since the delay amounts d1 and d2 of 5 and 18 are set smaller than the pulse width a of the input pulse in, the pulse width is gradually adjusted without separation at each stage, and the total adjustment width is adjusted. Since the adjustment of b is performed, the final output pulse OUT does not cause separation.

As described above, AND is used as the gate circuit.
By connecting multiple chopper circuits using gates in cascade and setting the delay amount of the inverter train in each chopper circuit to be smaller than the pulse width of the input pulse IN, the falling edge of the input pulse IN of negative logic is set. The pulse width can be adjusted by adjusting the timing of the output pulse OUT, and even if the adjustment width b is larger than the pulse width a of the input pulse IN, separation of the output pulse OUT does not occur and a stable output is obtained. Waveforms can be obtained.

In each of the above-mentioned embodiments, the inverter circuit is used as the delay circuit in each stage of the chopper circuit, but the invention is not limited to this.
Any circuit configuration may be used as long as it can delay a given pulse by a desired delay amount.

In each of the above embodiments, as an example,
When obtaining the adjustment width b for four stages of inverters, the number of stages of the inverter rows in the two chopper circuits is made equal by two and the delay amounts are set equal (d1 = d2 = b / 2).
However, if the conditions that the delay amounts d1 and d2 are smaller than the pulse width a of the input pulse IN are satisfied,
The number of inverter rows in each chopper circuit does not necessarily have to be set equal. However, setting the number of inverter rows in each chopper circuit to be equal is advantageous in terms of circuit design because variations in delay amount in each chopper circuit can be made substantially equal.

[0025]

As described above, according to the present invention,
It consists of a gate circuit that receives a pulse that is given directly as one input, and a delay circuit that delays the pulse that is one input of this gate circuit by a delay amount that is smaller than the pulse width of the input pulse and that is the other input of the gate circuit. Since the chopper circuits are connected in cascade in a plurality of stages, even if the adjustment width is larger than the pulse width of the input pulse, it is possible to prevent separation of the output pulse.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram according to one embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram according to another embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform diagram (1) according to a conventional example.

FIG. 7 is a waveform diagram (No. 2) according to the conventional example.

[Explanation of symbols]

 11, 12, 21, 22 Chopper circuit 13, 16 OR gate 15, 18, 25, 28 Inverter array 23, 26 AND gate

Claims (2)

[Claims] 1. A pulse width adjusting circuit for adjusting the pulse width of an input pulse by adjusting a timing of a rising edge or a falling edge of the input pulse by a predetermined adjustment width, the gate circuit having a directly applied pulse as one input. And a delay circuit which delays a pulse which is one input of the gate circuit by a delay amount smaller than the pulse width of the input pulse and which is the other input of the gate circuit, is an N-stage chopper circuit (N is 2). A pulse width adjusting circuit characterized in that the pulse width adjusting circuits are connected in cascade. 2. The pulse width adjusting circuit according to claim 1, wherein the delay amount is 1 / N of the adjusting width.