JP2608542B2 - Delay circuit - Google Patents

Description

The present invention relates to a delay circuit applied to, for example, a gate array LSI.

2. Description of the Related Art In a gate array LSI, a delay circuit is used to make a propagation delay time between signals constant. For example, in FIG. 2, it is assumed that latches the flip-flop FF1, FF2 by the clock CK _1, CK ₂ of the clock CK ₀ obtained by delaying the time t _1, t _2. In this case, as shown in Figure 3, after the latch by the clock CK ₁ of the flip-flop FF1, if the delay of the clock CK ₂ is large, that the latch by the clock CK ₂ of the flip-flop FF2 is performed on data after is there. That is, there is caused to hold time of the output data of the flip-flop FF2 to the clock CK ₂ of the flip-flop FF2 by the clock CK ₁ is reduced. Therefore, as shown in FIG. 4, when a delay circuit DL is inserted between the flip-flops FF1 and FF2,
The data output Q of the flip-flop FF1, as shown in FIG. 5 is delayed by time t _d by the delay circuit DL, therefore,
Data input D of the flip-flop FF2 is delayed by t _d from data output Q of the flip-flop FF1. As a result, the hold time of the input data of the flip-flop by the clock CK ₂ is sufficiently large.

 As the conditions of the above-described delay circuit, A) an optimum delay time can be obtained, B) a large area is not required, and C) a variation in delay time is required.

Generally, the delay time t per gate of a MOS transistor
_pd is t _pd ∝C / g _m where C is the load capacity and g _m is the conductivity. Therefore, if the load capacity C is constant, then g _m ∝W / L. The delay time can be increased by using an inverter with a MOS transistor having a small W and a large gate length L.
In I, only transistors of a certain size are used, so that the size of the transistor cannot be arbitrarily changed. Therefore, in the gate array LSI, conventionally, as shown in FIG. 6, the delay time is increased by connecting inverters in multiple stages. Note that a delay circuit can be configured by a CR circuit, but in this case, the delay time must be adjusted by the resistance or diffusion resistance of polysilicon, and therefore, parameters that are not used in the gate array LSI must be adjusted. Considering the variation, CR circuit is gate array
It is impossible to adopt it as a delay circuit of LSI.

In FIG. 6, if four gates equivalent to two input gates are defined as one basic cell and each inverter INV is configured as one basic cell, the delay time of the first stage is 0.77 when the potential of the input terminal IN changes from high to low. ns Second stage delay time 0.43 ns Third stage delay time 0.77 ns Fourth stage delay time is about 0.71 ns, so the total delay time is 2.68 ns. When the input potential IN changes from low to high, the delay time of the first stage is 0.43 ns, the delay time of the second stage is 0.77 ns, the delay time of the third stage is 0.43 ns, and the delay time of the fourth stage is about 1.32 ns. Therefore, the total delay time is 2.95 ns. (This value is a value when a CMOS having a gate length of about 2.5 μm is used.) Problems to be Solved by the Invention However, as described above, if a large number of inverters are simply connected in order to obtain a large delay time, In addition, there is a problem that the number of gates becomes large and therefore a large area is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array in view of the above-described problems.
It is an object of the present invention to provide a delay circuit which is suitable for an LSI and has a small area. The means is to provide two inverters in which P-channel / N-channel transistors are connected in cascade, and to output the output of the subsequent inverter to one of the inverters of the preceding stage. This is achieved by providing feedback to the department.

Operation According to the above configuration, since the output of the subsequent inverter is fed back to a part of the previous inverter, the driving capability is reduced, the delay time is increased, and the fan-out (F / O) is increased. 3.) A delay circuit having a large dependence can be obtained.

Embodiment FIG. 1 is a circuit diagram showing one embodiment of a delay circuit according to the present invention. In FIG. 1, two inverter means INV
A and INVB are provided. The inverter means INVA is constituted by cascade-connecting P-channel transistors Q _1p , Q _2p , Q _3p Q _4p and N-channel transistors Q _1n , Q _2n , Q _3n , Q _4n.
The channel / N channel transistor pair Q _1p , Q _1n constitutes one inverter, and the P channel / N channel pair Q _2p , Q _2n , Q
_3p , _Q3n , _Q4p , and _Q4n collectively constitute one inverter. Similarly, inverter means INVB is, P-channel transistor _{Q '1p, Q' 2p,} Q '3p, Q' 4p, and N-channel transistors _{Q '1n, Q' 2n,} Q '3n, Q' and _4n connected in cascade And a P-channel / N-channel transistor pair Q _1p , Q
_1n constitutes one inverter, and P channel / N channel pairs Q _2p , Q _2n , Q _3p , Q _3n , Q _4p and Q _4n collectively constitute one inverter.

As described above, since the output of the inverter at the subsequent stage is fed back to a part of the inverter at the previous stage, the driving capability of each inverter is reduced and the delay time is increased.

Note that if the circuit of FIG. 1 is constituted by a basic cell having two gates equivalent to two input gates, the transistors Q _1p , Q _2p , Q _1n , Q _2n ;
Transistors Q _3p , Q _4p , Q _3n , Q _4n ; Transistors Q ′ _1p , Q ′
_2p , Q ' _1n , Q'_2n; Transistors Q ' _3p , Q' _4p , Q ' _3n , Q'
_4n can each be composed of one basic cell, and therefore the first
The circuit shown in the figure can be composed of four basic cells as in the circuit of FIG.

The operation of the circuit of FIG. 1 will be described with reference to FIGS. 7 and 8.

In FIG. 7, it is assumed that the potentials of the input terminal IN and the output terminal OUT are at a high level as an initial state. At this time, since the transistor Q _1n to Q _4n it is in the on state, the potential of each potential and node B of the potential of the node A, the node D _1, D ₂ is at a low level, therefore, the transistor Q _'1p
Since to Q _'4p even in the on state, the potential of the node E _1, E _2, E ₃ is at a high level. When the potential of the input terminal IN changes from the high level to the low level in this state, the potential of the node A, which is the output of the inverter (Q _1p , Q _1n ), increases.
At this time, since the transistors Q _2n , Q _3n and Q _4n are still in the ON state, the potentials at the nodes D ₁ and D _{2 and} the potential at the node B rise following the potential A. As a result, as the potential of the node B rises, the transistors Q ′ _4n , Q ′ _3n , Q ′ _2n tend to turn on, and the nodes F ₁ , F ₂ , F ₃ are charged and their potentials rise. Accordingly, the potential of the output terminal OUT and the potentials of the nodes E ₁ , E ₂ , and E ₃ decrease. Such an unstable state continues until the potential of the output terminal OUT reaches the threshold value of the N-channel transistor. When the potential of the output terminal OUT reaches this threshold value, the transistors Q _2n , Q _3n and Q _4n are cut off and the potential of the node B rises again.

As described above, the potential of the node A is immediately increased, but a temporary saddle point is generated in the potential of the node B, so that the delay time of the decrease in the potential of the output terminal OUT increases.

In FIG. 8, it is assumed that each potential of the input terminal IN and the output terminal OUT is at a low level as an initial state. At this time, since the transistor Q _1p to Q _4p is in the on state, the potential of each potential and node B of the potential of the node A, node C _1, C ₂ is at a high level, therefore, the transistor Q _'1n
Since to Q _'4n even in the on state, the potential of the node F _1, F _2, F ₃ is at a low level. When the potential of the input terminal IN in this state changes from Robereru to a high level, the potential of the node A which is the output of the inverter (Q _1p, Q _1n) is lowered.
At this time, since the transistors Q _2p , Q _3p and Q _4p are still in the ON state, the potentials of the nodes C ₁ and C _{2 and} the potential of the node B fall following the potential A. As a result, not accompanied the lowering of the potential of the Node-B, a transistor _{Q '4p, Q' 3p,} Q '2p is turned on trend, node E _1, E _2, E ₃ is discharged these potential descends Accordingly, the potential of the output terminal OUT and the potentials of the nodes F ₁ , F ₂ , and F ₃ rise. Such an unstable state continues until the potential of the output terminal OUT reaches the threshold value of the P-channel transistor. When the potential of the output terminal OUT reaches this threshold value, the transistors Q _2p , Q _3p and Q _4p are cut off and the potential of the node B falls again.

As described above, although the potential of the node A is immediately decreased, the potential of the node B still has a temporary saddle point, so that the delay time of the rise of the potential of the output terminal OUT is increased. The reason why the delay time in FIG. 8 is larger than the delay time in FIG. 7 is that the driving capability of the P-channel transistor is smaller than the driving capability of the N-channel transistor.

Thus, when the potential of the input terminal IN changes from high level to low level, the delay time becomes 7 ns or more,
When the potential of the input terminal IN changes from low level to high level, the delay time becomes 17 ns or more, and in any case, the delay time becomes longer than in the case of FIG.

7 and 8 show the fan-out (F /
O) = 0, and when the fan-out is increased, the delay time is further increased.

In the above-described embodiment, each inverter means IN
Although the same number of P-channel transistors and N-channel transistors are connected in cascade to VA and INVB, it goes without saying that the number of transistors can be arbitrarily changed.
Further, an inverter as a waveform shaping means may be connected to the circuit of FIG.

Effect of the Invention As described above, according to the present invention, when the same number of basic cells are used, the driving capability of each inverter is reduced by feedback control as compared with the conventional case where inverters are simply connected in multiple stages. The delay time can be increased. In other words, when obtaining the same delay time, the area of the delay circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a delay circuit according to the present invention, FIG. 2 is a partial circuit diagram of a gate array LSI in which no delay circuit is inserted, and FIG. 3 is for explaining the circuit operation of FIG. FIG. 4 is a partial circuit diagram of a gate array LSI in which a delay circuit is inserted, FIG. 5 is a timing chart for explaining the circuit operation of FIG. 4, and FIG. 6 is a circuit showing a conventional delay circuit FIGS. 7 and 8 are timing diagrams of signals appearing in the circuit of FIG. IN: input terminal, OUT: output terminal, V _cc: power, INVA, INVB: inverter _{means, Q 1p, Q 2p, ...} : P -channel transistor, Q
_1n , Q _2n …: N-channel transistors.

Claims (1)

(57) [Claims] 1. An input terminal, an output terminal, first and second power supply means, and connected between the first and second power supply means,
A first inverter unit in which a plurality of the same number of P-channel transistors and an N-channel transistor are connected in cascade; and the outermost P-channel / N-channel transistor pair of the first inverter unit is determined by the potential of the input terminal. Driving the outermost P-channel of the first inverter means
The outermost P-channel / N-channel transistor pair of the second inverter means is driven by the common output of the / N-channel transistor pair, and the inner P-channel / N-channel transistor pair of the first inverter means is driven by the potential of the output terminal. To drive the inner P-channel / N-channel transistor pair of the second inverter means by the common output of the central P-channel / N-channel transistor pair of the first inverter means, Central P
A delay circuit in which the output of a channel / N-channel transistor pair is connected to the output terminal.