JPS60261216A - Multiplexer - Google Patents

Abstract

PURPOSE:To constitute a multiplexer of a small number of transisters (TRs), and to eliminate a DC current by supplying an output of a transfer gate by p and n type TRs to one of two cross-connected invertors. CONSTITUTION:The first and the second input signals DA, DB and a selecting signal SEL are applied to a transfer gate by MOS transistors TR8, 9 of n type and p type of a multiplexer, and an output signal B from a gate is outputted in accordance with a low or high level of the signal SEL. This output signal B is inputted to the first invertor constituted of MOS TRs 10, 11, and the second invertor constituted of MOS TRs 12, 13. An FF is constituted of said first and second inertors, and an output signal Q by which a DC current does not flow is outputted from this FF. Also, the multiplexer is constituted of a small number of TRs, and the circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplexer having an OMO8) transistor configuration, and particularly relates to a multiplexer that can be configured with a small number of transistors and does not conduct direct current.
It is highly effective when used in S digital integrated circuits.Conventional structure and problems thereof FIG. 1 shows a first conventional example of a multiplexer with an 0MO8 structure. 1 is an inverter with a CMOS transistor configuration,
2 is the same (0MO3 configuration AND-AND-NOR gate. When the selection signal SEL is low level (low logic level), the first input signal DA is high level (high logic), the first input signal DA is high level (high logic 'bell) The second input signal DB is selected and becomes the output Q (inverted) when The disadvantage is that it requires a large area on an integrated circuit.

Next, FIG. 2 shows a second conventional example. The function is exactly the same as the circuit of FIG. 3 and 4 are transfer gates formed by n-channel MO8) transistors. 5.61i
They are p-channel and n-channel transistors, respectively, and constitute a buffer inverter. 7 is an inverter.

This circuit is composed of six transistors and requires a small area, but since the transfer gate 3.4 is used, an intermediate potential is generated at point A. That is, the input signal selected from DA and DB is at high level (assumed to be sV).
2, the potential at point A in FIG. 2 drops from 5V to about 3 to 4V at room temperature due to the substrate bias effect. This leads to big trouble. In other words, while point A remains at an intermediate level of 3 to 4 V, both transistors 5 and 6 are on, so from vDD to (
A large DC current (up to several mA) flows through itND. This is very inconvenient because the power consumption of a CMOS digital LSI that uses many multiplexers will increase dramatically.

OBJECTS OF THE INVENTION The present invention was made in order to improve the drawbacks of the above-mentioned conventional examples, and it is an object of the present invention to provide a multiplexer that can be constructed with a small number of transistors and does not flow direct current.

Structure of the Invention The present invention achieves the above object by supplying the outputs of the transfer gates of a p-channel transistor and an n-channel transistor to one input of two cross-connected inverters (clip-flop configuration). This realizes a multiplexer.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows an embodiment of the present invention. 8, 16, 12・ is p
The channel MO8) is a transistor, and 9, 11 and 13 are n-channel MO, S transistors. The arrow indicates the source electrode. 12 and 13 constitute an inverter for the output cover.

In addition, 10 and 11 constitute an inverter, and 12 and 13
It constitutes a flip-flop together with an inverter consisting of. When the selection signal SEL is at a low level, the first input signal DA is at a low level; conversely, when SEL is at a high level, the second input signal DA is at a low level.
The input signal DB of is selected and becomes the output Q (inverted). The on-resistance of transistor 100 is set sufficiently high compared to the on-resistance of an n-channel transistor (not shown) that drives this multiplexer and the on-resistance of transistor 8.9. Similarly, the on-resistance of transistor 11 is set to be sufficiently high compared to the on-resistance of a p-channel transistor (not shown) that drives this multiplexer and the on-resistance of transistor 8.9. There are also two inverters (10 and 11), (12, 13)
)'s circuit threshold 'Ill pressure VthcU is about vDD//2, that is, VDD=5 V (when D is set to about 2.5 V).

Next, the operation will be explained.

When Q is at a low level and SEL is at a high level, that is, when transistors 9, 10, and 13 are on, D
When a low level signal is input to B, the on-resistance of transistor 1o is sufficiently large, so the potential at point B is vth
Well below c, "7 lip flop" (10-1
As a result of the positive feedback (3), Q rapidly rises to a high level. In the second case where Q is high level and SEL is low level, that is, when transistors 8, 11, and 12 are on, and a high level signal is input to DA, the on-resistance of transistor 11 is sufficient. Since the voltage at point B is large, the potential at point B sufficiently exceeds vtho, and Q rapidly transitions to a low level due to the positive feedback of the flipflop. Next, Q
In the third case where both SEL and SEL are at high level, that is, when transistors 9, 11, and 12 are on, and a high-level signal is input to DB, the on-resistance of transistor 11 is sufficiently large. The potential is sufficiently above vthe that Q quickly transitions to a low level due to the positive feedback of the seven lip-flops. Similarly, Q and SEL are both mouth-
- Fourth case of levels, i.e. transistors 8°10.
When transistor 13 is on, if a low-level signal is input to DA, the on-resistance of transistor 10 is sufficiently large, so the potential at point B falls well below vthc, and Q rapidly goes high.
Transition to a level.

Now, number three. In the fourth case, transistors 9,
A substrate bias effect is applied to transistor 8, and transistor 10.1
1 is absent, the potential at point B is about 3 to 4 V, 2 to 1 V (assuming vDD = 5 V), and a considerable amount of DC current flows, but transistor 10.11
acts as a pull-up and pull-down, so the potential at point B reaches 5V, OV. Therefore, the above-mentioned trouble cannot occur.

Effects of the Invention As described above, according to the present invention, it is possible to realize a CMOS multiplexer that can be configured with a small number of transistors and does not flow direct current, and is extremely valuable when used in CMO9 digital integrated circuits. It is.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first conventional example of a multiplexer;
FIG. 2 is a specific circuit diagram showing a second conventional example of a multiplexer, and FIG. 3 is a specific circuit diagram of a multiplexer showing an embodiment of the present invention. 12.13...First inverter, 10.11.
...Second inverter, 8...P channel MOS transistor, 9...N channel MO8)
Transistor, DA...First input signal, DB...
...second input signal, SEL ...selection signal, Q.
...Output signal. Name of agent: Patent attorney Toshio Nakao and 1 other person)

Claims (2)

[Claims] (1) a first inverter, a complementary MO8 whose input is connected to the output of the first inverter, and whose output is connected to the input of the first inverter; a P-channel MO3) transistor connected to the input of the first inverter; and an N-channel MO3') transistor, the drain of which is connected to the input of the first inverter;
O8) applying a first input signal to the source of the transistor;
A second input signal is applied to the source of the N-channel MO3) transistor, a selection signal is applied to the gate of the P-channel MO3) transistor, and the gate of the N-channel MOS transistor is applied to the first inverter. A multiplexer, characterized in that it obtains a selected output signal at the output of the multiplexer. (2) The second inverter has a relatively large on-resistance P
The multiplexer 0 according to claim 1, characterized in that it is composed of a channel MO3) transistor and an N channel MO8) transistor.