WO1995028768A1 - Multiplexing latch - Google Patents
Multiplexing latch Download PDFInfo
- Publication number
- WO1995028768A1 WO1995028768A1 PCT/US1995/003071 US9503071W WO9528768A1 WO 1995028768 A1 WO1995028768 A1 WO 1995028768A1 US 9503071 W US9503071 W US 9503071W WO 9528768 A1 WO9528768 A1 WO 9528768A1
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- WO
- WIPO (PCT)
- Prior art keywords
- output node
- reset
- transistor
- latch
- control terminal
- Prior art date
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Definitions
- the present invention relates in general to a multiplexing latch and in particular to a multiplexing latch having low signal propagation delay.
- FIG. 1 illustrates a typical prior art latch circuit having selectable set and reset inputs.
- the circuit includes a set of seven 2/1 multiplexers arranged in three stages for selecting one set signal from among eight in response to three input set selection signals S1-S3.
- the selected set signal drives a set input S of a conventional latch formed by two NOR gates .
- a second set of multiplexers arranged in a similar fashion permits selection of any of eight reset signals to drive a reset input R of the latch in response to a set of three reset selection signals
- the latch Upon receipt of a pulse at the set input, the latch sets its output signal Q to a true logic state and holds it true until it receives a pulse at its reset input R.
- the reset pulse causes the latch to drive its output signal Q to a logically false state and to hold it there until a set pulse is again delivered to its set input.
- the circuit can be expanded to allow for more set signals by increasing the number of multiplexer stages.
- One difficulty with the prior art arrangement is that for 2 N selectable input set or reset signals, each set or reset signal pulse must pass though N multiplexer stages. As the number of set or reset signals increases, the number of multiplexer stages at the set or reset input also increases . This causes a decrease in the speed of operation of the latch due to increasing signal propagation delay time through the multiplexer stages.
- a latch in accordance with one aspect of the invention, includes multiple pMOS transistors each having a gate providing a separate set signal input. Each pMOS transistor is connected to an output node for independently pulling up the voltage of the output node in response to a set signal pulse at its gate.
- the latch also includes a plurality of nMOS transistors each having a gate providing a separate reset signal input and each connected for independently pulling down the voltage of the output node in response to a reset signal pulse at its gate.
- a bistable circuit connected to the output node maintains the logic state of the output node after it is set or reset by a pulse at the gate of any of the nMOS or pMOS transistors.
- logic gates controlled by set and reset enable signals selectively enable each of the set and reset signals before they are supplied to the gates of the pMOS and nMOS transistors.
- the externally generated set and reset enable signals select the particular set or reset signal that is to operate the latch.
- the present invention carries out the function of a latch having large multiplexers at its set and reset inputs for selecting set and reset signals from among many.
- the invention requires set or reset signals to pass through relatively few logic stages and is therefore has relatively low propagation delay. It is accordingly an object of the invention to provide a latch having multiple set and reset inputs but minimal signal propagation delay.
- FIG. 1 is a block diagram of a prior art latch having multiplexed set and reset inputs
- FIG. 2 illustrates in block diagram form a latch having multiplexed set and reset input in accordance with the present invention.
- FIG. 2 illustrates in block diagram form a multiplexing latch 10 having an output Q, four set inputs S1-S4, four reset inputs Rl through R4, four set enable inputs SE1-SE4 and four reset enable inputs RE1-RE4.
- Multiplexing latch 10 sets and holds its output Q to a true logic state upon receipt of a pulse on any of its set inputs S1-S4 that art enabled.
- the set inputs S1-S4 are separately enabled by set enable inputs SE1-SE4, respectively. For example, if set enable input SEl is logically true then set input SI is enabled, and a logically true pulse on set input SI will set latch 10 output signal Q to a logically true state.
- Latch 10 resets and holds its output Q to a logically false state upon receipt of a pulse on any one of its reset inputs Rl- R4 that is enabled.
- the reset inputs R1-R4 are separately enabled by reset enable inputs RE1-RE4, respectively. For example, if reset enable input REl is true, then reset input Rl is enabled and a logically true pulse on reset input Rl will set latch 10 output signal Q to a logically false state.
- Latch 10 includes four CMOS NAND gates N1-N4, four
- Set inputs S1-S4 are applied to first inputs of NAND gates N1-N4, respectively, while set enable inputs SE1-SE4 are applied to second inputs of NAND gates N1-N4, respectively.
- Reset inputs R1-R4 drive first inputs of AND gates A1-A4, respectively, while reset enable inputs RE1-RE4 drive second inputs of AND gates A1-A4, respectively.
- the source of each transistor T1-T4 is tied to a first circuit node VSS while the source of each transistor T5-T8 is tied to a second circuit node.
- the first circuit node VSS is suitably maintained at a positive voltage level .
- the second circuit node is tied to ground or common, as represented by a triangle.
- the drains of all transistors T1-T8 are connected to a third circuit node S/R.
- Bistable circuit 12 consists of a pair of CMOS inverters II and 12.
- the output of inverter 12 is connected to the input of inverter II, and the output of inverter II is connected to the input of inverter 12 as well as to third circuit node S/R.
- the latch output signal Q appears at third circuit node S/R.
- set enable input SEl When, for example, set enable input SEl is high (logically true) and all other set enable input are low 5 (logically false) a true pulse from set signal SI will cause NAND gate Nl to pull down on the gate of transistor Tl, thereby turning on transistor Tl and pulling up node S/R to drive output Q high.
- output signal Q swings high, the output of inverter 12 goes 0 low and in turn causes the output of inverter II to go high, thereby latching Q high even after set signal SI goes low.
- inverter II has latched output Q high. Assume also that all set enable inputs are now 5 low, reset enable input RE1 is now high, and reset enable inputs RE2-RE4 are now low. A positive pulse on reset signal Rl will drive the output of AND gate Al high, thereby turning on transistor T5. Transistor T5 thereupon pulls down on node S/R, thereby resetting 0 output signal Q to a logically false state. As node
- latch 10 sets and holds its output Q to a true logic state upon receipt of a pulse on any one of its set inputs S1-S4 that is enabled and resets and holds its output Q to a logically false state upon
- each transistor Tl- T8 must be sized so that when it turns on it pulls output signal Q up or down irrespective of any opposing tendency of bistable circuit 12.
- the multiplexing latch of the present invention therefore has relatively low propagation delay. While the forgoing specification has described a preferred embodiment of the present invention, one skilled in the art may make many modifications to the preferred embodiment without departing form the invention in its broader aspects. For example, the circuit may easily altered to provide more or less set inputs by increasing or decreasing the number of NAND gates and pMOS transistors. Similarly the circuit may be altered to provide a larger or smaller number of reset inputs by increasing or decreasing the number of AND gates and nMOS transistors.
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Abstract
A multiplexing latch includes multiple pMOS transistors each having a control terminal providing a separate set signal input. Each pMOS transistor is connected to an output node for independently pulling up the voltage of the output node to set it to a high logic level in response to a set signal pulse at its control terminal. The latch also includes a plurality of nMOS transistors each having a control terminal providing a separate reset signal input and each connected to the output node for independently pulling down the voltage of the output node to reset it a low logic level in response to a reset signal pulse at its control terminal. A bistable circuit maintains the logic level of the output node after being set or reset by any of the nMOS or pMOS transistors. Logic gates controlled by input set and reset enable control signals selectively enable each of the set and reset signals before they are supplied to the gate terminals of the pMOS and nMOS transistors. Thus the externally generated set and reset enable signals select the particular set or reset signal that is to operate the latch.
Description
MULTIPLEXING LATCH
Background of the Invention Field of the Invention The present invention relates in general to a multiplexing latch and in particular to a multiplexing latch having low signal propagation delay.
Description of Related Art FIG. 1 illustrates a typical prior art latch circuit having selectable set and reset inputs. The circuit includes a set of seven 2/1 multiplexers arranged in three stages for selecting one set signal from among eight in response to three input set selection signals S1-S3. The selected set signal drives a set input S of a conventional latch formed by two NOR gates . A second set of multiplexers arranged in a similar fashion permits selection of any of eight reset signals to drive a reset input R of the latch in response to a set of three reset selection signals
R1-R3. Upon receipt of a pulse at the set input, the latch sets its output signal Q to a true logic state and holds it true until it receives a pulse at its reset input R. The reset pulse causes the latch to drive its output signal Q to a logically false state and to hold it there until a set pulse is again delivered to its set input. The circuit can be expanded to allow for more set signals by increasing the number of multiplexer stages. One difficulty with the prior art arrangement is that for 2N selectable input set or reset signals, each set or reset signal pulse must pass though N multiplexer stages. As the number of set or reset signals increases, the number of multiplexer stages at
the set or reset input also increases . This causes a decrease in the speed of operation of the latch due to increasing signal propagation delay time through the multiplexer stages.
Summary of the Invention In accordance with one aspect of the invention, a latch includes multiple pMOS transistors each having a gate providing a separate set signal input. Each pMOS transistor is connected to an output node for independently pulling up the voltage of the output node in response to a set signal pulse at its gate. The latch also includes a plurality of nMOS transistors each having a gate providing a separate reset signal input and each connected for independently pulling down the voltage of the output node in response to a reset signal pulse at its gate. A bistable circuit connected to the output node maintains the logic state of the output node after it is set or reset by a pulse at the gate of any of the nMOS or pMOS transistors. In accordance with another aspect of the invention, logic gates controlled by set and reset enable signals selectively enable each of the set and reset signals before they are supplied to the gates of the pMOS and nMOS transistors. Thus the externally generated set and reset enable signals select the particular set or reset signal that is to operate the latch.
The present invention carries out the function of a latch having large multiplexers at its set and reset inputs for selecting set and reset signals from among many. However the invention requires set or reset signals to pass through relatively few logic stages and is therefore has relatively low propagation delay.
It is accordingly an object of the invention to provide a latch having multiple set and reset inputs but minimal signal propagation delay.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements .
Brief Description of the Drawing(s) FIG. 1 is a block diagram of a prior art latch having multiplexed set and reset inputs; and
FIG. 2 illustrates in block diagram form a latch having multiplexed set and reset input in accordance with the present invention.
Description of the Preferred Embodiment(s) FIG. 2 illustrates in block diagram form a multiplexing latch 10 having an output Q, four set inputs S1-S4, four reset inputs Rl through R4, four set enable inputs SE1-SE4 and four reset enable inputs RE1-RE4. Multiplexing latch 10 sets and holds its output Q to a true logic state upon receipt of a pulse on any of its set inputs S1-S4 that art enabled. The set inputs S1-S4 are separately enabled by set enable inputs SE1-SE4, respectively. For example, if set enable input SEl is logically true then set input SI is enabled, and a logically true pulse on set input SI will set latch 10 output signal Q to a logically true state.
Latch 10 resets and holds its output Q to a logically false state upon receipt of a pulse on any one of its reset inputs Rl- R4 that is enabled. The reset inputs R1-R4 are separately enabled by reset enable inputs RE1-RE4, respectively. For example, if reset enable input REl is true, then reset input Rl is enabled and a logically true pulse on reset input Rl will set latch 10 output signal Q to a logically false state. Latch 10 includes four CMOS NAND gates N1-N4, four
CMOS AND gates A1-A4, four pMOS transistors T1-T3 , four nMOS transistors T5-T8, and a bistable circuit 12. Set inputs S1-S4 are applied to first inputs of NAND gates N1-N4, respectively, while set enable inputs SE1-SE4 are applied to second inputs of NAND gates N1-N4, respectively. Reset inputs R1-R4 drive first inputs of AND gates A1-A4, respectively, while reset enable inputs RE1-RE4 drive second inputs of AND gates A1-A4, respectively. Output signals G1-G4 of NAND gates N1-N4, respectively, drive control inputs (gates) of transistors T1-T4 while output signals G5-G8 of AND gates A1-A4 drive control inputs (gates) of transistors T5-T8, respectively. The source of each transistor T1-T4 is tied to a first circuit node VSS while the source of each transistor T5-T8 is tied to a second circuit node. The first circuit node VSS is suitably maintained at a positive voltage level . The second circuit node is tied to ground or common, as represented by a triangle. The drains of all transistors T1-T8 are connected to a third circuit node S/R. Bistable circuit 12 consists of a pair of CMOS inverters II and 12. The output of inverter 12 is connected to the input of inverter II, and the output of inverter II is connected to the input of inverter 12
as well as to third circuit node S/R. The latch output signal Q appears at third circuit node S/R.
When, for example, set enable input SEl is high (logically true) and all other set enable input are low 5 (logically false) a true pulse from set signal SI will cause NAND gate Nl to pull down on the gate of transistor Tl, thereby turning on transistor Tl and pulling up node S/R to drive output Q high. As output signal Q swings high, the output of inverter 12 goes 0 low and in turn causes the output of inverter II to go high, thereby latching Q high even after set signal SI goes low.
Assume now that inverter II has latched output Q high. Assume also that all set enable inputs are now 5 low, reset enable input RE1 is now high, and reset enable inputs RE2-RE4 are now low. A positive pulse on reset signal Rl will drive the output of AND gate Al high, thereby turning on transistor T5. Transistor T5 thereupon pulls down on node S/R, thereby resetting 0 output signal Q to a logically false state. As node
S/R swings low, the output of inverter 12 goes high and in turn causes the output of inverter II to go low, latching output signal Q low after the pulse on reset signal Rl goes low.
25 As may be seen from the foregoing example of operation, latch 10 sets and holds its output Q to a true logic state upon receipt of a pulse on any one of its set inputs S1-S4 that is enabled and resets and holds its output Q to a logically false state upon
30. receipt of a pulse on any one of its reset inputs Rl- R4 that is enabled. It should be noted that each transistor Tl- T8 must be sized so that when it turns on it pulls output signal Q up or down irrespective of any opposing tendency of bistable circuit 12. The
35 enable signal SE1-SE4 and RE1-RE4 states should be
constrained so that no transistor T1-T4 can turn on at the same time any transistor T5-T8 can turn on.
Thus has been shown and described a multiplexing latch which permits selection from among a large number of input set and reset signals but requires the selected set and reset signals to pass through relatively few logic stages . The multiplexing latch of the present invention therefore has relatively low propagation delay. While the forgoing specification has described a preferred embodiment of the present invention, one skilled in the art may make many modifications to the preferred embodiment without departing form the invention in its broader aspects. For example, the circuit may easily altered to provide more or less set inputs by increasing or decreasing the number of NAND gates and pMOS transistors. Similarly the circuit may be altered to provide a larger or smaller number of reset inputs by increasing or decreasing the number of AND gates and nMOS transistors. It should also be apparent that the enabling functions of the AND gates and the NAND gates and the latching function of bistable circuit 12 may be implemented in a variety of ways well known in the art. The appended claims therefore are intended to cover all such modifications as fall within the true scope and spirit of the invention.
Claims
1. A multiplexing latch comprising: an output node; a plurality of first transistors each having a control terminal providing a separate set signal input, each first transistor being connected to said output node for setting a voltage of the output node to a first logic level in response to a set signal pulse at said each first transistor's control terminal; a second transistor having a control terminal providing a reset signal input, said second transistor being connected to said output node for resetting the output node voltage to a second logic level in response to a reset signal pulse at its control terminal; and bistable circuit means for maintaining the output node voltage at said first logic after being set by any of said first transistors and for maintaining the output node voltage at said second logic level after being reset by said second transistor.
2. The latch in accordance with claim 1 wherein said plurality of first transistors consists of pMOS transistors and wherein said second transistor consists of an nMOS transistor.
3. The multiplexing latch in accordance with claim 1 wherein said bistable circuit means comprises: a first inverter having an output terminal connected to said output node and an input terminal; and a second inverter having an output terminal connected to the input terminal of said first inverter and an input terminal connected to said output node.
4. A multiplexing latch comprising: an output node; a plurality of first transistors each having a control terminal providing a separate set signal input, each first transistor being connected to said output node for setting a voltage of the output node to a first logic level in response to a set signal pulse at said each first transistor's control terminal; a second transistor having a control terminal providing a reset signal input, said second transistor being connected to said output node for resetting the output node voltage to a second logic level in response to a reset signal pulse at its control terminal; bistable circuit means for maintaining the output node voltage at said first logic after being set by any of said first transistors and for maintaining the output node voltage at said second logic level after being reset by said second transistor; and logic means for supplying a set signal to the control terminal of a selected one of said first transistors .
5. The multiplexing latch in accordance with claim 4 wherein said plurality of first transistors comprises pMOS transistors and wherein said second transistor comprises an nMOS transistor.
6. The multiplexing latch in accordance with claim 4 wherein said bistable circuit means comprises : - a first inverter having an output terminal connected to said output node and an input terminal; and a second inverter having an output terminal connected to the input terminal of said first inverter and an input terminal connected to said output node.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22840194A | 1994-04-14 | 1994-04-14 | |
| US8/228,401940414 | 1994-04-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1995028768A1 true WO1995028768A1 (en) | 1995-10-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1995/003071 WO1995028768A1 (en) | 1994-04-14 | 1995-03-08 | Multiplexing latch |
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| WO (1) | WO1995028768A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114388016A (en) * | 2021-12-08 | 2022-04-22 | 中天弘宇集成电路有限责任公司 | Pulse signal generating circuit and memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60261216A (en) * | 1984-06-08 | 1985-12-24 | Matsushita Electric Ind Co Ltd | Multiplexer |
| US4645944A (en) * | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
| US4709173A (en) * | 1985-05-17 | 1987-11-24 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit having latch circuit with multiplexer selection function |
| EP0499430A2 (en) * | 1991-02-14 | 1992-08-19 | Advanced Micro Devices, Inc. | Edge-triggered flip-flop |
| US5189319A (en) * | 1991-10-10 | 1993-02-23 | Intel Corporation | Power reducing buffer/latch circuit |
-
1995
- 1995-03-08 WO PCT/US1995/003071 patent/WO1995028768A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4645944A (en) * | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
| JPS60261216A (en) * | 1984-06-08 | 1985-12-24 | Matsushita Electric Ind Co Ltd | Multiplexer |
| US4709173A (en) * | 1985-05-17 | 1987-11-24 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit having latch circuit with multiplexer selection function |
| EP0499430A2 (en) * | 1991-02-14 | 1992-08-19 | Advanced Micro Devices, Inc. | Edge-triggered flip-flop |
| US5189319A (en) * | 1991-10-10 | 1993-02-23 | Intel Corporation | Power reducing buffer/latch circuit |
Non-Patent Citations (1)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 10, no. 129 (E - 403)<2186> 14 May 1986 (1986-05-14) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114388016A (en) * | 2021-12-08 | 2022-04-22 | 中天弘宇集成电路有限责任公司 | Pulse signal generating circuit and memory |
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