JPH07262781A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a CMOS circuit suitable for a high-speed operation. CONSTITUTION:Potentials 30, 31 for adjusting delay time are added to a delay circuit 300 generating a reset signal having the same phase as that of an output signal 20 and delayed by a prescribed time and the delay time of the delay circuit 300 is made constant regardless of power source voltage, temp. and the dispersion in manufacturing by controlling the delay time adjusting potentials 30, 31 in a self-reset circuit. By making the pulse width of the output signal constant regardless of power source voltage, temp. and the dispersion in manufacturing, the decrease of a margin to the skew of the signal due to the decrease of the pulse width of the output signal is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly,
The present invention relates to a high speed CMOS circuit and a CMOS memory circuit.

[0002]

2. Description of the Related Art CMOS circuits are widely used in the field of semiconductor integrated circuits, and high speed and high integration have been achieved by miniaturization of processing techniques. However, the limits of microfabrication are beginning to be recognized, and there is a strong demand for not only miniaturization of machining technology, but also speeding up by devising circuits.

As a speedup by devising such a circuit, it has been proposed to shorten a memory access time and realize a pipeline operation using a synchronous circuit. For example, as a synchronous high-speed CMOS memory circuit,
E-Journal of Solid State Circuts Volume 26 Number-11 1991 Pages 1577-1585 (IEEE Journal of Solid-State
Circuits, Vol. 26, No. 11, November 1991, pp.157
7-1585) or the circuit of U.S. Pat. No. 4,985,643 is known. In this conventional self-reset circuit (or post-charge circuit), the pulse operation of the circuit reduces the input capacitance to about half that of a normal CMOS circuit, speeding up the circuit, and increasing the effective channel length to 0.5.
A synchronous memory (SRAM) having an access time of about 4 ns and a cycle time (reading and writing of data) of 2 ns has been realized in a CMOS device of μm. Further, in the conventional self-reset circuit, a pulse for resetting the output signal (reset pulse) is generated from the output signal, so that the reset pulse is supplied only to the circuit in which the signal has changed, and a dynamic clock is supplied collectively from the outside. Compared to the circuit, there was no ineffective power consumption in the clock, and low power consumption was achieved.

[0004]

Although the conventional self-reset circuit has achieved high speed and low power consumption with respect to the dynamic circuit, the pulse width of the signal is reduced to a simple CM.
Since it is determined by the delay time of the delay circuit in which the OS gate circuits are connected in multiple stages, the delay time of the delay circuit fluctuates due to power supply voltage fluctuations, temperature fluctuations, and process variations, and the pulse width of the signal also changes.

For example, when the power supply voltage is high, the temperature is low, and the pulse width of the signal is narrow, if there is a substantially constant signal skew that does not depend on the power supply voltage, such as delay due to wiring resistance and wiring capacitance, the signal The period of overlap with other signals becomes shorter than the narrower pulse width.

That is, the conventional self-reset circuit has a problem that the pulse width of the signal is affected by the power supply voltage fluctuation, the temperature fluctuation, and the process variation, and the operation margin is reduced when the signal pulse width becomes narrow. . Further, when the power supply voltage is low, the temperature is high, and the pulse width of the signal is large, the maximum operating frequency of the circuit becomes small. Such a problem is particularly prominent in a device such as a DRAM or an SRAM that has a strict requirement for the pulse width.

A first object of the present invention is to provide a self-reset circuit which realizes a characteristic that the pulse width of a signal is not affected by power supply voltage fluctuations, temperature fluctuations and process variations without impairing the high speed of the self-reset circuit. To provide.

A second object of the present invention is to provide a delay circuit suitable for generating a reset pulse of a self-reset circuit in order to achieve the first object.

In order to achieve the above first and second objects, a third object of the present invention is to provide a circuit suitable for generating a delay time control signal of a delay circuit for generating a reset pulse of a self reset circuit. To provide.

A fourth object of the present invention is to provide a high speed memory circuit using a self reset circuit in which the pulse width of the above signal is controlled to be constant.

A fifth object of the present invention is to provide a synchronous circuit for an external clock and an internal clock suitable for a high speed memory circuit using the self reset circuit in order to achieve the fourth object. .

A sixth object of the present invention is, in order to achieve the fifth object, a frequency division suitable for a circuit for synchronizing an external clock and an internal clock of a high speed memory circuit using the self reset circuit. To provide a container.

[0013]

In order to achieve the above first object, in the present invention, in a self-reset circuit, a voltage for controlling the delay time of the delay circuit is applied to a delay circuit for generating a reset pulse to control the delay circuit. A control voltage is generated by the signal generation circuit.

In order to achieve the above second object, according to one embodiment of the present invention, in a self reset circuit,
The delay circuit is composed of even-numbered CMOS gate circuits, and a MOS transistor whose gate signal is the output of the self-reset circuit or the output of the CMOS gate circuit of the previous stage and a MOS transistor whose gate signal is the control voltage are connected in series.

In order to achieve the above second object, in another embodiment of the present invention, in the self-reset circuit, the delay circuit is formed by an even number of stages of CMOS gate circuits, and the self-reset circuit output or the preceding stage CMOS gate is provided. To the output of the MOS transistor part that uses the circuit output as the gate signal,
A transfer MOS transistor using a control voltage as a gate signal is connected.

To achieve the third object, in the present invention, in the self-reset circuit, the control voltage of the delay circuit is the control voltage of the voltage controlled oscillator of the PLL circuit, and P
The LL circuit (FIG. 3) compares the phase of the reference clock signal with the phase of the output signal of the voltage controlled oscillator. Also, PLL
The voltage controlled oscillator of the circuit is composed of a circuit similar to the delay circuit of the self reset circuit.

In order to achieve the third object, in another embodiment of the present invention, the phase of the reference clock signal and the voltage control delay are controlled by the voltage control delay circuit, the phase comparator, the charge pump circuit and the loop filter circuit. The phases of the output signals of the circuits are compared, and the control voltage of the delay circuit of the self-reset circuit is set to the control voltage of the voltage control delay circuit. Further, the voltage control delay circuit is configured by a circuit similar to the delay circuit of the self reset circuit.

In order to achieve the above third object, in another embodiment of the present invention, in a self reset circuit,
The control voltage of the delay circuit is the gate potential of the MOS transistor controlled so that the drain current proportional to the power supply voltage flows, or the output of the current mirror circuit that receives the gate potential.

In order to achieve the fourth object, the present invention uses a self-reset circuit in which the pulse width of the signal is controlled to be constant in the address buffer circuit and the decode circuit. In addition, a clock signal that determines the timing of taking the address signal into the memory is applied to the PLL circuit that generates a voltage that controls the delay time of the delay circuit of the self-reset circuit.

In order to achieve the fifth object, in the present invention, an external clock signal is added to the voltage controlled delay circuit,
The output of the voltage controlled delay circuit is applied to the pulse width limiting circuit.
An internal clock signal is generated by applying the output of the pulse width limiting circuit to the buffer circuit. By adding the external clock signal and the internal clock signal to the circuit consisting of the frequency divider, phase comparator, charge pump circuit and loop filter circuit, and comparing the phase of the external clock signal and the phase of the internal clock signal, the voltage control delay Generates the control voltage for the circuit.

In order to achieve the sixth object, in the present invention, the oscillation frequency of the clocked inverter circuit and the ring oscillator composed of the inverter circuit is controlled by the external clock signal and the inverted signal of the external clock.
A frequency-divided signal of the internal clock signal is generated by generating a frequency-divided signal of the external clock signal and capturing the ring oscillator signal in the latch circuit by the clocked inverter circuit controlled by the internal clock signal and its inverted signal. Occur.

[0022]

In a typical embodiment of the present invention (FIG. 1), the control voltage adjusts the time from when the output of the self-reset circuit changes to a low level until the MOS for resetting the output signal becomes conductive. You can Under the condition that the delay time is short such as high power supply voltage, low temperature, short MOS transistor gate length, etc., the gate-source voltage of the MOS transistor that adds the control voltage to the gate is reduced, and the power supply voltage is low. Under the condition that the delay time is large, such as high temperature and long MOS transistor gate length,
The delay time of the delay circuit can be kept constant by increasing the gate-source voltage of the MOS transistor that applies the control voltage to the gate. The control voltage can be generated by the control voltage generating circuit so that the delay time of the delay circuit becomes constant.

A typical embodiment of the present invention (FIG. 1)
Then, by connecting in series the MOS transistor that uses the output signal or the output of the previous CMOS gate circuit as the gate signal and the MOS transistor that uses the control voltage as the gate signal, the gate capacitance load of the MOS transistor is almost at the control voltage terminal. It will only be connected.

In another embodiment of the present invention (FIG. 19), the gate voltage load of the MOS transistor is almost connected to the control voltage terminal.

In a representative embodiment of the invention (FIG. 3),
The control voltage of the voltage controlled oscillator of the PLL circuit is determined so that the oscillation cycle (that is, delay time per stage × number of stages × 2) and phase of the reference clock signal and the voltage controlled oscillator become equal, and the voltage controlled oscillator is self-reset. Since the circuit is composed of the same circuit as the delay circuit of the circuit, the delay time per stage of the delay circuit is also determined by the control voltage under the condition that the period of the reference clock signal is constant. By setting this control voltage as the control signal of the delay circuit of the self-reset circuit and keeping the cycle of the reference clock signal constant, the delay time of the delay circuit of the self-reset circuit can be controlled to be constant.

In another embodiment of the present invention (FIG. 14), the control voltage of the voltage controlled delay circuit is determined so that the phase of the reference clock signal and the phase of the output signal of the voltage controlled delay circuit are equal. Under the condition that the signal cycle is constant, the delay time per stage of the voltage control delay circuit is determined, and the control voltage also determines the delay time per stage of the delay circuit. By setting this control voltage as the control signal of the delay circuit of the self-reset circuit and keeping the cycle of the reference clock signal constant, the delay time of the delay circuit of the self-reset circuit can be controlled to be constant.

In another embodiment of the present invention (FIG. 15), the drain current of the MOS transistor in which the control voltage is applied to the gate electrode is proportional to the power supply voltage, so that the power supply voltage fluctuation of the delay time of the delay circuit of the self-reset circuit is changed. Can be compensated.

In a representative embodiment of the invention (FIG. 7),
By using the self-reset circuit in which the pulse width of the signal is controlled to be constant for the address buffer circuit and the decode circuit, the decode time and the cycle time can be shortened. In addition, by adding a clock signal that determines the timing of fetching the address signal to the memory to a PLL circuit that generates a voltage that controls the delay time of the delay circuit of the self-reset circuit, the clock signal that determines the timing of fetching the address signal to the memory. The delay time of the delay circuit of the self reset circuit can be controlled.

In one embodiment of the invention (FIG. 16), the phase of the external clock signal matches the phase of the internal clock signal,
Further, power consumption in the pulse width limiting circuit and the buffer circuit can be reduced.

In one embodiment of the present invention (FIG. 17), a signal obtained by dividing the external clock signal and a signal obtained by dividing the internal clock signal are obtained.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a self-reset circuit according to the present invention that can control the pulse width to a constant value, and FIG.

FIG. 1 shows a part of a memory decoding circuit. The circuit of FIG. 1 functions as an AND circuit which inverts the signals of the input 10 and the input 11 and outputs them to 21 (20) and 22 and outputs the NOR logic signal of the signals 21 and 22 to 23.

First, the circuit 602 of FIG. 1 will be described. The circuit 602 functions as an inverter circuit which outputs an inverted signal of the input 10 to 20. The following measures have been taken to increase the speed. In a self-reset circuit such as the circuit of FIG. 1, a signal is not treated as a static potential of low level “L” or high level “H” but is represented by the presence or absence of a pulse as shown in FIG. For example, as shown at 10 in FIG. 2, 10 is “L” to “H”
Further, the state of changing to "L" is referred to as a "1" state, and the state of no pulse being output from "L" is referred to as a "0" state. Therefore, the propagation delay time of the signal only needs to be considered as the delay time from the change of 10 from “L” to “H” to the change of 20 from “H” to “L”.

Here, since it is the same as a normal CMOS circuit except that a signal is expressed by a pulse, it can be applied to a decoder of a memory circuit and the like, and detailed application examples will be described with reference to FIG. That is, regarding the circuit 602, it is sufficient to consider only the delay time from when “10” changes from “L” to “H” to when “20” changes from “H” to “L”.
To reduce this delay time, the circuit 602 is designed as follows.

The PMOS 200 of the circuit 602 is an element for applying a DC potential of 20, and has a gate width in comparison with that of an NMOS transistor (hereinafter abbreviated as NMOS) 100 and a PMOS transistor (hereinafter abbreviated as PMOS) 201. Designed small enough. As a result, the input capacitance of 602 is almost equal to the gate capacitance of NMOS 100.
The ratio of the gate width of 00 to the gate width of NMOS 100 is 1: 1 to 2: 1 when compared with a normal CMOS circuit when the load drive current is constant and the input capacitance is about 1/2. The load drive current is approximately doubled, and high speed operation is achieved. The PMOS 201 acts as an element for charging the output 20 from “L” to “H”, and is driven by the signal 50 (reset pulse) in phase with 20 and delayed by a predetermined time. The gate width of the PMOS 201 is designed to be large so that the charging delay time of 20 is reduced, but the gate capacitance of 201 is not included in the capacitance of the input 10, and the delay circuit 300 including a four-stage inverter circuit is used. Is connected to the output 20 via
The increase in capacity of 20 is also small. For example, if the ratio of the input capacitance / load capacitance of each inverter stage of the delay circuit 300 is designed to be 1: 5, the sum of the gate capacitances of the PMOS 203 and the NMOS 101 is PMOS 2
It becomes 1/625 of 01 gate capacity.

The operation of the circuit 602 will be described with reference to FIG. A pulse changing from a low level (hereinafter referred to as “L”) to a high level (hereinafter referred to as “H”) and further to “L” is input to the input 10. A pulse that changes from “H” to “L” and then to “H” is output to the output 20.
When the input 10 is "L", 20 is "H" and 50 is "H". When the input 10 changes from "L" to "H", 20 changes to "L". When 20 changes to "L", the delay time of the delay circuit 300 is delayed by 50
Changes to "L". When 50 becomes "L", PMOS
201 becomes conductive.

When the input 10 is designed to be "L" at the time when 50 becomes "L", the PMOS 201 becomes conductive and the NMOS 100 changes to non-conductive at the same time.
The shoot-through current flowing through the NMOS 100 can be made approximately the same as that of a conventional CMOS circuit. Input 1 before the time when 50 becomes "L"
If 0 is designed to be “L”, PMOS 201, NMOS 1
The through current flowing through 00 can be made smaller than that of the conventional CMOS circuit. In order to make the operation easier to understand, in FIG. 2 (solid line), the input 10 is “L” before the time when 50 becomes “L”.
The waveforms when designed to be (Fig. 2
A method of generating a pulse signal having a narrow width such as the inputs 10 and 11 from the external clock signal will be described later with reference to FIG. ) Since PMOS 201 is conductive and NMOS 100 is non-conductive, 20
Becomes "H". The time at which the PMOS 201 becomes conductive is after the delay time of the delay circuit 300 after 20 changes to “L”, so that the pulse width of 20 is ultimately determined by the delay time of the delay circuit 300. When the PMOS 201 becomes conductive and 20 becomes "H", 50 changes to "H" and the PMOS 201 becomes non-conductive at the time delayed by the delay time of the delay circuit 300. Since the PMOS 201 becomes non-conductive, the next time when the input 10 changes from “L” to “H”, 20 can be discharged to “L” at high speed.
It will be in a standby state waiting for the next change in input. That is, the minimum operation cycle time of 602 is the sum of the pulse width of about 20 and the pulse width of 50. Since the pulse width of 20 and the pulse width of 50 are each about the delay time of the delay circuit 300,
The minimum operation cycle time of 2 is about twice the delay time of the delay circuit 300.

Another effect of driving the gate electrode of the PMOS 201 in the circuit 602 by the delay circuit 300 will be described. By driving the PMOS 201 with the delay circuit 300, the gate capacitance of the 201 is discharged from “H” to “L” only when the output 20 changes from “H” to “L” (why? If so, the delay circuit 300 outputs the delayed signal at the output 20). On the other hand, in the case of the conventional dynamic circuit in which the gate of 201 is driven by a clock signal common to some circuits on the chip, the reset PMOS of the circuit in which the output 20 does not change (other circuits corresponding to 201) (PMOS of) will also be charged and discharged, which will consume unnecessary power originally. That is, by driving the PMOS 201 with the delay circuit 300, lower power consumption can be achieved as compared with the conventional dynamic circuit.

A circuit 600 in FIG. 1 shows an inverter circuit having the same structure as the circuit 602, and a circuit 601 shows a delay circuit having the same structure as 300. Also, the resistor 405 and the capacitor 50
1 is the output 20 of the inverter circuit and NOR circuits 230, 2
The (parasitic) resistance and the (parasitic) capacitance of the wiring for connecting to the input 21 of 31, 150, 151 are shown. N in FIG.
The OR circuits 230, 231, 150, 151 are also devised to speed up similarly to the inverter circuit 602. 60
In 2, the PMOS 200 was designed to be sufficiently smaller than the NMOS 100 and PMOS 201, but the NOR circuits 230, 231, 150, 1
In 51, the gate widths of the NMOSs 150 and 151 are equal to those of the PMOSs 230 and 23.
1, designed to be smaller than the NMOS 152 gate width. (2
In Nos. 1 and 22, the case of changing from “H” to “L” and further to “H” corresponds to the state of “0”, and the case where no pulse is output and the state of changing from “H” corresponds to the state of “1”. This makes it possible to obtain the same speed-up effect as 602.

NOR circuits 230, 231, 15 of FIG.
The operation of 0 and 151 will be described with reference to FIG. Similarly to the input 10, a pulse that changes from “L” to “H” and then to “L” is input to the input 11, and the output 2 is output as described above.
A pulse that changes from "H" to "L" to "H" is output to 0 and 22. When the inputs 10 and 11 change from "L" to "H", the inputs 20 and 22 change to "L".
When 20 and 22 change to "L", 23 changes to "H". When 23 changes to “H”, the gate potential of the NMOS 152 changes to “H” at the time delayed by the delay time of 601. When the gate potential of the NMOS 152 changes to "H", 23 becomes "L". Further, at the time delayed by the delay time of 601, the gate potential of the NMOS 152 becomes "L", and the standby state is waited for the next input.

In the circuit of FIG. 1, the following measures are taken in order to keep the pulse widths of 20, 22, 23 constant and not to increase the minimum operation cycle time.

The circuit 602 will be described as an example. In 602, the delay time of the delay circuit 300 is adjusted by the control voltages 30 and 31, and the pulse widths of 20 and 50 are set to a predetermined value.
For example, when the power supply voltage is high and the temperature is low, it is possible to prevent the pulse width of 20 from narrowing by increasing the potential of 30 and decreasing the potential of 31, and the power supply voltage is low. When the temperature is high, it is possible to prevent the pulse width of 20 from increasing by decreasing the potential of 30 and increasing the potential of 31. Set the delay time of the delay circuit 300 to 3
Since the adjustment is performed only with the potentials of 0 and 31, high speed performance similar to that of the conventional self-reset circuit can be maintained.

In the waveform diagram of FIG. 2, the solid line shows the operation waveform of the circuit of the present invention and the conventional circuit when the power supply voltage is low, the temperature is high, and the delay time of the delay circuit is long, and the broken line shows the power supply voltage. The operation waveforms of the conventional circuit when the temperature is high, the temperature is low, and the delay time of the delay circuit is short are shown. The output 20 of the inverter circuit and the NOR circuits 230, 231,
150 and 151 are arranged at distant locations on the chip. Inverter circuit output 20 and NOR circuits 230, 2
Due to the presence of the (parasitic) resistance 402 and the (parasitic) capacitance 501 of the wiring for connecting to the input 21 of 31, 150, 151, the signal waveform of 21 has rise time and fall time as shown in FIG. Both become large, and the waveform becomes a waveform delayed from the signal 20 by the time constant of the wiring.

On the other hand, the inverter circuit 600 is arranged near the NOR circuits 230, 231, 150, 151. Therefore, 22 is not affected by the wiring delay, and N
The pulse widths of the two inputs 21 and 22 of the OR circuit have different values, and the period in which both 21 and 22 are "L" is 2
It is smaller than the pulse width of 0,22. In order for 23 to change to "H", there must be a time sufficient to charge 23 to "H" and a period in which both inputs 21 and 22 are "L".

In the waveform (broken line) of the conventional circuit of FIG. 2, the pulse width of 20 becomes small due to fluctuations in the power supply voltage, temperature, etc. Therefore, the period in which both inputs 21 and 22 are "L" is small, and the PMOS 230, It shows an example in which the 231 is not conducting completely and the charging time of the 23 is long (NOR output 2
Since the rise of 3 is delayed, the rise of the gate potential of the NMOS 152 is also delayed, and this also affects the pulse width of 23, but for simplicity, FIG. 2 shows only the influence on the gate potential of the NMOS 152).

In the conventional circuit, the pulse width fluctuates due to variations in power supply voltage, temperature, and manufacturing variations. Therefore, if an operating margin is secured, the pulse width increases, that is, the operating frequency decreases. On the other hand, in the circuit of the present invention, the control voltages 30, 3
Since 1 can control the pulse width of 20 to be constant, it is possible to prevent the pulse width of 20 from decreasing and the operation margin against the signal skew from decreasing. When the power supply voltage is low and the temperature is high, the potential of 30 is set low and the potential of 31 is set high, whereby the pulse widths of 20 and 50 can be prevented from increasing. With this, it is possible to prevent an increase in the minimum operation cycle time of the circuit and a decrease in the maximum operation frequency while securing an operation margin,
High frequency operation becomes possible. Although FIG. 1 and FIG. 2 have described the example of the signal skew due to the resistance and capacitance of the wiring, the same effect can be obtained with respect to the general signal skew.

Further, the control voltages 30 and 31 are set to the PMOSs 202 and 2
04, 206, 208, gate electrodes of NMOS 102, 104, 106 and 108, 203, 205, 207,
By connecting in series with 209, 101, 103, 105 and 107 and controlling the delay time, the load of the control terminals 30, 31 is only the gate capacitance, and there is an advantage that a large current does not have to be supplied to 30, 31. . For example, when controlling the source electrode of a MOS transistor, the power supply of the control potential has to supply the drive current of the load, but in the structure of this embodiment, such a problem of designing the current supply capacity of the power supply can be avoided. Therefore, it is possible to prevent a decrease in accuracy due to the flow of a large current. Further, there is an advantage that the problem of forward bias between the substrate and the source / drain electrodes does not occur when controlling the substrate electrode.

As described above, in the circuit of FIG. 1, the delay times of the delay circuits 300 and 601 are controlled by the control voltages 30 and 31.
It is characterized in that the pulse width of 20 and 50 is controlled to be constant, and a high frequency operation is possible while securing an operation margin. In the circuit of FIG. 1, the delay circuit is composed of an inverter circuit, but it can be easily applied to a case where the delay circuit is composed of a general logic circuit.

FIG. 3 shows an example of a circuit for generating the control voltages 30 and 31 of the self-reset circuit of the present invention. The circuit of FIG. 3 is a circuit called a PLL, and the inverter circuits 301 to 309 capable of controlling the delay time by voltage constitute a voltage controlled oscillator. Control voltage of this voltage controlled oscillator 30,
31 is supplied as the delay time control voltages 30 and 31 of the circuit of FIG.

The operation of the circuit shown in FIG. 3 will be described. The oscillation output signal 51 of the voltage controlled oscillators 301 to 309 is transmitted to the frequency divider 311 by the inverter circuit 310. 310 functions as a buffer circuit. The signal 53 divided by the frequency divider 311 and the reference clock signal 40 are compared by the phase comparator 312.
When the frequency of 53 is higher than the frequency of the reference clock signal 40, the circuit of FIG. 3 acts to raise the potential of the control voltage 30 and lower the potential of 31 so as to lower the oscillation frequency of the voltage controlled oscillator. When the frequency of 53 is lower than the frequency of the reference clock signal 40, the circuit of FIG. 3 works to lower the potential of the control voltage 30 and increase the potential of 31 so as to increase the oscillation frequency of the voltage controlled oscillator. That is, the frequency of 53 becomes equal to the frequency of the reference clock signal 40. Since the frequency of 53 can be lowered by placing the frequency divider 311, the frequency of the reference clock signal 40 externally applied can also be lowered, and problems of high frequency operation such as noise and power consumption can be alleviated.

The charge pump and loop filter 313 shown in FIG. 3 function as a circuit for producing the control voltages 30 and 31 from the output of the phase comparator 312.

In FIG. 3, voltage controlled oscillators 301 to 309
1 is composed of 9 stages of inverter circuits similar to the delay circuit 300 of the circuit of FIG. 1, which is about twice the number of stages of the inverter circuits of the delay circuit 300 of FIG. The oscillation cycle of the voltage controlled oscillators 301 to 309 is the inverter circuit 18
It is the delay time for a step. Also, 301 to 309 are shown in FIG.
Since it is an inverter circuit similar to the delay circuit 300 of FIG. 1, the oscillation cycle of the voltage controlled oscillators 301 to 309 is about four times the delay time of the delay circuit 300 of FIG. If the frequency divider 31
1 outputs a signal having a frequency half that of 52 to 53, the delay time of the delay circuit 300 of FIG. 1, that is, the pulse width of the output signal 20 of the circuit of FIG. 1 is about the cycle of the reference clock signal 40. It becomes 1/8. That is, the pulse width of the output 20 of the circuit of FIG. 1 can be controlled to be constant by adding the reference clock signal 40 having a cycle of eight times the desired pulse width of the output signal 20 of the circuit of FIG.

In the above description, the frequency divider 311 is explained as a 1/2 frequency divider, but not limited to the 1/2 frequency divider, the number of inverter circuit stages of the voltage controlled oscillator can be arbitrarily designed based on the above idea. .

The characteristic of the circuit of FIG.
3 is matched with the frequency of the reference clock signal 40, the delay circuit 300 of the circuit of FIG. 1 and the voltage controlled oscillators 301 to 309 of the PLL circuit are configured by similar inverter circuits, and the control voltage of the voltage controlled oscillator of the PLL circuit is set. 30, 3
1 is used as the control voltage of the delay circuit 300 of the circuit of FIG. 1, the relationship between the number of stages of the voltage controlled oscillators 301 to 309 and the delay circuit 300 of the circuit of FIG. The point is that the delay time can be easily designed.

FIG. 4 shows an example of the phase comparator 312 and charge pump / loop filter circuit 313 of the circuit of FIG.

The operation of the circuit of FIG. 4 will be described. Since the phase comparator 312 itself is a general circuit, detailed description thereof will be omitted.
The essential points of the operation of 312 will be briefly described. When the phase of the output 53 of the frequency divider 311 leads the phase of the reference clock signal 40, a pulse of “L” is output to 55, and 53
When the phase of is delayed from the phase of the reference clock signal 40, the pulse of "L" is output to 54. Since the signal of 55 is inverted by the inverter circuit 323, the PMOS 214 becomes conductive when the phase of 53 is delayed from the phase of 40, and NM when the phase of 53 is advanced from the phase of 40.
OS 113 is conducting. That is, when the phase of 53 is behind the phase of 40, the potential of 57 is high, and when the phase of 53 is ahead of the phase of 40, the potential of 57 is low. The resistors 400 and 401 and the capacitor 500 act as a filter for smoothing the potential of 57.

This 57 potential is applied to the PMOS 215, 244, NMOS
The current mirror circuit composed of 114 and 123 transmits to the control voltages 30 and 31. When the phase of 53 is behind the phase of 40, the potential of 57 becomes high, the potential of 30 becomes low, and the potential of 31 becomes high. As a result, the oscillation frequencies of the voltage controlled oscillators 301 to 309 in FIG. 3 increase,
The delay time of the delay circuit 300 shown in FIG. 1 is reduced. When the phase of 53 leads the phase of 40, the potential of 57 becomes low, the potential of 30 becomes high, and the potential of 31 becomes low.
That is, the oscillation frequencies of the voltage controlled oscillators 301 to 309 in FIG. 3 are low, and the delay time of the delay circuit 300 in FIG. 1 is long. In the steady state, the phase of 53 and the phase of 40 match.

FIG. 5 shows an example of the frequency divider 311 of the circuit of FIG.

The circuit of FIG.
It works as a 1/2 divider that outputs to. The circuit of FIG. 5 includes an inverter circuit 328 and a clocked inverter circuit 21.
6, 217, 115, 116, inverter circuit 329,
330, clocked inverter circuit 220, 221, 1
It operates as a ring oscillator in which seven stages of gate circuits of 19, 120 and inverter circuits 331, 332 are connected in a ring shape, and the oscillation frequency thereof is controlled by control clock signals 60, 61 of the clocked inverter circuit. Since the circuit of FIG. 5 is similar to the circuit of FIG. 17 described later, detailed operation will be described with reference to FIG. 17, and only the main points will be described here. When the oscillation output of the voltage controlled oscillator of FIG. 3 is added to 52, signals in phase and in phase with 52 are obtained in 60 and 61, respectively. The signal of 53, which is the inversion of the signals of 64 and 64, is one cycle change of the signals of 60 and 61, that is,
It changes at a rate of once for the change of 52 1 cycle,
It functions as a 1/2 frequency divider that outputs to the 53 the frequencies of 60 and 61, that is, the frequency of 1/2 of the frequency of 52.

FIG. 6 is a diagram showing the effect of the circuits of FIGS. 1, 3, 4, and 5 of the present invention. The pulse width of the output signal 20 of FIG. 1 and the fluctuation of the power supply voltage when these circuits are combined. , The temperature variation and the manufacturing variation are compared with the conventional circuit. If the power supply voltage is 2.0V to 3.0V, the temperature is 0 ° C to 100 ° C, and the drain current of the MOS transistor fluctuates ± 10% from the standard value as an example of manufacturing variation, the output signal 20 The maximum pulse width of the conventional circuit is about 1.37ns and the minimum value is about 0.86n.
In the circuit of the present invention, the maximum value is about 1.34 ns, the minimum value is about 1.13 ns, and the fluctuation width is 0.21 ns, while the fluctuation width is 0.51 ns. Further, the maximum value of the pulse width of the output 20 is about 1.4n in both the conventional circuit and the circuit of the present invention.
Since s, the minimum cycle times are almost equal, but
It can be seen that the minimum value of the pulse width of the output 20 is 1.31 times that of the conventional circuit in the circuit of the present invention, that is, the operation margin is improved as described in FIG.

FIG. 7 shows a block diagram of a memory circuit using a self-reset circuit capable of controlling the pulse width to a constant value according to the present invention (a self-reset circuit is used in the portion labeled "self-reset circuit" in the figure).

The self-reset circuit shown in FIG.
By using the decoding circuits 701 and 703 and the address buffer circuit 704 as described above, the access time can be shortened by the self-reset circuit, and the pulse width of the signal of the self-reset circuit can be controlled to be constant, so that stable operation is possible. Can be realized. Since the self-reset circuit is used for the decode circuit and the address buffer circuit, the signal of the decode circuit (for example, the input signal 10 of FIG. 10, the output signal 82 of the address buffer circuit), the word line (87 of FIG. 11),
The signal on the column selection line (25 in FIG. 11) is a pulse signal, but is a normal signal except that the signal is a pulse and a circuit for controlling the pulse width of the signal of the self-reset circuit to be constant. It can be designed like a static memory circuit.

The clock signal 40 shown in FIG. 7 represents a reference clock signal for determining the timing of fetching the address signal and performing the synchronous operation. In the circuit of FIG. 7, not only the internal clock signal 81 for determining the timing of fetching the address signal 80 into the address buffer is generated from the clock signal 40, but also the voltages 30 and 31 for controlling the delay of the delay circuit of the self-reset circuit are generated. The example which occurs is shown.

A feature of the memory using the self-reset circuit of FIG. 7 as a decoding circuit is that not only the timing of fetching the address signal by the clock signal 40 is determined, but also P
Clock signal 40 and PL by installing LL circuit
The point is that voltages 30 and 31 for controlling the delay of the delay circuit of the self-reset circuit are also generated from the L circuit.

FIG. 8 shows an example of the generation circuit 705 of the internal clock signal 81 of the memory of FIG. 7 of the present invention, and FIG. 9 shows its operation waveform.

In the circuit of FIG. 8, the PMOS 232 is used for speeding up.
Has a gate width sufficiently smaller than that of the NMOS 153. For example, the gate width ratio is designed to be 1:10. Also, 620,6
Reference numerals 21 and 622 denote inverter circuits whose delay time is controlled by the same voltages of 30 and 31 as 618, and operate similarly to the delay circuit 300 of FIG. As shown in FIG. 7, the following measures are taken to make the address buffer circuit 704 that takes in the address signal 80 by the internal clock signal 81 a self-reset circuit. In order to use the self-reset circuit for the address buffer circuit 704, the external clock signal 4
0 to a narrow internal clock signal 8 independent of the operating frequency of the memory (frequency of the external reference clock signal 40)
1 (because, for example, using the circuit of FIG. 1 as an example, the input signal 10 changes from “H” to “L” at the time when the reset pulse 50 changes from “H” to “L”.
This reset pulse 50
The time at which is changed from "H" to "L" is determined by the delay circuit 300 independently of the cycle of the external clock signal 40, and thus a signal having a pulse width that does not depend on the frequency of the external clock signal 40 is required. Is because).

FIG. 8 shows an example of generating an internal clock signal 81 from an external clock signal 40 and a delay signal 90 having a reverse phase of the external clock signal 40 in a NAND circuit. Further, the circuit of FIG. 8 has the timing (40
Address signal 8 at the time when "H" changes to "L")
It operates to output a pulse of "L" to 81 in order to take 0 into the memory.

The operation will be briefly described with reference to FIG. 40
Changes from "L" to "H", the NMOS 153 becomes conductive,
81 becomes "L". Inverter circuits 619, 618, 620, and 6 from the time when 40 changes from "L" to "H".
When the delay time of 21,622 has elapsed, the delay signal 90 changes from "H" to "L". PM when 90 becomes "L"
Since the OS 233 becomes conductive, 81 becomes “H”. NAND
Assuming that the delay times of the circuits 232, 233, 153, 154 and the delay time of the inverter circuit 619 are substantially equal, the pulse width of the internal clock signal 81 is approximately 618, 62.
The delay time is 0,621,622. This 618,62
The delay time of 0, 621, 622 is 3 as in the circuit of FIG.
The internal clock signal 8 is controlled by the constant control of 0 and 31.
The pulse width of 1 can be made constant.

The circuit of FIG. 8 is characterized in that it is a NAND circuit and delay signals 90 to 40 of opposite phase to the external clock signals 40 and 40.
The internal clock signal 81 having a narrow width independent of the frequency is generated, and the pulse width of 81 is controlled to be constant at 30 and 31. In FIG. 8, an example in which a pulse is generated at the output when the external clock signal 40 rises has been described, but a circuit that generates a pulse at the output when the external clock signal 40 falls can be easily configured by the same idea.

FIG. 10 shows an example of the address buffer circuit of the memory of FIG. 7 of the present invention.

In the circuit of FIG. 8, the external clock signal 40
To generate a pulse on the output at the rising edge of
Although the gate width of S 232 is designed to be smaller than that of the NMOS 153, in the address buffer circuit of FIG.
The inverter composed of 234 and NMOS 155 outputs a pulse changing from "L" to "H" to "L" at 86 at the falling timing of the internal clock signal 81. Therefore, in order to speed up the inverters 234 and 155, PM
Design the gate width of OS 234 to be sufficiently larger than that of NMOS 155. Similarly, the NAND circuits 235, 236, 15
7, 158 outputs a pulse changing from “H” to “L” to “H” at 82 at the rising timing of 86 when the output of the inverter 606 is “H”. The gate width of 236 is small, NMOS 157,
The gate width of 158 is designed to be large. Reference numerals 604 and 605 denote delay circuits whose delay time is controlled by the voltages of 30 and 31 similar to 300 in FIG. 1, and 608 an inverter circuit similar to 607.

The operation of the circuit of FIG. 10 will be briefly described. The address signal 80 is fixed before the external clock signal 40 changes from "L" to "H"("H" or "L").
Specified in). When the external clock 40 changes from “L” to “H”, the internal clock 81 changes from “H” to “L”,
6 changes from "L" to "H". If 80 is "L", 82 changes to "L". 86 is "L" to "H"
When the delay time of the delay circuit 604 elapses from the time when the change occurs to 91, 91 changes from “L” to “H” and the NMOS 156 becomes conductive. In the circuit of FIG. 8, the pulse width of 81 is the inverter circuit 4
Since the delay time of the stages 618, 620, 621 and 622 is limited, at the time when the NMOS 156 becomes conductive, 81 changes from “L” to “H” and the PMOS 234 becomes non-conductive. ing. Since the PMOS 234 becomes non-conductive and the NMOS 156 becomes conductive, 86 returns from "H" to "L".

From the time when 82 changes to "L",
When the delay time of the delay circuit 605 elapses, 92 changes to "L" and 82 is charged (reset) to "H". NAND
The address signal 8 is input to the circuits 235, 236, 157 and 158.
By preparing the circuit of FIG. 10 for applying the inverted signal of 0 and the circuit for applying the non-inverted signal of the address 80 to the NAND circuit, complementary pulse signals corresponding to the inverted signals of the address signals 80 and 80 can be obtained. This pulse signal (82 and its complementary signal) is transferred to the row and column decoders 703 and 701.
By decoding (FIG. 7), the address signal can be decoded. By controlling the delay times of the delay circuits 604 and 605 with the voltages of 30 and 31, the same effect as that of the circuit of FIG. 1 can be obtained.

The output signal 10 (inverted signal of 82) of the circuit of FIG. 10 is decoded by the circuit of FIG.
Is obtained and the word line is selected by decoding 23 with the circuit of FIG. The characteristic of the circuit of FIG. 10 is that the logic of the internal clock 81 and the address signal is created by the NAND circuit, but the concept of the decode circuit and the address buffer circuit of FIG. 10 and FIG. 1 is the logical configuration of an arbitrary CMOS circuit. That is, the logic configuration of the decoding circuit is not limited to the configuration of the embodiment.

FIG. 11 shows an example of a part of the sense circuit, the decode circuit and the memory cell array of the memory of FIG. 7 according to the present invention.
2 shows an example of a sense circuit.

The operation of the circuits of FIGS. 11 and 12 will be described. The output signal 10 (8
2) is decoded by the circuit of FIG. 1 and its output signals 23 and 24 are decoded by the NAND circuit 609. Further, the output signal of 609 is output to the inverter circuit 610.
The word line 87 is selected by inverting with. 609,
When 610 is a normal CMOS circuit, the layout area can be suppressed small. When 609 and 610 are self-reset circuits like the circuit of FIG. 1, they are suitable for high speed operation. The word line 87 is selected by a pulse of "H" (a pulse that changes from "L" to "H" and then to "L"), and the column is selected by selecting the PMOS 238, 239 for column selection. Since it is realized, it is selected by the pulse of "L" (pulse from "H" to "L" and further to "H").
By setting 87 to “H” and the column selection signal 25 to “L”,
The read signal of the memory cell 611 is the bit line 88,
89, PMOS 238, 239, common data lines 32, 33, and first stage sense amplifiers 159, 160, 161
Be transmitted to.

Reference numeral 34 in FIG. 11 indicates an activation signal of the sense amplifier in the first stage. The PMOSs 270, 271, 240 serve as elements for equalizing the sense amplifier outputs 35, 36. The signals of the first-stage sense amplifier outputs 35 and 36 are further amplified by the second-stage sense amplifier 612 and transmitted to 37 and 38. The signals of the second-stage sense amplifier outputs 37 and 38 are amplified to almost the power supply voltage by the latch type sense amplifier composed of 162, 163, 164, 241 and 242 and output to 14. Similar to 34, 39 indicates an activation signal of a latch type sense amplifier, and the PMOS 243 functions as an element for equalization.

The PMOS 244, 245, NMOS 165, 166 and inverter circuits 613, 614 work as a latch circuit for latching the signal of the latch type sense amplifier output 14 and outputting it to the data output terminal 85. Reference numerals 12 and 13 represent signals for controlling the timing of latching the signal of 14. By setting 12 and 13 to “L” and “H”, respectively, the signal of 14 can be transmitted to 613 and 614.
By setting 3 to "H" and "L", respectively, 14 signals can be stored.

FIG. 13 shows an example of a circuit for generating the activation signal 34 of the sense circuit (FIG. 11) of the memory of the present invention. Reference numerals 616 and 617 represent delay circuits having the same configuration as the delay circuit 300 of FIG.

In the circuit of FIG. 11, 34 is set to "H" and set to 1
The timing of activating the sense amplifiers 159, 160, 161 in the stage is as follows: after 87 is "H" and the column selection signal 25 is "L", the signal of the memory cell 611 is the bit lines 88, 89 and columns. The first stage sense amplifier 159, through the select PMOS 238, 239 and the common data lines 32, 33.
It must be after reaching 160.

The circuit of FIG. 13 is devised as follows in order to stably generate the timing of 34.

The timing for changing the activation signal 34 of the sense amplifier from "L" to "H" is always the column selection signal 2
Since it must be after 5 becomes "L", it is detected that 25 becomes "L" and 34 is raised to "H". In the circuit of FIG. 13, when 25 becomes "L", 28 changes to "H", 93 becomes "H" after the delay time of 616, and 28 returns to "L". 28 changes to “H”, 95 becomes “L”, and the activation signal 34
Becomes "H". The gate width of the NMOS 168 is set to be sufficiently smaller than that of the PMOS 249, as in the circuit of FIG. After the delay time of 617 elapses after 34 becomes "H", 94 changes to "H" and 34 returns to "L". By the way, the common data lines 32 and 33 are shared by several columns, and the bit line pair connected to the common data lines 32 and 33 is not limited to 88 and 89. Therefore, 3
No matter which one of the bit line pairs connected to 2, 33 is selected, the "H" pulse is output to 34, 32, 3
The NAND logic signals of all the column selection signals of the bit line pairs connected to 3 are made at 28.

Reference numerals 26 and 27 in FIG. 13 represent selection signals for bit line pairs other than 88 and 89 connected to 32 and 33. The resistor 406 functions as an element for applying an “L” potential to 28 during standby. Common data line 3
When the number of pairs of bit lines connected to 2, 33 increases, NA
Although the number of column selection signals for which the ND logic has to be created also increases, the NAND circuits 246, 247, 24 of FIG.
By using the NAND circuit as a self-reset circuit as shown in 8, 406, high-speed operation can be realized even if the number of inputs increases. Since the activation time of the sense amplifier can be made constant by controlling the delay time of the delay circuit 617 to be constant at 30 and 31, the operation margin becomes large as in the circuit of FIG.

The circuit of FIG. 13 is characterized in that a self-reset NAND circuit capable of high-speed operation generates a timing for activating a sense amplifier from a column selection signal, so that the sense signal is always sensed after the column selection signal is in the selected state. The characteristics are that the amplifier is activated, and the signal pulse width of the self-reset circuit is controlled to be constant at 30 and 31 to expand the operation margin. In FIG. 13, 34 generation circuits are shown as an example, but the timing of activating 39, 12, 13 and the sense amplifier 612 can be generated in the same way.

FIG. 14 shows another embodiment of the control voltage 30, 31 generating circuit of the present invention. In the circuit of FIG. 3, the control voltage is generated by the PLL circuit, but in the circuit of FIG. 14, the voltage control delay circuit, the phase comparator 312, the charge pump,
The loop filter circuit 313 generates a control voltage.

The operation of the circuit of FIG. 14 will be described. Reference numerals 335 to 344 denote inverter circuits capable of controlling the delay time with the same voltage as the circuits 301 to 309 of FIG. 3, and reference numerals 335 to 344 form a voltage control delay circuit. In the circuit of FIG. 14, the phase comparator 31 is similar to the operation of the circuit of FIG.
2. Control voltages 30 and 31 are determined by the charge pump and loop filter circuit 313 so that the reference clock signals 41 and 53 have the same frequency and phase. This gives 33
The delay times of 5 to 344 are constant regardless of the power supply voltage, temperature, and manufacturing variations, and the delay time of the delay circuit 300 of FIG. 1 is also constant.

In the example of FIG. 14, the number of stages of the voltage control delay circuits 335 to 344 is 10 and an even number.
The signal of the same phase as 41 delayed by a delay time of 344 is transmitted. That is, in order for the frequencies and phases of 41 and 53 to match, the delay time of 335 to 344 must be the cycle time of the reference clock 41. That is, 335
1 to 344, the number of circuit stages of the delay circuit 300 of FIG. 1 and the cycle time of the reference clock signal 41, the delay time of the delay circuit 300 can be designed.

FIG. 14 shows an example in which the number of stages of the voltage control delay circuit is an even number. However, a circuit similar to that of FIG. 14 can be constructed with an odd number of voltage control delay circuits, and the phase of 53 is opposite to the phase of 41. Other than that, the delay time of the delay circuit 300 can be designed in the same way.

The circuit of FIG. 14 differs from the circuit of FIG. 3 in that the input 53 of the phase comparator 312 is a signal obtained by dividing the output of the voltage controlled oscillator in the circuit of FIG. In the circuit, the output of the voltage control delay circuit is used, and the potentials of 30 and 31 are generated with a simpler configuration.

FIG. 15 shows another embodiment of the control voltage 30, 31 generating circuit of the present invention. In the circuits of FIGS. 3 and 14, the control voltage that makes the delay time of the delay circuit 300 constant is generated by matching the phase of the output of the delay circuit or the oscillation circuit with the phase of the reference clock signal. Then, the differential amplifier 334 is used to generate a control voltage by controlling the gate potential of the MOS transistor so that a drain current proportional to the power supply voltage flows.

The operation of the circuit of FIG. 15 will be described. Resistance 40
2, 403 divides the power supply voltage Vcc by resistors. If it is assumed that the resistors 402, 403, and 404 have the same resistance value, the potential of 58 is Vcc / 2. Differential amplifier 3
34 determines the gate voltage of the NMOS 124 so that the voltage drop of the resistor 404 becomes equal to Vcc / 2. In other words, NMOS
The drain current of 124 is proportional to the power supply voltage Vcc. This one
The gate voltage of 24 is supplied as the control voltage 31. The voltage 30 is generated in the current mirror of PMOS 225 and NMOS 125. Therefore, when the voltage 30 is applied to the gate of the PMOS, the drain current of the PMOS is also proportional to Vcc. By the way, the delay time tpd of the CMOS circuit is generally tpd = Vcc
Since it is expressed by × C _L / I _DS , (C _L is the load capacity, I
_DS represents the drain current. ) When the drain current is proportional to the power supply voltage, the delay time tpd does not depend on the power supply voltage. Since the drain current of the MOS of the delay circuit 300 shown in FIG. 1 in which the control voltages 30 and 31 are applied to the gate is proportional to Vcc, the delay time of the delay circuit 300 does not vary with Vcc. Further, the temperature dependence of the resistance values of the resistors 402, 403, and 404 is made smaller than the temperature dependence of the drain current of the MOS, for example, by using a resistance layer having a high impurity concentration, so that the MOS of the delay circuit 300 has The temperature fluctuation of the drain current can also be improved, and the fluctuation of the delay time of the delay circuit 300 due to the temperature can be reduced.

The characteristic of the circuit of FIG. 15 is that the differential amplifier 334 is used.
The resistors 402, 403, 404, and the NMOS 124 generate control voltages 30, 31 so that a drain current proportional to the power supply voltage Vcc flows to the inverter of the delay circuit 300.
This is because the power supply voltage fluctuation and the temperature fluctuation with the delay time of 0 were reduced.

FIG. 16 shows another embodiment in which the self-reset circuit capable of controlling the pulse width of the present invention is applied to the internal clock generation circuit.

In the circuit of FIG. 8, a circuit for generating the internal clock signal 81 by a simple NAND circuit is shown, but the falling timing of 81 (timing of fetching the address signal) is the rising timing of the external clock signal 40. It is one step behind the gate. 81 has a large load capacity,
When the delay is large, it is possible to match the falling timing of 81 with the falling timing of the external clock signal 40 in the circuit of FIG. 16 (in the circuit of FIG. 8, the rising edge of the external clock signal 40). 16 functions as a circuit for fetching the address signal 80, while the circuit of FIG. 16 functions as a circuit for fetching the address signal 80 at the falling timing of the external clock signal 40).

The operation of the internal clock signal 81 generation circuit of FIG. 16 will be described. Reference numerals 707 to 710 in FIG. 16 function as an inverter circuit that can control the delay time by voltage.
Reference numerals 2 and 43 represent control voltages for the delay time. The external clock 40 is added to 707, 707 to 710.
Is transmitted to 44 with a delay of. PMOS 254, 255, N
MOS 174 and 175 act as a NAND circuit similar to the circuit of FIG. 8 and are inverted by inverters 715 to 719.
It creates 4 delayed signals and 44 NAND logic. As a result, a narrow pulse that does not depend on the frequency of the external clock 40 is obtained. The inverters 256, 176 and the inverters 257, 178 serve as NAND circuits 254, 255, 17
It functions as a buffer circuit that buffers the outputs of 4,175. The gate widths of 254, 176 and 257 are designed to be small, as described in the description of the other embodiments. 714
Represents a delay circuit having the same configuration as 300 in FIG.
The delay circuit 714 whose delay time is controlled by 30, 31 makes the pulse width of the internal clock 81 almost constant.
Frequency divider 711 for dividing internal clock 81 and external clock 40
Are divided by (45, 46) and compared by the phase comparator 712 (4
7 and 48), and the charge pump and loop filter circuit 713 generates the control potentials 42 and 43 of the voltage control delay circuits (707 to 710). Similar to the circuits of FIGS. 14 and 3, the potentials of 42 and 43 are determined so that the phases of 40 and 81 coincide with each other. The phase comparator 712, the charge pump and the loop filter circuit 713 may be any circuit that has the same function as the circuit of FIG.

The following measures have been taken to reduce power consumption. NAND circuits 254, 255, 174, 175 that limit the pulse width to four gate circuit (inverter circuit) stages
Is placed before the buffer circuits 256, 176, 257, and 178, the gate width of 174 and 175 can be designed to be smaller than the gate width of 178, for example, about 1/10. That is, the gate capacitance of 175 is smaller than the gate capacitance of 178, and the charge / discharge power of the gate capacitance of the NMOS is smaller than that in the case where the NMOS is connected in series to 178 to limit the pulse width of 81. Therefore, lower power consumption is achieved as compared with the case where an NMOS is connected in series to 178 to limit the pulse width of 81.

The circuit of FIG. 16 is characterized in that the frequency divider 711, the phase comparator 712, the charge pump and loop filter circuit 713, and the voltage controlled delay circuits (707 to 710) match the phases of 40 and 81. The output 44 of the voltage control delay circuit (707 to 710) is used to reduce power consumption.
The pulse width of the signal of the NAND circuit 254, 255, 17
4, 175, the gate circuit (inverter circuit) is limited to four stages, and then the buffer circuits 256, 176, 257, 17
81 was generated in 8 and the pulse width of 81 was set to the control voltage 3
This is a constant control at 0 and 31. In FIG. 16, 4
Although an example in which 0 is added to the voltage controlled delay circuits (707 to 710) has been shown, the same operation can be obtained by replacing the voltage controlled delay circuit with a voltage controlled oscillator as shown in FIG.

FIG. 17 shows an example of the frequency divider 711 of the circuit of FIG. 16, and FIG. 18 shows operation waveforms. The circuit of FIG. 17 corresponds to that of FIG.
It works as a 1/2 divider like the circuit of. The circuit of FIG. 17 also includes a clocked inverter 350, an inverter 351,
352, clocked inverter 354, inverter 35
It operates as a seven-stage ring oscillator of 6, 357 and 358, and its oscillation frequency is controlled by the control clock signals 40 and 3 of the clocked inverter.

The operation of the circuit of FIG. 17 will be described with reference to FIG. By adding the external clock 40 to the inverter 349, a signal having a phase opposite to that of 40 is obtained at 3. Further, by adding the internal clock 81 to the inverter 364, a signal having a phase opposite to that of 81 is obtained at 4. 350 and 359 are 40
When (/ φ1, / represents negation) is “L” and 3 (φ1) is “H”, it is transparent (through, transparent state, the state where the output signal changes in response to the input signal,
Hereinafter referred to as transparent. ) State, 40
When (/ φ1) is “H” and 3 (φ1) is “L”, opaque (opaque, data holding state, state in which the potential of the output signal is not influenced by the input signal is referred to as opaque hereinafter). It represents a clocked inverter that is in a state. For 353 and 354, 40 (/ φ1) is “H”, 3
The clocked inverter is in a transparent state when (φ1) is “L”, and in an opaque state when 40 (/ φ1) is “L” and 3 (φ1) is “H”. Similarly, 360 is in a transparent state when 81 (/ φ2) is “L” and 4 (φ2) is “H”, and when 81 (/ φ2) is “H” and 4 (φ2) is “L”. Is a clocked inverter that becomes an opaque state, and 363 is 81 (/ φ2) is “H”, 4 (φ
When 2) is “L”, it is in the transparent state, 81
It represents a clocked inverter that is in an opaque state when (/ φ2) is “L” and 4 (φ2) is “H”.

In the first state, 5 is "H" and 6 is "H".
I will explain. Since 5 is "H" and 6 is "H", the input of the inverter 351 is "H" and the input of the inverter 356 is "L". 40 is "L" from this state,
When 3 becomes "H", the clocked inverter 350 becomes transparent, so that the output of 350 becomes "L" and 6 also changes to "L". Since the same signal as 6 is obtained in 45, 45 also becomes "L". At this time, since the clocked inverter 354 is in the opaque state, the input of the inverter 356 does not change from the "L" state, and 5 also keeps "H". Next, when 40 becomes "H" and 3 becomes "L", the clocked inverter 354 becomes transparent and the clocked inverter 350 becomes opaque, so that the output of the clocked inverter 354 (input of the inverter 356) becomes "L". Changes from "H" to "H", and 5 also changes from "H" to "L". When 5 goes to "L", 40 goes to "L", and 3 goes to "H", the output of the clocked inverter 350 and 6 go from "L" to "H".
Changes to. Repeating this operation, the potential of 6,45 is 4
It changes at a rate of once with respect to one cycle change of 0 and 3. Eventually, the frequency of 1/2 of 40 is output to 45
Work as a frequency divider by two.

The clocked inverter 360 transmits the signal of 5 to 46 when 81 is "L" and 4 is "H". Since the frequencies of 81 and 40 are the same as shown in FIG. , 81 and 40, which is half the output frequency. At the time when 45 changes, 40 is "H"
From the time when it changes from "L" to "L", the time when 46 changes is the time when 81 changes from "H" to "L". Therefore, by comparing the phases of 45 and 46, 40
And 81 can be compared in phase.

The feature of FIG. 17 is that the external clock signal 40 and the internal clock signal 8 are added by adding a simple additional circuit (latch circuits 360, 361, 363) to the frequency divider of FIG.
The point is that a circuit that simultaneously divides 1 is realized.

FIG. 19 shows another embodiment of the self-reset circuit according to the present invention, which can control the pulse width to be constant.

In 300 of FIG. 1, an example of a delay circuit in which MOS transistors having control potentials 30 and 31 added to their gate electrodes are connected in series to an inverter circuit is shown. However, as shown in FIG. MOS transistor 2 in which control potentials 30 and 31 are applied to the output to the gate electrodes
It is also possible to form delay circuits (721 to 724) in which 02 and 102 are connected and used as transfer gates. In this case, it is desirable that the voltage controlled oscillator of the PLL circuit also has a similar circuit.

[0105]

According to the present invention, by controlling the delay time of the delay circuit that generates the reset pulse of the self-reset circuit to be constant, the pulse width of the signal of the self-reset circuit can be controlled to be constant, and the operation margin can be reduced. Big high speed CMOS
A circuit can be realized. When compared under the condition that the maximum pulse width of the signal is constant, the minimum pulse width of the signal can be increased by about 30% as compared with the conventional circuit. Since the delay time of the delay circuit that generates the reset pulse is only controlled to be constant, the high speed of the self-reset circuit is not impaired.

Further, a delay circuit for generating a reset pulse of the self-reset circuit is connected in series with a C including MOS.
Since the delay is controlled by controlling the gate potential of one of the MOSs formed by a MOS gate circuit and connected in series, the delay time can be controlled with a simple circuit configuration. Further, since only the capacitive load is connected to the delay time control terminal, the control signal generating circuit is not required to have a large current driving capability, and the control accuracy can be easily improved.

Further, the delay circuit of the self-reset circuit and the voltage controlled oscillator of the PLL circuit are configured by the same circuit, and the control potential of the delay time is set as the control voltage of the voltage controlled oscillator of the PLL circuit. Moreover, the delay circuit of the self-reset circuit and the number of stages of the voltage controlled oscillator of the PLL circuit can be easily designed.

According to the memory circuit of the present invention, since decoding time is shortened, high speed access is possible. Also,
Since the signal skew operation margin of the decoding circuit is large, it is possible to operate in a high speed cycle. Since the delay time of the delay circuit of the self-reset circuit can be controlled by the clock signal that determines the timing of fetching the address signal into the memory, it is not necessary to add a special clock signal for controlling the delay time of the delay circuit of the self-reset circuit.

According to the synchronizing circuit of the external clock signal and the internal clock signal of the memory of the present invention, the phases of the external clock signal and the internal clock signal can be matched, and the power consumption in the internal clock signal generating circuit is reduced. It can be reduced.

Further, according to the frequency divider of the present invention of the synchronizing circuit for the external clock signal and the internal clock signal, the external clock signal and the internal clock signal can be simultaneously divided by a simple circuit.

[Brief description of drawings]

FIG. 1 is a self-reset circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the circuit of FIG.

FIG. 3 is a delay time control voltage generation circuit diagram of the present invention.

FIG. 4 is a circuit diagram of the phase comparator and loop filter of FIG.

5 is a frequency divider circuit diagram of FIG. 3;

FIG. 6 is an explanatory view showing the effect of the present invention.

FIG. 7 is a block diagram of a memory showing an embodiment of the present invention.

FIG. 8 is a diagram of an internal clock generation circuit of a memory showing an embodiment of the present invention.

9 is an operation waveform diagram of the circuit of FIG.

FIG. 10 is an address buffer circuit diagram of a memory showing an embodiment of the present invention.

FIG. 11 is a sense circuit diagram suitable for the circuit of the present invention.

FIG. 12 is a sense circuit diagram suitable for the circuit of the present invention.

FIG. 13 is a circuit diagram of a sense amplifier activation signal generating circuit of a memory showing an embodiment of the present invention.

FIG. 14 is an explanatory diagram showing another embodiment of the delay time control voltage generating circuit of the present invention.

FIG. 15 is an explanatory diagram showing another embodiment of the delay time control voltage generating circuit of the present invention.

FIG. 16 is an internal clock generation circuit diagram of a memory showing an embodiment of the present invention.

FIG. 17 is an explanatory diagram showing an example of the frequency divider circuit of FIG. 16.

FIG. 18 is an operation waveform diagram of the circuit of FIG.

FIG. 19 is a self-reset circuit diagram showing an embodiment of the present invention.

[Explanation of symbols]

10, 11, 21, ... Signal input, 20, 22, 23, 24
... signal output, 30, 31 ... delay time control voltage, 50 ... delay signal, 100 series ... NMOS transistor, 200 series ... PMOS transistor, 300 ... delay circuit, 400
Series ... Resistance, 600, 602 ... Self-reset inverter circuit that outputs low level pulse.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H03L 7/06 A

Claims (3)

[Claims] 1. A drain electrode of a first MOS transistor is connected to a first output of a first CMOS circuit, which is composed of an NMOS transistor and a PMOS transistor, and has a gate electrode to which a first input signal is applied. 1 MOS
The source electrode of the transistor is connected to the first power supply and
In a circuit for adding a signal in phase with the first output signal and delayed by a predetermined time to the gate electrode of the MOS transistor of
The gate signal of the first MOS transistor is generated by a first delay circuit including a first output signal as an input, and the delay time of the first delay circuit is controlled by a first control signal,
The first control signal is set such that the delay time of the first delay circuit does not depend on power supply voltage fluctuations, temperature fluctuations, and manufacturing variations, and the first control signal generation circuit generates the first control signal. And a semiconductor integrated circuit. 2. The first delay circuit according to claim 1, wherein the first delay circuit comprises an even number of stages of CMOS gate circuits.
In order to make the delay time of the delay circuit constant, the one CMOS gate circuit of the even-numbered CMOS gate circuits includes a second MOS transistor and a third MOS transistor, and the second MOS transistor Third MOS above
The transistors are connected in series, the first control signal is applied to the gate electrode of the second MOS transistor, and the CM of the previous stage is applied to the gate electrode of the third MOS transistor.
A semiconductor integrated circuit to which the output of the OS gate circuit or the first output signal is added. 3. The first control signal generating circuit according to claim 1, comprising a phase comparator, a low pass filter and a voltage controlled oscillator, wherein the phase of the output of the voltage controlled oscillator and the phase of the reference clock signal. And a semiconductor integrated circuit that functions as a PLL circuit that matches the phase of the output of the voltage controlled oscillator with the phase of the reference clock signal and that uses the control potential of the oscillation frequency of the voltage controlled oscillator as the first control signal.