US6185129B1 - Power reset circuit of a flash memory device - Google Patents
Power reset circuit of a flash memory device Download PDFInfo
- Publication number
- US6185129B1 US6185129B1 US09/468,934 US46893499A US6185129B1 US 6185129 B1 US6185129 B1 US 6185129B1 US 46893499 A US46893499 A US 46893499A US 6185129 B1 US6185129 B1 US 6185129B1
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- United States
- Prior art keywords
- node
- voltage
- output
- level
- reset circuit
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Links
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
Definitions
- the present invention relates to a power reset circuit of a flash memory device.
- the present invention relates to a power reset circuit of a flash memory device which can feed back the output of the power reset circuit to remove a standby current, thus improving the integration degree of a device.
- respective components of the device Upon an initial operation of the flash memory device, respective components of the device has to maintain an initial set value so that they can perform a normal operation. Therefore, in the operation of the flash memory device, it is important to initiate (or reset) the device.
- the power reset circuit performs the finction of initializing the device.
- the standby current of the flash memory device is limited within about 5 ⁇ A. Therefore, upon power-up, after the devices are initialized, the power reset circuit does not have to consume any current.
- a conventional power reset circuit will be explained by reference to FIG. 1 .
- FIG. 1 is a circuit diagram for illustrating a conventional power reset circuit.
- a delay section 11 for delaying the increase of the supply voltage is connected between the supply terminal Vcc and the first node K 1 , and a fourteenth NMOS transistor N 14 the gate of which is connected to the first node K 1 is connected between the first node K 1 and tie supply terminal Vcc.
- a plurality of PMOS transistors P 101 to P 112 the gates of which are connected to the ground terminal Vss, respectively, are serially connected between the supply terminal Vcc and the second node K 2
- a plurality of PMOS transistors P 113 to P 132 the gates of which are connected to the ground terminal Vss, respectively, are serially connected between the second node K 2 and the third node K 3
- a first capacitor C 1 consisted of NMOS transistors is connected between the third node K 3 and the ground terminal Vss.
- a resistor R is connected between the fourteenth NMOS transistor N 14 and the fourth node K 4 and a fifteenth transistor N 15 the gate of which is connected to the fourth node K 4 , is connected between the fourth node K 4 and the supply terminal Vcc.
- first and second inverters 12 and 13 are connected between the supply terminal Vcc and the ground terminal Vss, respectively.
- a first PMOS transistor P 1 the gate of which is connected to the fourth node K 4
- a PMOS transistor P 2 and a third PMOS transistor P 3 the gate of which is connected to the ground terminal Vss are serially connected between the supply terminal Vcc and the fifth node K 5 .
- the first to fifth NMOS transistors N 1 to N 5 the gates of which are connected to the supply terminal Vcc are serially connected between the fifth node K 5 and the ground terminal Vss.
- a fourth PMOS transistor P 4 the gate of which is connected to the fourth node K 4
- a fifth PMOS transistor PS the gate of which is connected to the ground terminal Vss are serially connected between the supply terminal Vcc and the sixth node K 6 .
- Seventh to ninth NMOS transistors N 7 to N 9 the gates of which are connected to the fifth node K 5 are connected between the sixth node K 6 and the ground terminal Vss.
- the sixth NMOS transistor N 6 the gate of which is connected to the fifth node KS is connected the supply terminal Vcc and the fifth node K 5
- a second capacitor C 2 consisted of the NMOS transistors is connected between the fifth node K 5 and the ground terminal Vss.
- the first to sixth inverters I 1 to I 6 are serially connected between the sixth node and the output terminal PURST
- a third capacitor C 3 consisted of the PMOS transistors is connected between the supply terminal Vcc and the sixth node K 6 .
- tenth to thirteenth NMOS transistors N 10 to N 13 the gates of which are connected to the fourth node K 4 , respectively, are serially connected between the sixth node K 6 and the ground terminal Vss.
- NMOS transistors N 7 to N 9 gates of which are connected to the fifth node K 5 are connected between the ground terminal and the sixth node K 6 .
- the operation of the power reset circuit constructed as above may be explained by dividing three steps as the supply voltage thereof increases from 0V to Vcc slowly.
- the voltage level of the fourth node K 4 being an input terminal of the first inverter I 1 is maintained at low level.
- the first PMOS transistor P 1 is turned on and the supply voltage is applied to the fifth node K 5 via the second and third PMOS transistors P 2 and P 3 .
- the first to fifth NMOS transistors N 1 to N 5 are kept turned off.
- the fourth PMOS transistor P 4 will be turned on by the voltage level of the fourth node K 4 being an input terminal of the second inverter I 2 , and thereby the supply voltage is applied to the sixth node K 6 via the fifth PMOS transistor P 5 . Then, as the voltage level of the sixth node K 6 is higher than that of the fifth node K 5 , the seventh to ninth NMOS transistors N 7 to N 9 are kept turned off Also, as the voltage level of the supply voltage is at low level, the sixth node K 6 is kept at a low level. Accordingly, a low level of voltage is outputted via the output terminal PURST.
- the first and fourth PMOS transistors P 1 P 4 will be turned off and the tenth to thirteenth AMOS transistors N 10 to N 13 will be turned on, thus making the sixth node K 6 a low level. Therefore, the operation of the first and second inverters I 1 and I 2 will stop and a low level of voltage will be outputted via tle output terminal PURST, thus stopping the initial operation.
- the fourteenth and fifteenth NMOS transistors N 14 and N 15 are consisted of transistors having a low threshold voltage, i. e, about 0.3V than a different transistor. In this case, if the supply voltage is lowered to 0V, it functions to lower the voltage level of the fourth node K 4 to 0V.
- the delay section 11 for delaying the increase of the supply voltage upon power-up is consisted of a plurality of PMOS transistors P 101 to P 132 and a capacitor C 1 , the area in which the power reset circuit occupies in the flash memory device is large. Also, if the power-up time is too long, the delay section 11 does not operate corresponding to the long power-up time.
- the power reset circuit of the flash memory device is characterized in that it comprises a first bootstrap circuit for raising the voltage level of a first node into a higher level upon a power-up; a latch means for inverting the voltage level of said first node; a voltage detector operable depending on the output of said latch means, for outputting a low level or a high level of signal depending on the level of the supply voltage; a second bootstrap circuit for raising the voltage level of a second node into a higher level upon a power-up; a delay means for delaying and outputting the voltage level of said second node; a transfer means operable depending on the output of said delay means, for transferring the output of said voltage detector; and a feedback means for feedbacking the output of said voltage detector to said first node and said second node.
- FIG. 1 is a circuit diagram for illustrating a conventional power reset circuit
- FIG. 2 is a circuit diagram for illustrating a power reset circuit according to the present invention.
- FIGS. 3 and 4 are graphs for illustrating the output voltages of each of the nodes depending on the power-up time of the power reset circuit according to the present invention.
- FIG. 2 is a circuit diagram for illustrating a power reset circuit according to the present invention.
- a first bootstrap circuit 21 is connected to a tenth node K 30 and a latch means 200 is connected between the tenth node K 30 and the first node K 21 , wherein the latch means 200 is consisted of serially connecting a first inverter 26 , a second inverter 22 and a sixteenth inverter I 16 of a third inverter.
- the first inverter 26 is consisted of serially connecting the thirteenth to fifteenth inverters I 13 to I 15 .
- the sixth inverter I 6 is connected between the eleventh node K 31 and the twelfth node K 32 , and a sixth NMOS transistor N 26 the gate of which is connected to the twelfth node K 32 is connected between the eleventh node K 31 and the thirteenth node K 33 .
- a fourth PMOS transistor P 24 the gate of which is connected to the twelfth node K 32 is connected between the supply terminal Vcc and the thirteenth node K 33
- a pair of latches consisted of a pair of inverters I 7 ad I 8 and the sixteenth inverter I 16 is connected between the thirteenth node K 33 and the first node K 21 .
- a voltage detector 23 for outputting a high level of voltage below a given voltage is connected between the supply terminal Vcc and the ground terminal Vss.
- the first PMOS transistor P 21 the gate of which is connected to the first node K 21 being an input terminal of the voltage detector 23 is connected between the supply terminal Vcc and the second node K 22 . Also, the first resistor R 1 and the first NMOS transistor N 21 is serially connected between the second node K 22 and the ground terminal Vss, while the second NMOS transistor N 22 and the second resistor R 2 are serially connected.
- the second PMOS transistor P 22 the gate of which is connected to the third node K 23 is connected between the second node K 22 and the third node K 23
- the third PMOS transistor P 23 the gate of which is connected to the third node K 23 is connected between the second node K 22 and the fourth node K 24
- a third NMOS transistor N 23 the gate of which is connected the connecting point of the first resistor R 1 and the first NMOS transistor N 21 is connected between the third node K 23 and the fifth node K 25
- a fourth NMOS transistor N 24 the gate of which is connected the connecting point of the second NMOS transistor N 22 and the second resistor R 2 is connected between the fourth node K 24 and the fifth node K 25
- a fifth NMOS transistor N 25 the gate of which is connected the connecting point of the first resistor R 1 and the first NMOS transistor N 21 is connected between the fifth node K 25 and the ground node Vss.
- a transfer means 300 is connected between the fourth node K 24 and the output terminal VOUT, wherein the transfer means 300 includes a first delay means I 17 and I 18 , a fourth inverter 24 consisted of a transfer transistor T 1 and a latch, and a nineteenth inverter I 19 being the fifth inverter.
- the transfer transistor T 1 is connected between the first delay means 27 and the seventh node K 27 .
- the transfer transistor T 1 is consisted of a NMOS transistor and a PMOS transistor, wherein the gate of the NMOS transistor is connected to the sixth node K 26 and the gate of the PMOS transistor is connected to the inverter I 1 for level-shifting the voltage level of the sixth node K 26 .
- a latch circuit is connected between the seventh node K 27 and the output terminal, wherein the latch circuit includes a pair of inverters I 2 and I 3 connected in parallel.
- the output of the voltage detector 23 is feedbacked to the eighth node K 28 via the second delay means (feedback means 28 ).
- the third delay means 25 is connected between the eighth node K 28 and the sixth node K 26 .
- the fourth inverter I 4 is connected between the eighth node K 28 and the ninth node K 29 , which inverts the voltage level of the fourth node K 24 that is delayed in a given time by the ninth to the twelfth inverters I 9 to I 12 .
- a capacitor C 21 consisted of NMOS transistors is connected between the ninth node K 29 and the ground terminal Vss.
- the fifth inverter I 5 is connected between the ninth node K 29 and the sixth node K 26
- the second capacitor C 22 is connected between the sixth node K 26 and the ground terminal Vss.
- a second bootstrap circuit 29 is connected between the eighth node K 28 and the fourteenth node K 34 , and a twelfth and twenty first inverters I 20 and I 21 are connected between the fourteenth node K 34 and the tenth node K 30 .
- the tenth node K 30 upon a power-up, the tenth node K 30 is raised to a high level by the first bootstrap circuit 21 , and the latch means 300 latches the voltage level of the tenth node K 30 .
- the voltage detector operates depending on the output of the latch means 200 , that is it outputs a high level or a low level signal depending on the supply voltage.
- the voltage level of the fourteenth node upon a power-up, the voltage level of the fourteenth node is made to a high level by the second bootstrap circuit 29 , and the third delay means 25 delays and outputs the voltage level of the fourteenth node K 34 .
- the transfer means 300 operates depending on the output of the third delay means 25 , and the voltage detector 23 transfers it to the output terminal. Also, the output of the voltage detector 23 is feedbacked to the tenth node K 30 and the fourteenth node K 34 by the second delay means (feedback means 28 ).
- the tenth node K 30 Upon a power-up when the supply voltage is applied, the tenth node K 30 is made a high level by the bootstrap operation of the first bootstrap circuit 21 .
- the voltage level of the tenth node K 30 is made a low level via the thirteenth to fifteenth inverters I 13 to I 15 being the fist inverter 26 and is then inputted to the second inverter 22 .
- the voltage level of the first inverter 26 is inverted via the second inverter 22 and is made a low level via the sixteenth inverter I 16 being the third inverter, the voltage level of the first node K 21 becomes a low level.
- the voltage of the eleventh node K 31 is inverted via the sixth inverter I 6 to turn off the fourth PMOS transistor P 24 , while tuning on the sixth NMOS transistor N 26 .
- This is outputted as a high level via an inverting latch consisted of a pair of inverters I 7 and I 8 .
- the voltage detector 23 will operate.
- the voltage detector 23 is constructed so that it outputs a high voltage if it is less than a given voltage but outputs a low voltage if it is more than a given voltage.
- the first PMOS transistor P 21 is turned on so that it can apply a supply voltage the voltage level of which is raised more than a given level. Thereby, the second node K 22 becomes a high level.
- the first, second, third and fifth NMOS transistors N 21 , N 22 , N 23 and N 25 the gates of which are connected to the second node K 22 will be kept turned off. Also, the second and the third NMOS transistors N 22 and N 23 will be kept turned off. On the other hand, as the voltage level of the third node K 23 is kept at low level, the second and third PMOS transistors P 22 and P 23 will be turned on and the fourth node K 24 being the output terminal of the voltage detector 23 will be kept at high level.
- the fourteenth node K 34 becomes a high level by the bootstrap operation of the second bootstrap circuit 29 . Therefore, the eighth node K 28 will have a high level and the third delay means 25 will delay and output the voltage level of the eighth node K 28 .
- the voltage level of the eighth node K 28 causes the voltage level of the ninth node 29 to be low via the fourth inverter I 4 , but the first capacitor C 21 will not be charged.
- the voltage level of the ninth node K 29 is again inverted via the fifth inverter I 5 to make the sixth node 26 high, and thus while the second capacitor C 22 is charged, the output level of the third delay means 25 is delayed by a given time.
- the transfer means 300 operates depending on the output of the third delay means 25 .
- the output voltage of the first delay means 27 is passed via the transfer transistor T 1 to make the seventh node K 27 high. This is latched into a low level by the latches I 2 and I 3 and is inverted via the nineteenth inverter I 19 being the fifth inverter to become a high level, thus it is passed to the output terminal VOUT.
- the output terminal VOUT becomes a high level, the elements within the flash memory are reset (initialized). Also, the output of the voltage detector 23 is feedbacked to the fourteenth node K 34 via the second delay means (feedback means 28 ).
- the second node K 22 of the voltage detector 23 becomes a high voltage, which is a high voltage enough to turn on the first, second, third and fifth NMOS transistors N 21 , N 22 , N 23 and N 25 . Therefore, a current is passed from the supply terminal Vcc to the ground terminal Vss, which causes the fourth node K 24 being the output terminal of the voltage detector 23 to be a low voltage.
- the output voltage of the voltage detector 23 is feedbacked to the fourteenth node K 34 via the second delay means (feedback means 28 ) and is simultaneously passed to the transfer means 300 .
- the eighth node K 28 has a low voltage
- the sixth node K 26 being the output node of the third delay means 25 will become a low voltage, and the transfer transistor T 1 will not operate. Therefore, a low voltage is outputted to the output terminal VOUT to complete the initialization of tle device.
- the third delay means 25 is designed to have enough a latch time so that it can sufficiently delay the output value of the first delay means 27 in the third inverter 24 .
- the eighth node K 28 is maintained at a low voltage
- the tenth node K 30 will become a low voltage.
- the voltage level of the tenth node K 30 is latched and inverted via the latch means 200 and is then passed to the first node K 21 At this time, the voltage level of the first node K 21 becomes a high state.
- the first node K 21 is the input terminal of the voltage detector 23 which it will not stop its operation as it reach a high voltage state. All the current within the voltage detector 23 is passed to the ground terminal Vss and thus any driving current will not flow on
- FIGS. 3 and 4 are graphs for illustrating the output voltages of each of the nodes depending on the power-up time of the power reset circuit according to the present invention.
- FIG. 3 shows the case where the power-up time is 10 ms
- FIG. 4 shows the case where the power-up time is 100 ms.
- the present invention can provide the advantages that it can remove the standby current by feedbacking the output value of the power reset circuit, and also can reduce the layout area of the power reset circuit, thus improving the integration degree of the device
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Abstract
Description
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980060315A KR100296323B1 (en) | 1998-12-29 | 1998-12-29 | Power Reset Circuit of Flash Memory Device |
KR98-60315 | 1998-12-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
US6185129B1 true US6185129B1 (en) | 2001-02-06 |
Family
ID=19567133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/468,934 Expired - Lifetime US6185129B1 (en) | 1998-12-29 | 1999-12-22 | Power reset circuit of a flash memory device |
Country Status (3)
Country | Link |
---|---|
US (1) | US6185129B1 (en) |
JP (1) | JP3647702B2 (en) |
KR (1) | KR100296323B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020021159A1 (en) * | 2000-08-10 | 2002-02-21 | Nec Corporation | Delay circuit and method |
US6430102B2 (en) * | 2000-06-30 | 2002-08-06 | Fujitsu Limited | Semiconductor integrated circuit and method for controlling activation thereof |
US9654096B1 (en) * | 2016-07-19 | 2017-05-16 | Freescale Semiconductor,Inc. | Low variation power-on-reset circuit |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020009702A (en) * | 2000-07-26 | 2002-02-02 | 박종섭 | Power on reset circuit |
KR100514413B1 (en) * | 2000-10-26 | 2005-09-09 | 주식회사 하이닉스반도체 | Circuit for generating a reset signal |
KR100865557B1 (en) * | 2007-06-29 | 2008-10-28 | 주식회사 하이닉스반도체 | Power up initializing circuit |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4746822A (en) | 1986-03-20 | 1988-05-24 | Xilinx, Inc. | CMOS power-on reset circuit |
JPH06296125A (en) | 1993-04-08 | 1994-10-21 | Nec Corp | Power-on reset circuit |
US5455794A (en) * | 1993-09-10 | 1995-10-03 | Intel Corporation | Method and apparatus for controlling the output current provided by a charge pump circuit |
JPH07262781A (en) | 1994-03-22 | 1995-10-13 | Hitachi Ltd | Semiconductor integrated circuit |
JPH08187724A (en) | 1995-01-05 | 1996-07-23 | Toyo A Tec Kk | Blade deflection correcting mechanism for slicing machine and correcting method therefor |
US5552725A (en) | 1994-08-05 | 1996-09-03 | Advanced Micro Devices, Inc. | Low power, slew rate insensitive power-on reset circuit |
US5578951A (en) | 1993-12-10 | 1996-11-26 | Samsung Electronics Co., Ltd. | CMOS circuit for improved power-on reset timing |
JPH09258852A (en) | 1996-03-26 | 1997-10-03 | Sanyo Electric Co Ltd | Reset circuit |
US5778238A (en) | 1996-06-19 | 1998-07-07 | Microchip Technology Incorporated | Power-down reset circuit |
US5898635A (en) | 1995-06-26 | 1999-04-27 | Micron Technology, Inc. | Power-up circuit responsive to supply voltage transients |
US5917255A (en) | 1998-01-20 | 1999-06-29 | Vlsi Technology, Inc. | Power-on-reset circuit having reduced size charging capacitor |
US5930129A (en) | 1997-08-08 | 1999-07-27 | Oki Electric Industry Co., Ltd. | Power on reset circuit |
-
1998
- 1998-12-29 KR KR1019980060315A patent/KR100296323B1/en not_active IP Right Cessation
-
1999
- 1999-12-22 US US09/468,934 patent/US6185129B1/en not_active Expired - Lifetime
- 1999-12-24 JP JP36682699A patent/JP3647702B2/en not_active Expired - Fee Related
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4746822A (en) | 1986-03-20 | 1988-05-24 | Xilinx, Inc. | CMOS power-on reset circuit |
JPH06296125A (en) | 1993-04-08 | 1994-10-21 | Nec Corp | Power-on reset circuit |
US5455794A (en) * | 1993-09-10 | 1995-10-03 | Intel Corporation | Method and apparatus for controlling the output current provided by a charge pump circuit |
US5578951A (en) | 1993-12-10 | 1996-11-26 | Samsung Electronics Co., Ltd. | CMOS circuit for improved power-on reset timing |
JPH07262781A (en) | 1994-03-22 | 1995-10-13 | Hitachi Ltd | Semiconductor integrated circuit |
US5552725A (en) | 1994-08-05 | 1996-09-03 | Advanced Micro Devices, Inc. | Low power, slew rate insensitive power-on reset circuit |
JPH08187724A (en) | 1995-01-05 | 1996-07-23 | Toyo A Tec Kk | Blade deflection correcting mechanism for slicing machine and correcting method therefor |
US5898635A (en) | 1995-06-26 | 1999-04-27 | Micron Technology, Inc. | Power-up circuit responsive to supply voltage transients |
JPH09258852A (en) | 1996-03-26 | 1997-10-03 | Sanyo Electric Co Ltd | Reset circuit |
US5778238A (en) | 1996-06-19 | 1998-07-07 | Microchip Technology Incorporated | Power-down reset circuit |
US5930129A (en) | 1997-08-08 | 1999-07-27 | Oki Electric Industry Co., Ltd. | Power on reset circuit |
US5917255A (en) | 1998-01-20 | 1999-06-29 | Vlsi Technology, Inc. | Power-on-reset circuit having reduced size charging capacitor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6430102B2 (en) * | 2000-06-30 | 2002-08-06 | Fujitsu Limited | Semiconductor integrated circuit and method for controlling activation thereof |
US20020021159A1 (en) * | 2000-08-10 | 2002-02-21 | Nec Corporation | Delay circuit and method |
US7042266B2 (en) * | 2000-08-10 | 2006-05-09 | Nec Electronics Corporation | Delay circuit and method |
US9654096B1 (en) * | 2016-07-19 | 2017-05-16 | Freescale Semiconductor,Inc. | Low variation power-on-reset circuit |
Also Published As
Publication number | Publication date |
---|---|
KR100296323B1 (en) | 2001-08-07 |
KR20000043877A (en) | 2000-07-15 |
JP2000195282A (en) | 2000-07-14 |
JP3647702B2 (en) | 2005-05-18 |
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