KR20020009702A - Power on reset circuit - Google Patents

Abstract

PURPOSE: A power-on reset circuit is provided to control the voltage level of a reset signal by adjusting the number of diodes, to easily embody all the elements on one-chip by forming the elements as active elements, and to minimize consumption current by using only active elements. CONSTITUTION: A plurality of diodes(D1-Dn) are serially connected between a source voltage terminal(Vcc) and a ground side. A PMOS transistor(PM1) and an NMOS transistor(NM1) are connected in parallel to the plurality of diodes(D1-Dn) and are serially connected to each other. An output terminal outputs a power-on reset signal(POR) to a junction of the PMOS transistor(PM1) and NMOS transistor(NM1). If a source voltage is applied through the source voltage terminal(Vcc), the diodes(D1-Dn) are turned on.

Description

Power-On Reset Circuit {POWER ON RESET CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit for adjusting the voltage level of a reset signal by the number of diodes. The present invention relates to a power-on circuit which is easily implemented on a chip by using only active elements and minimizes current consumption. It relates to a reset circuit.

The conventional power-on reset circuit includes a voltage sensing unit for comparing an applied voltage with a threshold voltage, and generating a reset signal that senses the above and generates a reset signal when the voltage is greater than or equal to the threshold voltage. It is made of wealth.

Looking at the prior art configured as described above is as follows.

When the power supply voltage is applied, the power detection unit compares the power supply voltage with the threshold voltage. When the power supply voltage is greater than or equal to the threshold voltage, the power detection unit generates a signal informing the reset signal generator.

Then, the reset signal generator generates a reset signal after a suitable time delay and delivers it to the next stage. Here, the reset signal is made of a resistor or a combination of resistors and capacitors.

Circuits that require the reset signal generated above are required in digital logic circuits, memory circuits, and the like.

However, in the prior art as described above, it is not easy to adjust the time when generating the reset signal or it takes a lot of time to delay the actual chip operation time, and also use a counter for delay. In this case, the circuit becomes more complicated and takes a large area in implementation.

Accordingly, an object of the present invention for solving the above-described conventional problems is to provide a power-on reset circuit for adjusting the voltage level of the reset signal by adjusting the number of diodes.

It is another object of the present invention to provide a power-on reset circuit which is made of all active devices to facilitate implementation on a one-chip.

Another object of the present invention is to provide a power-on reset circuit for minimizing current consumption using only active devices.

1 is a memorial diagram for a power-on reset circuit of the present invention.

Figure 2 is a first embodiment of the power-on reset circuit of the present invention.

FIG. 3 is a diagram illustrating a characteristic change of voltage for each node until power is applied to reach a 5V voltage in FIG. 2.

FIG. 4 is a waveform diagram of a power-on reset signal for the case where the rising rate of power is different in FIG. 2; FIG.

FIG. 5 is a second embodiment of a power-on reset circuit in the case where the connection number of the PMOS transistor of the present invention is connected differently; FIG.

FIG. 6 is a characteristic diagram of voltage change for each node until power is applied to reach a 5V voltage in FIG. 5. FIG.

Fig. 7 is a third embodiment of the present invention power-on reset circuit.

***** Explanation of symbols for the main parts of the drawing *****

P: PMOS transistor N: NMOS transistor

C: Capacitor

To achieve the above object, the present invention provides n diodes connected in series between a power supply terminal and a ground side, PMOS and NMOS transistors connected in parallel with the n diodes in series, and the PMOS and NMOS transistors. Characterized in that the output terminal for outputting a power-on reset signal (POR) to the connection point of the MOS transistor.

The present invention is characterized in that the inverter is connected in two stages for the driving capability in parallel with the PMOS and NMOS transistor.

In the present invention, the diode is characterized in that a plurality of MOSFETs (MOSFET) connected.

Hereinafter, with reference to the accompanying drawings in detail as follows.

1 is a conceptual diagram of a power-on reset circuit of the present invention. As shown in FIG. 1, n diodes D1-Dn connected in series between a power supply voltage terminal and a ground side, and the n diodes D1-Dn are illustrated in FIG. ) Outputs a power-on reset signal (POR) to a connection point of the PMOS and NMOS transistors PM1 (NM1) and the PMOS and NMOS transistors PM1 (NM1) connected in parallel with each other in series. It consists of an output stage.

2 shows an embodiment of the power-on reset circuit of the present invention. As shown therein, n PMOS transistors P1-P6 connected in series with a power supply voltage terminal and the n PMOS transistors P1 are shown in FIG. A first inverter connected in parallel with P6 and connected in series with each other, and a first inverter connected in two stages in parallel with the PMOS and NMOS transistors P7 and N1; It consists of (P8, N2) and the second inverters (P9, N3).

Referring to the operation and effect of the present invention configured as described in detail as follows.

First, when a power supply voltage is applied through the power supply voltage terminal Vcc in FIG. 1, the n diodes D1 -Dn connected in series are turned on. The turn-on voltage of the diode is referred to as vthd, and the turn-on voltage of the NMOS transistor NM1 is referred to as vthd.

At this time, when the NMOS transistor NM1 is turned on, when the PMOS transistor PM1 and the NMOS transistor NM1 become a constant voltage, a power-on reset signal POR is generated. That is, when the turn-on voltage of the diodes D1 -Dn is greater than the turn-on voltage of the NMOS transistor NM1, the NMOS transistor NM1 is turned on to generate a power-on reset signal POR.

The power-on reset signal POR holds the reset signal until the power supply voltage becomes more than vthd x number of diodes + vth.

Referring to FIG. 2, which is an embodiment of a power-on reset circuit operating as described above, is as follows.

When the power supply voltage is applied through the power supply voltage terminal Vcc, the n PMOS transistors P1 to P6 to which the gate and the drain are respectively connected are turned on. As the n PMOS transistors P1-P6 are turned on, the NMOS transistor N1 is turned on or off.

For example, when the turn-on voltage of the PMOS transistor is vthd and the turn-on voltage of the NMOS transistor N1 is vth, the power supply voltage applied through the power supply voltage terminal passes through the n PMOS transistors P1-P6 and the NMOS transistor. When the voltage supplied to the gate of N1 becomes equal to or higher than (vthd x number of diodes + vth), the NMOS transistor N1 is turned on.

At this time, the PMOS transistor P7 connected to the power supply voltage terminal is also turned on.

Accordingly, the PMOS transistor P7 and the NMOS transistor N1 are turned on, respectively, and output a power-on reset signal having a predetermined size through the net015 output terminal.

The power-on reset signal is inverted through an inverter consisting of a PMOS transistor P8 and an NMOS transistor N2, and the inverted power-on reset signal is output through a net068 output terminal.

The inverted power-on reset signal outputted through the net068 output terminal is again converted into an original power-on reset signal (POR) inverted through an inverter consisting of a PMOS transistor P9 and an NMOS transistor N3. Output through

As a result, outputting the power-on reset signal through the two-stage inverters P8 and N2 (P9 and N3) prevents double current consumption as a buffer for driving digitals.

In this state of operation, when the voltage applied through the power supply voltage terminal gradually increases from 0V to 5V, the voltage of the power-on reset signal POR for each node is the same as in FIG. 3, and the rising rate of the power supply voltage (rising rate) The waveforms of the power-on reset signal POR when) are different from each other are shown in FIG. 4.

The PMOS transistor P7 applies the power supply voltage Vcc from the power supply voltage terminal to the net015 output terminal until the power-on reset signal POR drops to zero, thereby applying the power-on reset signal POR to the Vcc voltage. It serves to hold.

In this manner, when the power-on reset signal POR becomes 0, the PMOS transistor P7 turns off and cuts off a path PATH through which current flows, thereby preventing current consumption.

In addition, when the PMOS transistor is configured in the form of a diode and connected, the power-on reset signal POR is generated as shown in FIG.

As described above, both the PMOS transistor and the NMOS transistor are active elements, and the PMOS transistor and the NMOS transistor are easily implemented on one chip.

Since the voltage level of the power-on reset signal is the same regardless of the rate of increase of the power supply voltage, the voltage level is detected regardless of the rate of increase of the power supply voltage to generate a reset signal.

In addition, instead of connecting the PMOS transistors P1-P6 shown in FIG. 2 to each other in series, a current mirror is formed using the first PMOS transistor P1 and the PMOS transistor P22 as shown in FIG. The capacitor C is connected in series with the current mirror.

In this case, the capacitor C is charged up by the power supply voltage after the reset operation is performed, thereby converting the reset signal to zero.

A voltage sensing switch was used to allow the capacitor C to be charged with sufficient supply voltage. In order to match fast power supply, the charging rate of the capacitor is adjusted to ensure the minimum required duration of the reset signal.

As described in detail above, the present invention has the effect of reducing the area by configuring only active elements so that the chip can be easily implemented, and also easily adjusting the voltage generated by the reset by adjusting or removing the number of diodes. In addition, the present invention is configured only with active elements to minimize the current consumption, and since the elements used to detect the voltage level is almost unaffected by the change in the power-up ratio, there is an effect that it operates stably even with the change in the power-up ratio. .

Claims (3)

N diodes connected in series between a power supply voltage terminal and a ground side, PMOS and NMOS transistors connected in parallel with the n diodes in series, respectively, and a power-on reset signal at a connection point of the PMOS and NMOS transistors. A power-on reset circuit comprising an output stage for outputting (POR). The power-on reset circuit according to claim 1, wherein an inverter is connected in two stages for driving capability in parallel with the PMOS and NMOS transistors. The power-on reset circuit according to claim 1, wherein the n diodes use a MOS field effect transistor (MOSFET).