KR19990046939A - Semiconductor memory device - Google Patents

Abstract

An internal power supply voltage generation circuit according to the present invention includes an internal voltage generation circuit that receives an external power supply voltage and generates an internal power supply voltage having a lower level and a constant level than the external power supply voltage according to a level of a first reference voltage; Accepts an external voltage for informing the burn-in test mode, and outputs a high voltage detection signal that detects whether the external voltage is a high voltage having a higher level than the internal power supply voltage, and is activated when the external voltage is high voltage A high voltage detection circuit for outputting a high voltage detection signal; A reference voltage generation circuit connected to the high voltage detection circuit, for converting an external power supply voltage into a second reference voltage when the high voltage detection signal is deactivated, which becomes a reference for internal circuits provided to the semiconductor memory device; A reference voltage converting circuit connected to the reference voltage generating circuit and converting the second reference voltage to a level corresponding to the first reference voltage provided to the internal voltage generating circuit.

Description

SEMICONDUCTOR MEMORY DEVICE

The present invention relates to a semiconductor memory device, and more particularly, to an internal power supply voltage generation circuit for generating an internal power supply voltage of a semiconductor memory device.

1 is a circuit diagram showing an internal power supply voltage generation circuit having a burn-in voltage control circuit according to the prior art. 2 is a diagram illustrating a relationship between an external power supply voltage and an internal power supply voltage according to an operation mode.

In order to minimize the influence of external power supply voltage (hereinafter referred to as EVC) due to the high integration and high performance design of semiconductor memory devices, the use of an internal power supply voltage generating circuit is becoming common. Burn-in tests on chips employing internal power supply voltage generation circuits have been made by the burn-in voltage control circuit of internal power supply voltage generation circuits.

As shown in FIG. 1, the burn-in voltage control circuit 16 has a PMOS having a plurality of diode connections connected between an internal power supply voltage (hereinafter referred to as IVC) and an external power supply voltage (EVC). By using transistors 10 to 14, the burn-in voltage is equal to the threshold voltages Vth corresponding to the transistors 10 to 14 to the internal power supply voltage IVC, respectively. It was set by boosting by (4 * Vtp). Therefore, in order to set the burn-in voltage, a very high external power supply voltage (EVC) must be applied according to a process to generate a desired burn-in voltage.

When a very high external supply voltage (EVC) is applied to enter burn-in mode, very high overstress or even breakdown is applied to the transistors serving as the chip-to-chip interface using the external supply voltage (EVC). Is likely to be.

It is therefore an object of the present invention to provide an internal power supply voltage generating circuit for ensuring that the external power supply voltage for the burn-in voltage of the required level is not too high.

1 is a circuit diagram showing an internal power supply voltage generation circuit according to the prior art;

2 is a view showing a relationship between an external power supply voltage and an internal power supply voltage according to an operation mode;

3 is a block diagram showing a configuration of an internal power supply voltage generating circuit according to the present invention;

4 is a circuit diagram showing an internal power supply voltage generating circuit according to a first preferred embodiment of the present invention;

5 is a view showing a relationship between an internal power supply voltage and an external power supply voltage according to a burn-in test mode and a normal operation mode;

6 is a circuit diagram showing an internal power supply voltage generation circuit according to a second preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: high voltage detection circuit 120: reference voltage generation circuit

140: reference voltage conversion circuit 160: internal voltage generation circuit

180: level shifter

(Configuration)

According to one aspect of the present invention for achieving the above object, a semiconductor memory device comprising: an internal having an external power supply voltage and having a lower level and a constant level than the external power supply voltage according to a level of a first reference voltage. An internal voltage generator circuit for generating a power supply voltage; Accepts an external voltage for informing the burn-in test mode, and outputs a high voltage detection signal that detects whether the external voltage is a high voltage having a higher level than the internal power supply voltage, and is activated when the external voltage is high voltage A high voltage detection circuit for outputting a high voltage detection signal; A reference voltage generation circuit connected to the high voltage detection circuit, for converting an external power supply voltage into a second reference voltage when the high voltage detection signal is deactivated, which becomes a reference for internal circuits provided to the semiconductor memory device; A reference voltage converting circuit connected to said reference voltage generating circuit and converting said second reference voltage to a level corresponding to a first reference voltage provided to said internal voltage generating circuit; When the high voltage detection signal is activated, each level of voltages respectively output from the reference voltage generator circuit, the reference voltage converter circuit, and the internal voltage generator circuit increases according to the level of the external power supply voltage.

In this embodiment, it is connected to said high voltage detection circuit, and further includes a level shifter for converting the level of the said high voltage detection signal into the level of the said external power supply voltage, The said reference voltage generation circuit is the said external power supply. A first power supply terminal for receiving a voltage; A second power supply terminal for receiving a ground potential; A first resistor connected to one terminal of the first power supply terminal; A second resistor having one end connected to the other terminal of the first resistor; First and second NMOS transistors having current paths sequentially formed in series between the other terminal of the second resistor and the second power supply terminal; A gate of the first NMOS transistor is connected to a node to which the first and second resistors are commonly connected, and a gate of the 2 NMOS transistor is connected to the high voltage detection circuit; A first PMOS transistor having a current path formed between the common connection node and the second power supply terminal and a gate connected to the drain of the first NMOS transistor; And a second PMOS transistor having a current path formed between the first power supply terminal and the common connection node and a gate connected to an output of the level shifter.

In this embodiment, the reference voltage generating circuit includes: a first power supply terminal for receiving the external power supply voltage; A second power supply terminal for receiving a ground potential; A first resistor connected to one terminal of the first power supply terminal; A second resistor having one end connected to the other terminal of the first resistor; First and second NMOS transistors having current paths sequentially formed in series between the other terminal of the second resistor and the second power supply terminal; A gate of the first NMOS transistor is connected to a node to which the first and second resistors are commonly connected, and a gate of the 2 NMOS transistor is connected to the high voltage detection circuit; And a PMOS transistor having a current path formed between the common connection node and the second power supply terminal and a gate connected to the drain of the first NMOS transistor.

According to another aspect of the invention, in a semiconductor memory device: an internal voltage generation circuit for receiving an external power supply voltage and generating an internal power supply voltage having a lower level and a constant level than the external power supply voltage according to a level of a first reference voltage. Wow; Outputs a high voltage detection signal that detects whether the first voltage is a high voltage having a higher level than the internal power supply voltage by receiving a first voltage for indicating a burn-in test mode, and when the first voltage is a high voltage A high voltage detection circuit for outputting the high voltage detection signal that is activated; A level shifter connected to said high voltage detection circuit for converting a level of said high voltage detection signal into a level of said external power supply voltage; A reference voltage generating circuit connected to said level shifter for converting an external power supply voltage into a second reference voltage when said high voltage detection signal is deactivated, which becomes a reference for internal circuits provided to said semiconductor memory device; A reference voltage converting circuit connected to said reference voltage generating circuit and converting said second reference voltage to a level corresponding to a first reference voltage provided to said internal voltage generating circuit; When the high voltage detection signal is activated, each level of voltages respectively output from the reference voltage generator circuit, the reference voltage converter circuit, and the internal voltage generator circuit increases according to the level of the external power supply voltage.

(Action)

With such a device, the internal power supply voltage, which is the output of the internal power supply voltage generator circuit, becomes equal to the external power supply voltage so that the desired burn-in voltage can be increased without excessively increasing the external power supply voltage to set the burn-in voltage required for burn-in test. Supply external power voltage as much as.

(Example)

Reference will now be made in detail with reference to FIGS. 3 to 6 according to an embodiment of the present invention.

In the following description, specific details of the circuit are given by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

3 is a block diagram showing the configuration of an internal power supply voltage generation circuit according to the present invention.

Referring to FIG. 3, an internal power supply voltage generating circuit according to the present invention may include a high voltage detecting circuit 100, a reference voltage generating circuit 120, and a reference voltage converting circuit. converting circuit 140 and internal voltage generating circuit 160. An example of a detailed circuit for this is shown in FIG. 4. In FIG. 4, since it has the same circuit configuration as the reference voltage converting circuit 140 and the internal voltage generating circuit 160 of FIG. 1, the description thereof is omitted here.

Referring back to FIG. 4, the high voltage detection circuit 100 is for detecting whether the voltage applied to the pad PAD from the outside has a high voltage level. Therefore, when a high voltage is applied to the pad PAD to enter the burn-in test mode, the high voltage detection circuit 100 detects the high voltage and generates a high voltage detection signal SVDT. The high voltage detection signal SVDT is at a low level in normal operation and at a high level in burn-in test mode.

The reference voltage generator circuit 120 consists of two resistors 26 and 28, two NMOS transistors 30 and 32, and one PMOS transistor 34. The resistors 26 and 28 are connected in series between the drain of the NMOS transistor 30 arranged close to the external power supply voltage EVC and the external power supply voltage EVC.

The current paths of the transistors 30 and 32 are sequentially formed in series between the resistor 28 and the ground potential. The gate of the transistor 32 is controlled by the high voltage detection signal SVDT applied through the inverters 20 to 24, and the gate of the transistor 30 is the connection point N1 of the resistors 26 and 28. ) The current path of the PMOS transistor 34 is formed between the connection point N1 and the ground potential, and its gate is connected to the drain of the NMOS transistor 30.

According to this circuit configuration, when a high voltage for informing the burn-in test mode is applied to the pad PAD, a high level high voltage detection signal SVDT is generated from the high voltage detection circuit 100. Accordingly, the low voltage high voltage detection signal SVDT via the inverters 20 to 24 deconducts the NMOS transistor 32 of the reference voltage generator circuit 120. As a result, the outputs of the circuits 120, 140, and 160 all have the same level as the level of the external power supply voltage EVC. That is, the internal power supply voltage IVC is stepped up along the level of the external power supply voltage EVC, and as a result, the burn-in voltage required in the burn-in test mode is output. 5 is a diagram illustrating a relationship between an internal power supply voltage and an external power supply voltage according to a burn-in test mode and a normal operation mode.

6 is a circuit diagram illustrating an internal power supply voltage generation circuit according to a second preferred embodiment of the present invention.

Referring to FIG. 6, the internal power supply voltage generation circuit according to the second embodiment includes a level shifter for switching the level of the high voltage detection signal SVDT provided from the high voltage detection circuit 100 to the level of the external power supply voltage EVC. And 180. Accordingly, the high voltage detection signal SVDT generated by the high voltage detection circuit 100 is provided to the reference voltage generation circuit 120 at the level of the external power supply voltage EVC through the level shifter 180. The reference voltage generator circuit 120 according to the second embodiment has the same configuration as that of FIG. However, it further includes a PMOS transistor 64 turned on / off by the level shifter 180. Since the configuration of the second embodiment including the level shifter 180 described above has the same configuration as that of the first embodiment, it is omitted here to avoid duplication of description.

As described above, as can be seen in the first and second embodiments, when a very high voltage is applied to an existing input pin without using a separate option pin during burn-in test of the packaged product, The detected signal SVDT may control the reference voltage generator circuit 120 to enter the burn-in mode. That is, when a high voltage is applied to a specific pin, the detection signal SVDT controls the reference voltage generating circuit 120 to boost the output voltage thereof by the external power supply voltage EVC. Therefore, the internal power supply voltage IVC, which is the output of the internal power supply voltage generator circuit, becomes equal to the external power supply voltage EVC, so that the external power supply voltage EVC is excessively increased for setting the burn-in voltage required for the burn-in test. You do not need to supply an external supply voltage (EVC) as much as you want.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, even if the external power supply voltage is not excessively increased during the burn-in test operation, the burn-in voltage of a desired level may be provided to the internal circuit including the memory cell array of the semiconductor memory device.

Claims (4)

In a semiconductor memory device: An internal voltage generation circuit which receives an external power supply voltage and generates an internal power supply voltage having a lower level and a constant level than the external power supply voltage according to the level of the first reference voltage; Accepts an external voltage for informing the burn-in test mode, and outputs a high voltage detection signal that detects whether the external voltage is a high voltage having a higher level than the internal power supply voltage, and is activated when the external voltage is high voltage A high voltage detection circuit for outputting a high voltage detection signal; A reference voltage generation circuit connected to the high voltage detection circuit, for converting an external power supply voltage into a second reference voltage when the high voltage detection signal is deactivated, which becomes a reference for internal circuits provided to the semiconductor memory device; A reference voltage converting circuit connected to said reference voltage generating circuit and converting said second reference voltage to a level corresponding to a first reference voltage provided to said internal voltage generating circuit; When the high voltage detection signal is activated, each level of voltages respectively output from the reference voltage generator circuit, the reference voltage converter circuit, and the internal voltage generator circuit increases in accordance with the level of the external power supply voltage. . The method of claim 1, A level shifter connected to the high voltage detection circuit, the level shifter for converting a level of the high voltage detection signal into a level of the external power supply voltage, wherein the reference voltage generating circuit is configured to receive the external power supply voltage. 1 power terminal; A second power supply terminal for receiving a ground potential; A first resistor connected to one terminal of the first power supply terminal; A second resistor having one end connected to the other terminal of the first resistor; First and second NMOS transistors having current paths sequentially formed in series between the other terminal of the second resistor and the second power supply terminal; A gate of the first NMOS transistor is connected to a node to which the first and second resistors are commonly connected, and a gate of the 2 NMOS transistor is connected to the high voltage detection circuit; A first PMOS transistor having a current path formed between the common connection node and the second power supply terminal and a gate connected to the drain of the first NMOS transistor; And a second PMOS transistor having a current path formed between the first power supply terminal and the common connection node and a gate connected to an output of the level shifter. The method of claim 1, The reference voltage generator circuit includes a first power supply terminal for receiving the external power supply voltage; A second power supply terminal for receiving a ground potential; A first resistor connected to one terminal of the first power supply terminal; A second resistor having one end connected to the other terminal of the first resistor; First and second NMOS transistors having current paths sequentially formed in series between the other terminal of the second resistor and the second power supply terminal; A gate of the first NMOS transistor is connected to a node to which the first and second resistors are commonly connected, and a gate of the 2 NMOS transistor is connected to the high voltage detection circuit; And a PMOS transistor having a current path formed between the common connection node and the second power supply terminal and a gate connected to the drain of the first NMOS transistor. In a semiconductor memory device: An internal voltage generation circuit which receives an external power supply voltage and generates an internal power supply voltage having a lower level and a constant level than the external power supply voltage according to the level of the first reference voltage; Outputs a high voltage detection signal that detects whether the first voltage is a high voltage having a higher level than the internal power supply voltage by receiving a first voltage for indicating a burn-in test mode, and when the first voltage is a high voltage A high voltage detection circuit for outputting the high voltage detection signal that is activated; A level shifter connected to said high voltage detection circuit for converting a level of said high voltage detection signal into a level of said external power supply voltage; A reference voltage generating circuit connected to said level shifter for converting an external power supply voltage into a second reference voltage when said high voltage detection signal is deactivated, which becomes a reference for internal circuits provided to said semiconductor memory device; A reference voltage converting circuit connected to said reference voltage generating circuit and converting said second reference voltage to a level corresponding to a first reference voltage provided to said internal voltage generating circuit; When the high voltage detection signal is activated, each level of voltages respectively output from the reference voltage generator circuit, the reference voltage converter circuit, and the internal voltage generator circuit increases in accordance with the level of the external power supply voltage. .