JPH02228810A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To obtain a multiplied output signal with an optional pulse width by providing a delay circuit retarding an input signal whose delay quantity is variable and an EX-NOR gate receiving the input signal and an output signal of the delay circuit and outputting an output signal being a multiple of the input signal. CONSTITUTION:The circuit consists of a delay circuit 2 retarding an input signal (a) with a reference voltage 5, an nMOS transistor(TR) and a capacitor C and an EX-NOR gate 3 doubling the frequency of the input signal (a). When the reference voltage 5 is small, the equivalent resistance of the TR is increased, the delay time is increased, the time when the input signal (a) and an output signal (b) are coincident is decreased, and a multiple output signal (c) is obtained at an output terminal 4 while the time of 'L' is longer than 'H'. Thus, even when the LSI manufacture process, the ambient temperature and the power voltage are fluctuated, the multiple output signal (c) with an optional pulse width is obtained by varying the reference voltage 5.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplier circuit.

[Conventional technology]

Conventionally, this type of multiplier circuit has a plurality of inverters (IV1 to IV1 to
The input signal and the output signal of the delay circuit 6 are both 1 high or 1 low, as shown in the operation waveform diagram (to) shown in Figure 4. When the input signal is 1 high, the output signal of the delay circuit 6 is 10-, or the input signal is 10-, and the output signal of the delay circuit 6 is 1 high. When - does not match, the output signal becomes ・90-", which almost doubles the frequency of the input signal? ) EX-NOR gate 3.

[Problem to be solved by the invention]

The above-mentioned conventional multiplier circuit has a configuration that includes a circuit that fixes the amount of delay by connecting inverters in series to delay the input signal. Therefore, fluctuations in the SI manufacturing process, environmental temperature, and power supply voltage can affect the delay of the inverter. This has the disadvantage that it directly affects the amount of pulse width and appears as a variation in pulse width, and as a result, a large amount of variation in pulse width must be taken into account during design.

[Means to solve the problem]

The multiplier circuit of the present invention multiplies the input signal by using a delay circuit with a variable delay amount that delays an input signal, a reference voltage that controls the delay amount, and the input signal and the output signal of the delay circuit as two inputs. It has an EX-NOR gate that outputs an output signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are a circuit diagram and an operation waveform diagram showing an embodiment of the present invention, respectively.

1 and 2, this embodiment uses a predetermined input signal a as a reference voltage (vr) 5 and an nMOS transistor (T
) and a delay circuit 2 that is delayed by a capacitor (C)
, the input signal a and the output signal of the delay circuit 2 are both high (hereinafter referred to as H) as shown in the operating waveform diagram shown in FIG.
When the output signal C is "H'/", the output signal of the delay circuit 2 is "L", or the input signal a is "L". When the output signals of the delay circuit 2 do not match, the output signal C becomes ks I, J/
EX-N, which almost doubles the frequency of input signal a
It consists of OR gate 3.

Note that the nMO8) transistor (Tr) has a reference voltage (Vr).
5, the delay time of the input signal a can be controlled by the time constant with the capacitor (C).

When the reference voltage (Vr) 5 is large, the equivalent resistance value of the nMOS transistor (Tr) becomes small and the delay time t also becomes small. By reducing the output delay of delay circuit 2. The time period during which the input signal a and the output signal of the delay circuit 2 match becomes longer, and the voltage at the output terminal 4 becomes V″H″ rather than V″L″.
A multiplied output signal C having a long time is obtained. Conversely, when the reference voltage (Vr) 5 is small, the nMOS transistor (Tr)
The equivalent resistance value becomes larger, and the delay time becomes larger.

As the output delay of the delay circuit 2 increases, the time during which the input signal a and the output signal of the delay circuit 2 match becomes shorter, and the output terminal 4 receives a multiplied output signal whose time is longer at 9L than at "H". As a result, the reference voltage (Vr) can be maintained even if the original voltage changes due to the LSI manufacturing process, environmental temperature, etc.
By changing 5, a multiplied output signal C having an arbitrary pulse width can be obtained.

〔Effect of the invention〕

As described above, the present invention provides an LSI manufacturing process by configuring the output delay time of an input signal delay circuit to be controlled by a reference voltage.

This has the effect of being able to obtain a multiplied output signal with an arbitrary pulse width without being affected by fluctuations in environmental temperature or power supply voltage.

[Brief explanation of the drawing]

1N and 2 are a circuit diagram and an operating waveform diagram showing an embodiment of the present invention, respectively, and FIGS. 3 and 4 are a circuit diagram and an operating waveform diagram, respectively, of a conventional multiplier circuit. l...Input terminal, 2...Delay circuit, 3
...EX-NOR gate, 4...Output terminal, 5...Reference voltage (Vr), 6...
...Delay circuit, Tr...nMO8) transistor, C...capacitor, fV, ~IV4...
...Inverter. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A delay circuit with a variable delay amount that delays an input signal, a reference voltage that controls the delay amount, and an EX that uses the input signal and the output signal of the delay circuit as two inputs and outputs an output signal that is a multiple of the input signal. - a NOR gate.