JPH04170791A - Asynchronous type memory circuit - Google Patents

Abstract

PURPOSE:To eliminate a complicated work such as circuit design, etc., and to shorten a developing time by setting a delay time of a circuit made of an active circuit element having properties for simply reducing the delay time in response to the rise of a supply power source voltage to an optimum delay time. CONSTITUTION:A resistance element 2 is newly provided as a composing content of an address transfer detector ATD, a power source voltage is applied to the element 2 by a power source terminal 51, and supplied to delay circuits I-1 - n through the lead terminal of the element 2. Thus, the power supplied to the circuits I-1 - n is supplied from the terminal of the element 2, and the position of the terminal of the element 2 is regulated. Thus, the delay times of the circuit I-1 - n formed of active circuit elements having properties for simply reducing the delay time in response to the rise of the power source voltage can be set to the optimum delay time to a memory configuration of various bit lengths and word lengths required for a standard cell type LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous memory circuit, and more particularly to an asynchronous memory circuit using a standard cell design method.

[Conventional technology]

Asynchronous memory circuits based on the conventional standard cell design method mainly use an address transition detection circuit (Address transition detection circuit) that detects changes in input address signals.
Transition Detector: Below,
(abbreviated as an ATD circuit) and a synchronous memory circuit.

The circuit diagram of the conventional asynchronous memory circuit is shown in the second example.
As shown in the figure, a plurality of address input terminals 58-1
~n (n is a positive integer) corresponding delay circuit l-1
~n, the ATD circuit including EXOR circuits 3-1 to 3-n, NMOS transistors 4-1 to n, and PMOS transistor 5, and NMO3)-transistors 4-1 to n that form the output terminals of this ATD circuit. drain and PM
and a synchronous memory circuit 6 connected to a connection point with the drain of the OS transistor 5.

Note that the synchronous memory circuit 6 usually has an address input section,
It is composed of a decoder section, a memory cell array section, a column selector section, a read circuit section, a write circuit section, etc. However, since the section targeted by the present invention is in the above-mentioned ATD circuit, the synchronous memory circuit is A detailed explanation will be omitted below.

As shown in FIG. 2, in the conventional ATD circuit, the power supply voltage is supplied from a single power supply terminal 57 to the delay circuits 1 and 1, each of which is composed of active circuit elements including inverters.
-1 to n, EXOR circuits 3-1 to n and PMOS)-
It is commonly supplied to the sources of the transistors 5.

In FIG. 2, the address input terminal 58- of the ATD circuit is
Address signals corresponding to write/continue output to the synchronous memory circuit 6 are inputted from 1 to n, respectively. The delay times of delay circuits 1-1 to 1-n included in the address transition detection circuit are set corresponding to the access time for writing or reading data in the synchronous memory circuit 6, and the delay times of each are the same. be.

In the initial state of the ATD circuit, the address signal does not change, so for example, when an address signal is input to the address input terminal 58-1, it is output from the corresponding delay circuit 1-1 and input to the EXOR circuit 3-1. The address signal input directly from the address input terminal 58-1 to the EXOR circuit 3-1 coincides in time, and therefore the output of the EX''OR circuit 3-1 becomes ``L''. ”
Output as a level signal, NMO3) transistor 4
-1 gate. In the NMO'S transistor 4-1, in response to this "L" level signal input, the NMOS transistor 1 enters the rOFFJ state, and the output of the ATD circuit is output via the drain of the PMOS transistor 5. The signal is then input to the synchronous memory circuit 6 as an rH, level signal. The synchronous memory circuit 6 does not operate in response to the above-mentioned rH, level signal input. Therefore, when there is no change in the address signal, no data is written or read in the synchronous memory circuit 5.

Next, when the address signal changes, the EXOR circuit 3
Since the two address signals input to -1 are different signals, the output of the EXOR circuit 3-1 becomes rH, level, and the NMO3) transistors 4 to 1 become rONJ, so the output of the ATD circuit becomes "L". ” level,
This signal is input as an internal clock to the synchronous memory circuit 6, and the synchronous memory circuit 6 becomes operational.

On the other hand, in the synchronous memory circuit 6, address signals corresponding to writing and reading, write/read control signals, input data to be written, etc. are input from the address input terminal 59, control input terminal 60, and data input terminal 61, respectively. When predetermined data is stored in the synchronous memory circuit 6, the internal clock is input from the address input terminal 59 and the control input terminal 60 only when the internal clock is input from the ATD circuit. Data input from data input terminal 61 is written to synchronous memory circuit 6 via an address signal and a write control signal.

Further, when reading predetermined data from the synchronous memory circuit 6, only when the internal clock is input from the ATD circuit, the address signals input from the address input terminal 59 and the control input terminal 60, respectively, and Data output terminal 6 via read control signal
Predetermined data is read from 2.

That is, the address input terminal 58-1 in the ATD circuit
Only when there is a change in the address signal input from ~n, the synchronous memory circuit operates according to the internal clock output from the ATD circuit, and writes or reads predetermined data in response to the address signal. will be held.

[Problem to be solved by the invention]

Generally, in an ATD circuit of an asynchronous memory circuit, the delay time of delay circuits 1-1 to 1-n included in the address detection circuit is set to match the access time corresponding to writing or reading data in a synchronous memory circuit. However, regarding the setting of this delay time, the bit length and
It is necessary to perform circuit design and layout design so as to have an optimal time length in accordance with the word length configuration, etc., and there is a drawback that the extension of these design periods increases the development period and development cost.

[Means to solve the problem]

The asynchronous memory circuit of the present invention includes a group of active delay circuits that receive an address signal corresponding to write/read and generate an address change signal with a fixed time width, and a group of EXOR circuits corresponding to each of the delay circuits. , a transistor group including a plurality of first transistors each having a gate electrode connected to the output end of the EXOR circuit and having a drain electrode commonly connected; and a drain electrode to which the plurality of first transistors are commonly connected. A second transistor outputs a predetermined clock signal from the commonly connected drain electrode, and a lead-out terminal for taking out a power supply voltage, and a predetermined voltage power supply is applied to both ends. and a resistive element that supplies the voltage output from the extraction terminal as a power supply voltage to the active delay circuit group through the position adjustment action of the extraction terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment has a plurality of address input terminals 5.
Delay circuits 1-1 to 1-n and E corresponding to 2-1 to 2-n, respectively
An ATD circuit including XOR circuits 3-1 to 3-n and NMO3) - transistors 1 to n, PMO8), transistor 5, and resistor element 2, and NMOS transistors 4-1 to 4-1 that form output terminals of this ATD circuit. drain of n and P
A synchronous memory circuit 6 is connected to a connection point with the drain of the MOS transistor 5.

As shown in FIG. 1, the difference between this embodiment and the conventional example is that the above-mentioned ATD circuit is provided with a new resistance element 2 compared to the structure of the conventional example. 2, a power supply voltage is applied from the power supply terminal 51, and the power supply voltage is applied to the delay circuit 1 via the lead terminal of the resistor element 2.
−1 to n.

In this way, by supplying the power to the delay circuits 1-1 to 1-n through the lead terminals of the resistor element 2 and adjusting the position of the lead terminals of the resistor element 2, as the supply power voltage increases, The delay times of delay circuits 1-1 to 1-n formed by active circuit elements whose delay time monotonically decreases are determined by memory configurations with various bit lengths and word lengths required in standard cell type LSIs. The delay time can be set to the optimum value.

Note that the basic operation of the asynchronous memory circuit including the ATD circuit and the synchronous memory circuit in this embodiment is exactly the same as that in the conventional example described above.

〔Effect of the invention〕

As explained above, the present invention supplies power to the delay circuit included in the ATD circuit through a resistor element having a lead terminal, thereby adjusting the position of the lead terminal, thereby achieving a standard-cell type. LSI
By controlling and adjusting the voltage of the power supply to the delay circuit and setting the delay time of the delay circuit to the optimal value, the circuit design This also has the effect of eliminating complicated work such as layout design and reducing development time and development costs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. In the figure, 1-1 to n...delay circuits, 2...
...Resistance element, 3-1~n...EXOR circuit, 4-1~n...NMOS transistor, 5
...PMO3) transistor,6...synchronous memory circuit.

Claims (1)

[Scope of Claims] A group of active delay circuits that receives an address signal corresponding to writing/reading and generates an address change signal with a fixed time width, a group of EXOR circuits corresponding to each of the delay circuits, and the EXOR circuit. A transistor group including a plurality of first transistors each having a gate electrode connected to an output end of the circuit and a common drain electrode connected to the plurality of first transistors; are connected to each other, and output a predetermined clock signal from the commonly connected drain electrodes.
transistor, and a lead-out terminal for taking out the power supply voltage, a predetermined voltage power is applied to both ends, and the voltage output from the lead-out terminal is controlled by the active delay through the position adjustment action of the lead-out terminal. An asynchronous memory circuit comprising: a resistance element that supplies a power supply voltage to a group of circuits; and an address transition detection circuit comprising: