JPH0410807A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To make a clock frequency variable by constituting an inverting circuit of a comparator, and making the hysteresis width variable. CONSTITUTION:The output from an output terminal is inputted to the inverting terminal of a comparator 3 being an inverting means via a delay line 2 being a delay means. The noninverting input of the comparator 3 is connected to ground via a variable resistor 4, and a resistor 5 is interposed between the output of the comparator and the noninverting input of the comparator. Moreover, a hysteresis is provided to the comparator 3 by using the resistor 5 and the variable resistor 4, and the width of the hysteresis is varied by varying the variable resistor 4. Thus, a change in a characteristic impedance is eliminated regardless of simple constitution and the clock frequency is made variable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal generation circuit, and relates to a clock signal generation circuit that can be used, for example, in a waveform storage device such as a digital storage oscilloscope.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a conventional clock signal generation circuit.

The figure shows a feedback circuit consisting of an inverting circuit and a delay circuit, and includes a signal inverting means 10 that is enabled by a trigger signal and inverts an input signal, and a signal inverting means 10 that delays the output signal of the signal inverting means by a variable delay time. A delay means 2 which feeds back the input signal to the inverting means is known (see Japanese Patent Laid-Open No. 62-207025).

As the delay means 2, for example.

A variable delay circuit as disclosed in Japanese Patent Laid-Open No. 60-233912 is used.

In the clock signal generating circuit having such a configuration, a tarok signal having a period corresponding to the delay time set in the delay means 2 is outputted from the OUT terminal in the figure.

[Problem to be solved by the invention]

However, in the prior art described above, the variable delay circuit includes a plurality of inductors connected in series between input and output terminals, and a capacitive element connected between each connection point of the inductors and ground, and the capacitive element is a capacitor. The delay time can be continuously adjusted by applying a control voltage to the connection point between the variable capacitance diode and the capacitor via a resistor.

Therefore, when adjusting the delay time, there is a problem that matching of the terminated transmission lines cannot be achieved due to a change in characteristic impedance due to a change in the capacitance of the capacitor.

Further, the variable delay circuit uses a large number of components as described above, and has a complicated configuration.

Therefore, the present invention has been made based on these circumstances, and its purpose is to eliminate the change in characteristic impedance and vary the clock frequency, despite the extremely simple configuration. The object of the present invention is to provide a clock signal generation circuit that can perform the following functions.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a clock signal generation circuit basically consisting of an inverting circuit and a feedback circuit of a delay circuit, wherein the inverting circuit consists of a comparator, and the comparator has is characterized in that it is provided with means for varying the hysteresis width.

[Effect]

In this way, the inverting circuit is configured by a comparator,
By providing this comparator with means for varying the hysteresis width, the clock frequency of the clock signal can be varied in accordance with the variation of the hysteresis width.

Further, since varying the bisteresis width of the comparator does not change the capacitance as in the conventional case, the characteristic impedance does not change.

Furthermore, the configuration also eliminates the need for a large number of parts.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

FIG. 1 is a block diagram showing one embodiment of a clock signal generator according to the present invention.

AN where one terminal into which the trigger signal is input is input terminal A
There is a D circuit 1 whose output terminal is an OUT terminal, and the output from the output terminal is sent to a comparator 3 which is an inverting means via a delay line 2 which is a delay means.
It is designed to be input to one terminal of the . A child terminal of this comparator 3 is grounded via a variable resistor 4, and a resistor 5 is interposed between it and the output terminal.

The resistor 5 and variable resistor 4 thereby provide the comparator 3 with hysteresis, and by varying the variable resistor 4, the width of the hysteresis can be varied.

The output from the output terminal of the comparator 3 is input to another input terminal of the AND circuit 1.

In the clock signal generation circuit having such a configuration, when the signal from the input terminal A reaches the 11 HI+ level, the output of the AND circuit 1 becomes "L I+ level → 11 HI
Change to T level. The output of the front EAND circuit 1 is delayed via a delay line 2, and this delayed output is input to the comparator 3. As a result, when the input B of the comparator 3 changes to the "H" level, the output C of the comparator 3 becomes N L
I'' level starts to change.The output C becomes ``L''
When the level changes, the output of the AND circuit 1 is "1L"
become the level.

By repeating the above operations, an oscillated signal as a clock signal is obtained from the OUT terminal, which is the output terminal of the AND circuit 1.

Here, the comparator 3 is provided with hysteresis by a resistor 5 and a variable resistor 4, and by varying the variable resistor 4, the width of the hysteresis can be varied.

FIG. 2 shows a signal waveform diagram of each part in such a configuration and operation. Note that the B signal and C signal in the figure correspond to the B signal and C signal in FIG. 1, respectively.

In the figure, ■ indicates the total amount of delay when the signal passes through both the AND circuit 1 and the delay line 2. In this figure, the rise time of the signal waveform,
and the fall time is shown enlarged. Figure (a)
1 shows a case where the hysteresis width is large, and FIG. 2B shows a case where the hysteresis width is small. The same figure (a
) and (b) in the figure, after the output C from the comparator 3 falls, the output B falls after a delay shown by ■ in the figure.

In this case, the timing at which the output C from the comparator 3 changes varies depending on the difference in the voltages applied to the child terminals of the comparator 3. The larger the hysteresis width, the slower the timing at which the output C changes.

Next, when the output C rises, the output B similarly rises after the amount of delay shown by ■ in the figure. However, in this case, the timing of the output C differs as described above due to the difference in the voltages applied to the child terminals of the controller 3.

As is clear from this, by varying the hysteresis width of the comparator 3, the clock frequency can be varied.

FIG. 3 is a block diagram showing another embodiment of the clock signal generation circuit according to the present invention. The basic configuration is the same as that shown in FIG. The value F is output.

On the other hand, instead of the variable resistor 4 shown in FIG.
There is a MOSFET T8, and the gate of this MOSFET8 has the above-mentioned D
An analog value F corresponding to the count value from the /A conversion circuit 7 is applied.

By doing this, the MO8FET8 becomes
It comes to function equivalent to the variable resistor 4 in FIG.

As described above, according to this embodiment, it is possible to vary the clock frequency without changing the delay amount of the delay line 2. Therefore, it becomes possible to use a distributed constant type delay line with good stability, and it becomes unnecessary to use a large number of parts required to change the delay amount of the delay line.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As is clear from the above description, the clock signal generation circuit according to the present invention makes it possible to eliminate changes in characteristic impedance and vary the clock frequency, despite having an extremely simple configuration.

[Brief explanation of drawings]

1 is a block configuration diagram showing an embodiment of a clock signal generation circuit according to the present invention; FIGS. 2(a) and 2(b) are signal waveform diagrams of each part in the block configuration diagram of FIG. 1; FIG. 4 is a block diagram showing another embodiment of the clock signal generation circuit according to the present invention, and FIG. 4 is a block diagram showing an example of the conventional clock signal generation circuit. In the figure, 1...ADN circuit, 2...delay line. 3... Comparator, 4... Variable resistor, 5... Resistor, 6... Frequency counter, 7... D/A conversion circuit,
8...MOSFET, 9...Microcomputer, 10...NAND circuit.

Claims (1)

[Claims] (1) In a clock signal generation circuit composed of an inverting circuit and a feedback circuit using a delay circuit, the inverting circuit is composed of a comparator, and the comparator is provided with means for varying its hysteresis width. A clock signal generation circuit characterized in that: